CN1393936A - Flash memory structure - Google Patents

Abstract

The structure of the flash memory includes one tunneling oxide layer, one floating grid, one dielectric lamination layer and one area of the control grid and the source/drain area. The dielectric lamination is a stack, positioned between the floating grid and the control grid, and composed of one first oxide layer, one layer of the dielectric layer amde from the material with high dielectric constant and one layer of the second oxide layer in sequence. The floating grid is positioned on the tunneling oxide layer. The control grid is positioned on the dielectric lamination. The source/drain areas are located on the substrate at the two sides of the floating grid. The invention can lower the magnitute of voltage needed to apply for operating the flash memory so as to reduce energy loss.

Description

A kind of structure of flash memory

The invention relates to a kind of structure of internal memory, particularly relevant for the structure of a kind of flash memory (FlashMemory).

Recently owing to the portable type electronic product Requirement Increases, the demand of flash memory obviously increases.Because its technology reaches its maturity, cost descends, and has not only stimulated purchase intention, and has new market to use.Recently the flash memory structure of development can electricity removes and programmable read only memory has had access speed faster.But the internal memory of the egative film of digital camera, individual accompanied electronic memo pad, individual MP3 walkman, electronics answer-recording device program IC or the like all are the market that flash memory is used.

Please refer to Fig. 1, it has provided a kind of structural profile of flash memory.This structure comprises 102, one of one deck tunnel oxides (Tunneling Oxide) control grid (Control Gate) 108, layer of oxide layer 110,104 and source/drain regions of floating grid (Floating Gate); Floating grid 104 is configured on the tunnel oxide 102; Oxide layer 110 is configured on the floating grid 104; Control grid 108 is configured on the oxide layer 110; 106 of source/drain regions are to be configured in floating grid 104 substrate on two sides 100.

When flash memory is programmed (Program), be added to source/drain region 106 respectively and control on the grid 108 with suitable program voltage, electronics will flow to drain region 106 via channel (Channel) by source area 106.In this process, to there be electronics partly can pass the tunnel oxide 102 of 104 layers of below of compound crystal silicon floating grid, enter and be evenly distributed in the whole floating grid 104, this electronics passes through the phenomenon that tunnel oxide 102 enters floating grid 104, is called tunneling effect (Tunneling Effect).

Tunneling effect can be divided into two kinds of situations, and a kind of channel hot electron that is called is injected (ChannelHot-Electron Injection), and another kind is called Fowler-Nordheim tunnelling (F-NTunneling).Usually flash memory is with the channel hot electron programming, and wears then with Fowler-Nordheim by source electrode next door or channel region and to erase.But, if the tunnel oxide defectiveness (Weak Point) of floating grid below exists, then cause the leakage current of assembly easily, influence the reliability of assembly.

In order to solve the flash memory component leakage problem, the present practice is to utilize silicon oxide/silicon nitride/silicon oxide (Oxide-Nitride-Oxide is called for short ONO) stacking-type (Stacked) structure that composite bed constituted as the dielectric layer between floating grid and the control grid.

Because the silicon nitride layer in the ONO dielectric layer has the effect of catching electric charge, so the electronics of injecting in the ONO layer can't be evenly distributed in the whole silicon nitride, but concentrate on the regional area of silicon nitride in the mode of Gaussian Profile, therefore, susceptibility for its defective of oxide layer is less, and the phenomenon of assembly leakage current is difficult for taking place.

In addition, when the advantage of ONO dielectric layer also was included in component programming, electronics only can store locally near the channel above source electrode or the drain electrode.Therefore, when programming, can be respectively to source/drain region applying voltage with gate pole, and in the silicon nitride layer that approaches other end source/drain region, produce the electronics of Gaussian Profile.So can be by changing the voltage that source/drain regions applies of grid and its both sides, can in single ONO dielectric layer, exist two electronics with Gaussian Profile, independent one to have the electronics of Gaussian Profile or do not have electronics.Therefore, this kind can write four kinds of states with the flash memory of silicon nitride material as dielectric layer in single memory cell, is the flash memory of two of a kind of single memory cells (1 cell 2bit).Yet, above-mentioned flash memory is when programming, need suitable program voltage to be added to source/drain region respectively and to control on the grid, and required magnitude of voltage can be along with the material of the dielectric medium of floating grid and control gate interpolar and is changed in this process, has been instant subject under discussion so how to reduce to the program voltage value minimum.

The structure that the purpose of this invention is to provide a kind of flash memory, so that the required magnitude of voltage reduction that applies of operation flash memory, and then reduce energy loss.

The invention provides a kind of structure of flash memory, its structure comprises one deck tunnel oxide, floating grid, one deck dielectric lamination, a control grid and a source/drain regions, wherein dielectric lamination is to be formed by the dielectric layer of one deck first oxide layer, one deck high dielectric constant material and one deck second oxide layer storehouse successively, and is configured between floating grid and the control grid; Floating grid is configured on the tunnel oxide; The control grid is configured on the dielectric lamination; Source/drain regions then is to be configured in the floating grid substrate on two sides.In addition, can be according to band gap (Band Gap) size of dielectric layer with high dielectric constant, whether decision is omitted in second oxide layer of dielectric layer with high dielectric constant and control gate interpolar, if the Band Gap of the BandGap of employed dielectric layer with high dielectric constant and silica is close or bigger, then can not comprise this second oxide layer; Otherwise, if the Band Gap of dielectric layer with high dielectric constant less than the Band Gap of silica, then need comprise this second oxide layer.The material of so-called high-k is meant the material of the dielectric constant higher than nitrogenize silicon/oxidative silicon (Si3N4/SiO2 also is called NO), is not to be regular noun; And band gap is meant two gaps of allowing between the electron energy band in metal and the semiconductor.In addition, because aluminium oxide has the feature of high-k and high band gap, so when the dielectric layer material is aluminium oxide, then do not need other oxide layer.

Because the present invention utilizes the material of dielectric layer with high dielectric constant as dielectric lamination, thus the required voltage that applies of operation flash memory is reduced, and then reduce energy loss.

Under be described with reference to the accompanying drawings embodiments of the present invention.

The section of structure of a kind of flash memory that Fig. 1 is.

Fig. 2 is the section of structure of a kind of flash memory of a preferred embodiment of the present invention.

Description of reference numerals:

100,200: substrate

102,202: tunnel oxide

104,204: floating grid

106,206: source/drain electrode

108,208: the control grid

110,212,216: oxide layer

210: dielectric lamination

214: dielectric layer with high dielectric constant

Embodiment

Please refer to Fig. 2, its structure comprises one deck tunnel oxide 202, control grid 208, floating grid 204, one once dielectric lamination 210 and a source/drain regions 206, and its relevant position is that floating grid 204 is positioned on the tunnel oxide 202; Dielectric lamination 210 is configured on the floating grid 204; Control grid 208 is to be configured on the dielectric lamination 210; 206 of source/drain regions are to be configured in floating grid 204 substrate on two sides 200.Wherein, dielectric lamination 210 is to be formed with one deck second oxide layer 216 storehouse successively by one deck first oxide layer 212, one dielectric layer 214, and the material of dielectric layer 214 is the materials with high-k (HighDielectric Constant).

And the material of the dielectric layer 214 in the dielectric lamination 210 has high-k (ε) for what is the need for, and just can reach the present invention and reduce the required voltage that applies when operating flash memory, and then reduce the purpose of energy loss.Its reason is that the voltage (representing with VTCS) that when the operation flash memory control grid is applied is with shown in the following formula (1) $V_{\mathrm{TCS}}=\frac{1}{\mathrm{GCR}}\×V_{\mathrm{TFS}}-\frac{Q}{C_c}---\left(1\right)$

GCR in the formula (1) representative be gate coupled than (Gate Coupling Ratio), it is worth as shown in the formula shown in (2) $\mathrm{GCR}=\frac{C_c}{C_T}=\frac{C_{\mathrm{ONO}}}{C_{\mathrm{Tox}+}{C}_{\mathrm{ONO}}}---\left(2\right)$

C in the formula (2) _ToxWhat represent is the electric capacity (Tunneling OxideCapacitance) of tunnel oxide; C _ONOWhat represent then is the electric capacity (ONO LayerCapacitance) of ONO dielectric layer.

Therefore from following formula (1) and formula (2) as can be known, apply voltage V if reduce _TCS, then the GCR value need be increased, and the GCR value will be increased, just must set about from the capacitance that improves dielectric layer.Again because the relational expression of electric capacity and dielectric constant (representing) with ε as shown in the formula shown in (3) $C=\mathrm{\ϵ}\×\frac{A}{d}---\left(3\right)$

So composite type (1), formula (2) and formula (3) will reduce applying voltage V _TCS, the just necessary dielectric constant that increases the dielectric layer 214 in the dielectric lamination 210 is operated the required voltage that applies of flash memory to reduce, and then is reduced energy loss.

First oxide layer 212 in the dielectric lamination 210 is the absorption affinities that are used for strengthening 214 of floating grid 204 and dielectric layer with high dielectric constant, and the generation that reduces defective (Defect).In addition, second oxide layer 216 in the dielectric lamination 210 is the absorption affinities that are used for strengthening 208 of dielectric layer with high dielectric constant 214 and the control grids on it, and reduces generation of defects.

The material of so-called high-k is meant permittivity ratio nitrogenize silicon/oxidative silicon (Si3N4/SiO2, also be called NO) the high material of dielectric constant, dielectric layer with high dielectric constant 2 14 can be aluminium oxide (Al2O3), yittrium oxide (Y2O3), zirconium silica (ZrSixOy), hafnium silica (HfSixOy), lanthanum sesquioxide (La2O3), zirconium dioxide (ZrO2), hafnium oxide (HfO2), tantalum pentoxide (Ta2O5), praseodymium oxide (Pr2O3) or titanium dioxide (TiO2), tabulating down one is the dielectric constant of above-mentioned dielectric layer, comprises Si3N4/SiO2 in addition, the dielectric constant of silica (SiO2) and silicon nitride (Si3N4).

Table one

Material	Dielectric constant	Material	Dielectric constant
				????SiO2	????2.9	??La2O3	????20
????Si3N4	????7.5	??ZrO2	????22
				??NO(Si3N4/SiO2)	????7～8	??HfO2	????25
????Al2O3	????10	??Ta2O5	????26
				????Y2O3	????12～14	??Pr2O3	????31
????ZrSixOy	????12～22	??TiO2	????80
				????HfSixOy	????15～25

As shown in Table 1, the dielectric constant of so-called high dielectric constant material need be higher than the dielectric constant values 8 of Si3N4/SiO2.In addition, the dielectric layer with high dielectric constant 214 of present embodiment can also be the mixture of above-mentioned each high dielectric constant material or the stack layer of above-mentioned each high dielectric constant material (Stack Layer).

In addition, according to band gap (BandGap) size of employed dielectric layer with high dielectric constant 214 materials, whether decision omits in dielectric lamination 210 in dielectric layer with high dielectric constant 214 and second oxide layer 216 of controlling 208 of grids.If the Band Gap of the Band Gap of employed dielectric layer with high dielectric constant 214 and silica is close or bigger, then can not comprise this second oxide layer 216; Otherwise, if the Band Gap of dielectric layer with high dielectric constant 214 less than the Band Gap of silica, then need comprise this second oxide layer 216.Tabulating down two is the band gap magnitude of employed dielectric layer 214 materials of present embodiment, comprises the band gap magnitude of silica (SiO2) and silicon nitride (Si3N4) in addition.

Table two

Material	Band gap (eV)	Material	Band gap (eV)
				??SiO2	????9	??La2O3	????4
??Si3N4	????5.3	??ZrO2	????7.8
				??Al2O3	????8.0	??HfO2	????6
??Y2O3	????5.6	??Ta2O5	????4.4
				?ZrSixOy	????6.5	??Pr2O3	????-
?HfSixOy	????6.5	??TiO2	????2.3

If the band gap of dielectric layer with high dielectric constant 214 is close with the silicon oxide layer of known use or bigger, then dielectric layer with high dielectric constant 214 can replace known second oxide layer 216 that is formed on the dielectric layer with high dielectric constant 214, and has identical effect.

In addition, from table one and table two as can be known, aluminium oxide has the dielectric constant higher than nitrogenize silicon/oxidative silicon, and the feature close with the band gap of silica, therefore with aluminium oxide during as the material of dielectric layer 214, therefore other oxide layer 212,216 in the alternative dielectric layer lamination 210 can be simplified the manufacture craft of flash memory.

In sum, the present invention utilizes the main material of dielectric layer with high dielectric constant as dielectric layer between control grid and floating grid, therefore can increase the gate coupled ratio, the required magnitude of voltage that applies of operation flash memory is reduced, and then reduce energy loss; If adopt aluminium oxide in addition as the dielectric layer material, not only can increase the gate coupled ratio, also can replace the effect of first and second oxide layer fully, and then simplify the manufacture craft of flash memory.

A preferred embodiment of the present invention openly as above, but it is not in order to limiting the present invention, any change in the present invention conceives scope all drops in protection scope of the present invention.

Claims (10)

1, a kind of structure of flash memory comprises: one deck tunnel oxide, and it is positioned in the substrate; A floating grid, it is positioned on this tunnel oxide; Layer of oxide layer, it is positioned on the floating grid; A control grid disposes on this oxide layer; And a source/drain region, it is positioned at this floating grid substrate on two sides, it is characterized in that: this oxide layer is a dielectric lamination, and this dielectric lamination comprises one deck first oxide layer, and it is positioned on the floating grid; One deck dielectric layer with high dielectric constant, it is positioned on first oxide layer; One deck second oxide layer, it is positioned on the dielectric layer with high dielectric constant.

2, the structure of flash memory according to claim 1 is characterized in that: the band gap magnitude of this dielectric layer with high dielectric constant is less than the band gap magnitude of silica.

3, the structure of flash memory according to claim 1 is characterized in that: the dielectric constant of this dielectric layer with high dielectric constant is greater than 8.

4, the structure of flash memory according to claim 1 is characterized in that: the material of this dielectric layer with high dielectric constant be selected from the mixture that group that aluminium oxide, yittrium oxide, zirconium silica, hafnium silica, lanthanum sesquioxide, zirconium dioxide, hafnium oxide, tantalum pentoxide, praseodymium oxide and titanium dioxide forms and above-mentioned substance form group one of them.

5, the structure of flash memory according to claim 1 is characterized in that: this dielectric layer with high dielectric constant be selected from stack layer group that aluminium oxide, yittrium oxide, zirconium silica, hafnium silica, lanthanum sesquioxide, zirconium dioxide, hafnium oxide, tantalum pentoxide, praseodymium oxide and titanium dioxide forms one of them.

6, a kind of structure of flash memory comprises: one deck tunnel oxide, and it is positioned in the substrate; A floating grid, it is positioned on this tunnel oxide; Layer of oxide layer, it is positioned on the floating grid; A control grid disposes on this oxide layer; And a source/drain region, it is positioned at this floating grid substrate on two sides, it is characterized in that: this oxide layer is a dielectric lamination, and this dielectric lamination comprises one deck first oxide layer, and it is positioned on the floating grid; One deck dielectric layer with high dielectric constant, it is positioned on first oxide layer.

7, the structure of flash memory according to claim 6 is characterized in that: the band gap magnitude of this dielectric layer with high dielectric constant is not less than the band gap magnitude of silica.

8, the structure of flash memory according to claim 6 is characterized in that: the material of this dielectric layer with high dielectric constant be selected from the mixture that group that aluminium oxide, yittrium oxide, zirconium silica, hafnium silica, lanthanum sesquioxide, zirconium dioxide, hafnium oxide, tantalum pentoxide, praseodymium oxide and titanium dioxide forms and above-mentioned substance form group one of them.

9, the structure of flash memory according to claim 6 is characterized in that: this dielectric layer with high dielectric constant be selected from stack layer group that aluminium oxide, yittrium oxide, zirconium silica, hafnium silica, lanthanum sesquioxide, zirconium dioxide, hafnium oxide, tantalum pentoxide, praseodymium oxide and titanium dioxide forms one of them.

10, a kind of structure of flash memory comprises: one deck tunnel oxide, and it is positioned in the substrate; A floating grid, it is positioned on this tunnel oxide; Layer of oxide layer, it is positioned on the floating grid; A control grid disposes on this oxide layer; And a source/drain region, it is positioned at this floating grid substrate on two sides, it is characterized in that: this oxide layer is one deck aluminum oxide dielectric layer, and it is positioned on this floating grid.

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