CN1387253A - High-density IC package structure and its method - Google Patents
High-density IC package structure and its method Download PDFInfo
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- CN1387253A CN1387253A CN02121825A CN02121825A CN1387253A CN 1387253 A CN1387253 A CN 1387253A CN 02121825 A CN02121825 A CN 02121825A CN 02121825 A CN02121825 A CN 02121825A CN 1387253 A CN1387253 A CN 1387253A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Microelectronics & Electronic Packaging (AREA)
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- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
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Abstract
The present invention relates to a structure of packaging integrated circuit and its forming method, especially to a structure of packaging integrated circuit in high density and its forming method. The metal having weld adhesive ability is used as the material of the first welding pad in the high density packaging integrated circuit and a shielding layer with high reliability is formed on the metal layer as the circuit in order to avoid the creating of defects in packaging integrated circuit, to increase the circuit density in the packaging integrated circuit, to simplify the manufacturing course, to increase the rate of the first class product and to raise the packaging reliability of integrated circuit.
Description
Technical field
The present invention relates to a kind of structure and formation method of structure dress integrated circuit, particularly a kind of high-density IC package structure and method thereof are to increase the circuit integration in the structure dress integrated circuit and to simplify processing procedure, reduce manufacturing cost, increase the product yield and improve the reliability that the integrated circuit structure is adorned.
Background technology
Integrated circuit generally needs framework within the structure package material, and the flat structure dress in four for example traditional limits (Quad Flat Package, QFP).Smooth assembling structure comprises a pin frame, and many lead-in wires that are contacted with integrated circuit (IC) chip (Chip) are arranged on pin frame.Chip is contained in one by structure has mechanical support to reach in the firm plastics that insulate with circuit, and lead-in wire mainly is to be welded on the printed circuit board (PCB).
In the past, the integrated circuit structure packing technique that integrated circuit manufacturer develops has out attempted to satisfy the requirement of microminiaturization.For the integrated circuit modification method of microminiaturization, be to make it on silicon base material, combination comprise millions of transistor circuit assemblies such as circuit, chip.The method of these improvement causes the method for structure dress circuit unit in limited space more to come into one's own.
Integrated circuit, is created in integrated device electronics through complicated technology such as etching, doping, deposition and cutting by a Silicon Wafer.One Silicon Wafer comprises an integrated circuit (IC) chip at least, and each chip is represented an independent integrated circuit.At last, this chip can be adorned by being enclosed in chip plastics encapsulating mixture (Molding Compound) structure all around, and has diversified stitch to expose and interconnected design.For example: M type dual inline type packaging housing (the M Dual-In-Line-Package that a quite smooth structure dress is provided; M-Dip), it has the parallel pin of two row to extend out from the reach through hole of bottom, contacts and is fixed on below the surface-mounted integrated circuit.The printed circuit board (PCB) of allowing the higher density integrated circuit is single-column type packaging housing (Single-In-Line-Package; SIP) and little external form pin structure dress (Small Outline J-leaded; SOJ), it is for adopting the structure dress of model.
According to the integrated circuit (IC) chip number of combination in the structure dress, the kind of structure dress integrated circuit is broadly divided into single-chip structure dress (Single Chip Package; SCP) with many chip packaging (MultichipPackage; MCP) two big classes, many chip packagings also comprise multi-chip module structure dress (MultichipModule; MCM).If according to the juncture of assembly and circuit board, structure dress integrated circuit can be divided into pin insert type (Pin-Through-Hole; PTH) with SMD LED surface-mount device LED (Surface MountTechnology; SMT) two big classes.The pin of pin insert type assembly is fine acicular or lamellar metal, and is fixing for welding in the guide hole (Via) that inserts runners (Socket) or circuit board.After then sticking on the circuit board earlier, fixes in the mode of welding again by the assembly of SMD LED surface-mount device LED.Currently used advanced structure packing technique is that chip directly coheres (Direct Chip Attach; DCA) structure dress is adorned the size of the volume of integrated circuit to reduce structure, and increases the integration of the circuit of structure dress IC interior.The technology that chip directly coheres is fixed on the substrate (Substrate) for direct chip (Integrated Circuit Chip) with integrated circuit, carries out the binding of circuit again.
With reference to shown in Figure 1, this uses the photosensitive type weld-proof membrane for tradition chip is fixed in schematic diagram on the substrate.One substrate 10 and a chip 40 at first are provided, wherein comprise on this substrate 10 a plurality of circuit leads 25 that layout is good, a plurality of first welded gasket (Solder Pad) 20, weld-proof membrane 30, with prewelding platform 18 (can omit according to need).Then comprise a plurality of second welded gaskets 45 and a plurality of soldering projections (Solder Bump) 15 on this chip.A plurality of soldering projections 15 are connected on the chip 40 by a plurality of second welded gaskets 45.Next chip 40 can be connected on a plurality of first welded gaskets 20 or prewelding platform 18 on the substrate 10 by a plurality of soldering projections 15, and so that chip 40 is fixed on the substrate 10, the position of wherein arbitrary soldering projection 15 is all corresponding to arbitrary first welded gasket 20.
In traditional structure dress integrated circuit structure, using the purpose of weld-proof membrane 30 is to avoid the online circuit lead 25 on the substrate 10 to be subjected to the infringement of external environment, and prevents in the successive process, because of the overflow of soldering projection 15 causes defective between the circuit.Therefore comprise in the structure dress integrated circuit structure of weld-proof membrane in tradition, weld-proof membrane 30 must cover on the circuit 25 that is distributed on the substrate, is distributed in circuit 25 on the substrate 10 with protection.For preferable defencive function is provided, weld-proof membrane 30 more must the cover part be distributed on arbitrary first welded gasket 20 on the substrate 10, causes the defective of defective because of overflow to avoid soldering projection 15 in follow-up processing procedure.Because weld-proof membrane must cover on arbitrary first welded gasket 20 that partly is distributed on the substrate 10, therefore use in the structure dress integrated circuit structure of weld-proof membrane in tradition, the periphery of first welded gasket 20 need be reserved extra border so that there are enough errors to allow that width carries soldering projection, also therefore between first welded gasket 20 on the substrate and first welded gasket 20 number of allowed lead will tail off.This phenomenon will cause the volume of the structure dress integrated circuit structure that uses weld-proof membrane to dwindle, and make this technology can't be applicable to the more and more littler demand of volume of integrated circuit.
Use the structure of weld-proof membrane to adorn integrated circuit,, therefore also can when soldering projection be connected on first welded gasket, soldering projection take place locate inaccurate problem and influence the quality that structure is adorned integrated circuit because weld-proof membrane must cover on arbitrary first welded gasket partly.And weld-proof membrane will cause taking place easily defective.When the structure dress form of using is chip bonding (the Flip Chip that covers brilliant filling (Underfill) that does not all cover adhesive filling mould adhesive filling mould mixtures (Molding Compound) or replaced; FC) time, the weld-proof membrane that is covered on the circuit will peel off the easy generation of the circuit that causes on the substrate relatively poor structure dress reliability and defective easily because of adhesion is more weak.
Summary of the invention
Main purpose of the present invention is to overcome the deficiencies in the prior art and defective, a high-density IC package structure and method thereof are provided, utilize the metal of tool attaching property of welding (Solder Wettability), material as first welded gasket, and on as the metal level of circuit, form a high-reliability screen, to avoid structure dress integrated circuit generation defective.
Second purpose of the present invention is to utilize the metal of attaching property of tool welding, as the material of first welded gasket, and forms a high-reliability screen on as the metal level of circuit, to improve the circuit integration of structure dress integrated circuit on substrate.
The 3rd purpose of the present invention is to utilize the metal of attaching property of tool welding, as the material of first welded gasket, and forms a high-reliability screen on as the metal level of circuit, to increase the reliability of structure dress integrated circuit.
The 4th purpose of the present invention is to utilize the metal of attaching property of tool welding, as the material of first welded gasket, and forms a high-reliability screen on as the metal level of circuit, to improve the yield (yield) of structure dress integrated circuit.
The 5th purpose of the present invention is to utilize the metal of attaching property of tool welding, as the material of first welded gasket, and forms a high-reliability screen on as the metal level of circuit, to improve the production efficiency of structure dress integrated circuit.
A further object of the present invention is to utilize the metal of attaching property of tool welding, as the material of first welded gasket, and forms a high-reliability screen on as the metal level of circuit, to reduce the production cost of integrated circuit structure dress.
According to above-described purpose, the invention provides a high-density IC package structure and method thereof, utilize the material of the metal of attaching property of tool welding as first welded gasket, and on as the metal level of circuit, form a high-reliability screen, to avoid not comprising the structure dress integrated circuit generation defective of weld-proof membrane.One substrate at first is provided and on this substrate, forms one whole metal level, wherein the most of copper (Copper) that adopts of the material of this metal level.Next in the position of definition first welded gasket on this metal level and on the metal level of part, form one first photoresist layer, wherein comprise a plurality of first openings in first photoresist layer.Next form one first welded gasket in the bottom of arbitrary opening on metal level and remove first photoresist layer, wherein this first welded gasket is the metal of attaching property of tool welding, forms in the mode of electric/electroless plating or in the mode of physical/chemical deposition.Next on the metal level of part, form second photoresist layer to remove the metal level of part, and removing second photoresist layer on substrate, to form a plurality of weld interfaces and a plurality of metal level, wherein arbitrary weld interface comprises the circuit that a plurality of metal levels of first welded gasket and metal level and this are used as substrate surface.Next on substrate, metal level and first welded gasket, form a high-reliability screen and remove high-reliability screen partly to expose first welded gasket.At last can be according to the demand of processing procedure and product, select whether forming mini projection or prewelding platform on first welded gasket, can finish the production process of the substrate in the high density structure dress integrated circuit as first soldering projection in successive process and the interface between first welded gasket.Be connected to the chip of a plurality of first soldering projections by a plurality of second welded gaskets, can directly add and be thermally coupled on a plurality of first welded gaskets, so that chip is directly fixed on the substrate by a plurality of first soldering projection reflows.At last cover on the substrate one deck structure dress encapsulating mixture (Molding Compound) or covering of replacing brilliant fill (Underfi11) with protective substrate on formed circuit and chip, can finish the processing procedure of high density structure dress integrated circuit.
Utilize processing procedure of the present invention and structure can improve the circuit integration of structure dress integrated circuit on substrate, and increase the reliability of structure dress integrated circuit.Utilize processing procedure of the present invention and structure also can improve the structure dress yield and the efficient of producing structure dress integrated circuit of integrated circuit.Utilize processing procedure of the present invention and structure more can reduce the production cost of structure dress integrated circuit.
Description of drawings
Fig. 1 uses weld-proof membrane for tradition chip is fixed in schematic diagram on the substrate;
Fig. 2 is the schematic diagram that forms metal level on substrate;
Fig. 3 is the schematic diagram that forms first photoresist layer on the part metals layer;
Fig. 4 is for forming the schematic diagram of one first welded gasket on metal level in the bottom of arbitrary opening;
Fig. 5 is the schematic diagram that removes first photoresist layer and form first welded gasket on the metal level of part;
Fig. 6 is the schematic diagram that forms one second photoresist layer on the metal level of part;
Fig. 7 is the schematic diagram that removes the metal level of part;
Fig. 8 removes second photoresist layer to form the schematic diagram of a plurality of metal levels and a plurality of weld interfaces on substrate;
Fig. 9 is the schematic diagram that forms a high-reliability screen on substrate, metal level and first welded gasket;
Figure 10 removes the high-reliability screen of part with the schematic diagram at a plurality of second openings of the inner formation of high-reliability screen;
Figure 11 removes the high-reliability screen of part to expose another schematic diagram of first welded gasket;
Figure 12 is the schematic diagram that forms mini projection on first welded gasket;
Figure 13 is the schematic diagram that forms the prewelding platform on first welded gasket;
Figure 14 is connected to schematic diagram on the substrate for chip; And
Figure 15 is for forming the schematic diagram that structure is adorned the encapsulating mixture and linked a plurality of second soldering projections at base plate bottom on chip and substrate.Symbol description among the figure
10 substrates
15 soldering projections
18 prewelding platforms
20 first welded gaskets
25 circuit leads
30 weld-proof membranes
40 chips
45 second welded gaskets
100 substrates
110 metal levels
120 first photoresist layers
122 first openings
130 first welded gaskets
140 second photoresist layers
160 weld interfaces
170 high-reliability screens
200 second openings
210 first is axial
220 second is axial
230 angles
240 mini projections
250 prewelding platforms
300 chips
310 second welded gaskets
320 first soldering projections
400 structures dress encapsulating mixture
500 the 3rd welded gaskets
510 second soldering projections
Embodiment
Describe the specific embodiment of the present invention in detail below in conjunction with drawings and Examples.
The invention provides a kind of IC package structure and the formation method that need not use traditional photosensitive type weld-proof membrane, utilize the material of attaching property of tool welding metal as first welded gasket, and on as the metal level of circuit, form a high-reliability screen, fail to cover fully the metal level of circuit because of contraposition is inaccurate so that defective takes place with the structure dress integrated circuit of avoiding traditional photosensitive type weld-proof membrane.With reference to shown in Figure 2, this is the schematic diagram that forms metal level on substrate.The present invention at first must provide a substrate 100 and form a metal level 110 on substrate.This metal level 110 can adopt different materials according to the demand of product.The material that common this metal level 110 is adopted is a copper.With reference to shown in Figure 3, this is the schematic diagram that forms first photoresist layer on the part metals layer.When defining desire on this metal level 110 behind the position of first welded gasket that forms on the substrate 100, can on metal level 110, form one first photoresist layer 120, and in first photoresist layer 120, form a plurality of first welded gasket openings 122.
With reference to shown in Figure 4, this is for forming the schematic diagram of one first welded gasket on metal level in the bottom of arbitrary first welded gasket opening.With reference to shown in Figure 5, this is the schematic diagram that removes first photoresist layer and form first welded gasket on the metal level of part.After on metal level 110, forming a plurality of first openings 122, form one first welded gasket 130 immediately in the bottom of arbitrary first opening 122 on metal level 110 and remove first photoresist layer 120 by first photoresist layer 120.This first welded gasket 130 is in order to connect first soldering projection in the successive process, so that chip can be fixed on the substrate.This first welded gasket 130 be one have the welding attaching property (SolderWettability) metal material.The thickness of this first welded gasket 130 can change with the difference of product and process requirement.Usually if first welded gasket 130 is for being used for connecting first soldering projection in the successive process, so that chip can be fixed on the substrate 100, then this first welded gasket 130 forms with the method for electric/electroless plating usually.If first welded gasket 130 connects other lead to connect other circuit unit for being used for, then this first welded gasket 130 forms in the mode of physical/chemical deposition usually.
With reference to shown in Figure 6, this is the schematic diagram that forms second photoresist layer on the substrate of part.After removing first photoresist layer 120, on the metal level 110 of part, form one second photoresist layer 140 immediately.The purpose of this second photoresist layer 140 is to be used for circuit on the layout substrate 100.With reference to shown in Figure 7, this is the schematic diagram that removes the metal level of part.After on the metal level of part, forming second photoresist layer 140, serve as that shielding removes the metal level 110 of part and removes second photoresist layer 140 (with reference to shown in Figure 8) with second photoresist layer 140 and first welded gasket 130 immediately, to form a plurality of metal levels 110 and a plurality of weld interfaces 160 on substrate 100, wherein arbitrary weld interface 160 comprises the metal level 110 and first welded gasket 130.After removing second photoresist layer 140, a plurality of metal levels 110 that remain on the substrate 100 are desire formed circuit on substrate 100.In the process that removes part metals layer 110; metal level 110 in weld interface 160 and below first welded gasket 130 is because there is the protection of first welded gasket 130; even therefore do not form second photoresist layer 140 above first welded gasket 130, the metal level 110 in weld interface can not be removed yet.
With reference to shown in Figure 9, this is the schematic diagram that forms a high-reliability screen (High Reliability Mask Layer) on substrate, metal level and first welded gasket.When after forming a plurality of metal levels 110 and a plurality of weld interfaces 160 on the substrate 100, form a high-reliability screen 170 immediately on substrate 100, metal level 110 and first welded gasket 130, wherein this high-reliability screen 170 is generally a non-photosensitive type dielectric material.The thickness of this high-reliability screen 170 can change with the difference of product and process requirement.Therefore high-reliability screen 170 is generally a non-photosensitive type material, therefore follow-up when removing the high-reliability screen 170 of part, can directly adopt the laser or the mode of electric paste etching to remove and does not need to use photoresist layer.
When after forming a high-reliability screen 170 on substrate 100, metal level 110 and first welded gasket 130, the high-reliability screen of removable portion is to expose first welded gasket 130 immediately.The following stated only is a kind of embodiment of the present invention, but does not limit the scope of the invention.With reference to shown in Figure 10, this is to remove the high-reliability screen of part with the schematic diagram at a plurality of second openings of the inner formation of high-reliability screen.When after forming a high-reliability screen 170 on substrate 100, metal level 110 and first welded gasket 130, the high-reliability screen 170 that removes part immediately is to form a plurality of second openings 200 in high-reliability screen 170 inside, and first welded gasket 130 is all exposed in the bottom of wherein arbitrary second opening 200.The sidewall of arbitrary second opening 200 all presents an angle 230 with one first axial 210, stability when interconnecting to improve first soldering projection in the successive process and first welded gasket 130, wherein this is first axial 210 for being parallel to the direction on substrate 100 surfaces.Arbitrary first welded gasket all is lower than the height on the plane of high-reliability screen 170 on second axial 220 at the height on the plane on second axial 220, and wherein this second axial 220 is a direction perpendicular to substrate 100 surfaces.The present invention is in the processing procedure that removes part high-reliability screen 170, and the mode of employing laser (Laser) or electric paste etching (Plasma Etching) are to remove the high-reliability screen 170 of part.Therefore in the program of the high-reliability screen 170 of this part that removes, can not need to use photoresist layer to come the assembly on protective substrate surface.
The following stated is another kind of embodiment of the present invention, but does not limit the scope of the invention.With reference to shown in Figure 11, this is to remove the high-reliability screen of part to expose another schematic diagram of first welded gasket.When after forming a high-reliability screen 170 on substrate 100, metal level 110 and first welded gasket 130, the high-reliability screen 170 that removes part immediately is to expose first welded gasket 130.In the process of the high-reliability screen 170 that removes part, the mode that is adopted be direction-free be etched with reduce high-reliability screen 170 the height of plane on second axial 220 up to exposing first welded gasket 130, wherein this is not second axial 220 for exposing in this removes the process of high-reliability screen 170 of part perpendicular to the direction on substrate 100 surfaces and metal level 110.In order to expose first welded gasket 130, therefore first welded gasket 130 is higher than the height on the plane of high-reliability screen 170 on second axial 220 at the height on the plane on second axial 220.
With reference to shown in Figure 12, this is the schematic diagram that forms mini projection (MiniBump) 240 on first welded gasket.With reference to shown in Figure 13, this is the schematic diagram that forms prewelding platform 250 on first welded gasket.In order to increase first soldering projection in the successive process and associativity, stability and the coplanarity of first welded gasket 130, usually can on first welded gasket 130, form a mini projection 240 or prewelding platform 250 interface, so that chip can more stably be carried on the substrate as first soldering projection and first welded gasket 130.In the processing procedure of making mini projection 240, can form one deck tin layer on the bed course 130 as mini projection 240 to weld with substrate immersion one tin lead solution or through electroless plating first.And in the processing procedure of making prewelding platform 250, usually flatten as prewelding platform 250 with tin ball/tin cream reflow gluing to the first welded gasket 130 and with this tin ball earlier, to be increased in the successive process, first projection is connected to the contact area of weld interface and provides good coplanarity and the welding reliability.In the present invention, mini projection and prewelding platform can be applicable to another kind and expose on the substrate of form of first welded gasket, do not limit the scope of its use.In the present invention first welded gasket more can be directly and first soldering projection in the successive process interconnect, to be fixed on the substrate through chip.
With reference to shown in Figure 14, this is connected to schematic diagram on the substrate for chip.After exposing first welded gasket, with chip 300 and substrate 100 being linked mutually.Chip 300 link mutually by a plurality of second welded gaskets 310 and a plurality of first soldering projections 320 and arbitrary second welded gasket 310 all corresponding to arbitrary first soldering projection 320.More comprise a protective layer on the chip, in the process that the reflow heating is cohered, damaged to prevent chip.A plurality of first soldering projections 320 can be connected to a plurality of first welded gaskets 130 on the substrate 100 by the mode of reflow heating so that chip 300 is fixed on the substrate 100.Arbitrary first soldering projection 320 all can be easily corresponding to arbitrary first welded gasket 130.Owing to do not use weld-proof membrane among the present invention and in first soldering projection 320 is connected to the process of first welded gasket 130, can not produce the problem of location, therefore the present invention can increase the processing procedure operational paradigm of integrated circuit, and reduces and produce the needed cost of structure dress integrated circuit.Chip only is fixed on the substrate to utilizing a kind of enforcement of the present invention sharp, but does not limit protection scope of the present invention.The present invention also can utilize first welded gasket on weld interface to be connected to other circuit unit by a lead.After chip 300 is fixed on the substrate 100; adhesive filling mould mixture (Paekage Molding Compound) 400 structures are adorned mode or covering brilliant filler (Underfill) structure dress mode fixes with the joint employing structure of chip 300 and substrate and chip being adorned; and link that a plurality of second soldering projections 510 (with reference to shown in Figure 15) can not be subjected to the influence of external environment with protection chip 300 and circuit on the substrate 100 in the process of running and the usefulness that reduces its running, and finish the processing procedure of the structure dress integrated circuit that does not comprise weld-proof membrane at base plate bottom.Can be connected with a plurality of second soldering projections 510 by a plurality of the 3rd welded gaskets 500 at base plate bottom, can not connect other assembly again so that comprise the structure dress integrated circuit of weld-proof membrane.With reference to shown in Figure 11, a plurality of second soldering projections 510 that are connected with substrate 100 bottoms only do not limit interest field of the present invention for one embodiment of the invention.Utilize the structure dress integrated circuit of the non-photosensitive type dielectric medium welding pad opening design of made of the present invention, still can adopt other structure dress form to be connected on other assembly.
Owing to do not use weld-proof membrane, therefore the periphery of first welded gasket does not need to reserve extra border among the present invention, but and the more circuit of layout between wantonly two first welded gaskets.This phenomenon can make the volume of the structure dress integrated circuit that does not comprise weld-proof membrane successfully dwindle and can comprise more circuit, with the usefulness of the structure dress integrated circuit after the raising reduced volume, and can improve the stability that structure is adorned integrated circuit
In sum, the invention provides an IC package structure and a method thereof of not using weld-proof membrane, utilize the material of the metal of attaching property of attaching property of attaching property of tool welding as first welded gasket, and on as the metal level of circuit, form a high-reliability screen, to avoid not comprising the structure dress integrated circuit generation defective of weld-proof membrane.One substrate at first is provided and on this substrate, forms a metal level, wherein the most of copper that adopts of the material of this metal level.Next in the position of definition first welded gasket on this metal level and on the metal level of part, form one first photoresist layer, wherein comprise a plurality of first openings in first photoresist layer.Next form one first welded gasket in the bottom of arbitrary opening on metal level and remove first photoresist layer, wherein this first welded gasket is the metal of attaching property of tool welding, forms in the mode of electric/electroless plating or in the mode of physical/chemical deposition.Next on the metal level of part, form second photoresist layer to remove the metal level of part, and removing second photoresist layer on substrate, to form a plurality of weld interfaces and a plurality of metal level, wherein arbitrary weld interface comprises the circuit that a plurality of metal levels of first welded gasket and metal level and this are used as substrate surface.Next on substrate, metal level and first welded gasket, form a high-reliability screen and remove high-reliability screen partly to expose first welded gasket.At last can be according to the demand of processing procedure and product, select whether forming mini projection or prewelding platform on first welded gasket, can finish the production process of the substrate in the high density structure dress integrated circuit as first soldering projection in successive process and the interface between first welded gasket.Be connected to the chip of a plurality of first soldering projections by a plurality of second welded gaskets, can directly add and be thermally coupled on a plurality of first welded gaskets, so that chip is directly fixed on the substrate by a plurality of first soldering projection reflows.At last cover one deck structure dress encapsulating mixture on the substrate or insert cover brilliant fill (Underfill) with protective substrate on formed circuit and chip, can finish the processing procedure of high density structure dress integrated circuit.
Utilize processing procedure of the present invention and structure can improve the circuit integration of structure dress integrated circuit on substrate, and increase the reliability of structure dress integrated circuit.Utilize processing procedure of the present invention and structure also can improve the yield and the efficient of producing structure dress integrated circuit of structure dress integrated circuit.Utilize processing procedure of the present invention and structure more can reduce the production cost of structure dress integrated circuit, not only have outside the practical effect, and be design not seen before, have the enhancement of effect and progressive.
The above is preferred embodiment of the present invention only, is not in order to limit protection scope of the present invention; All other do not break away from the equivalence of being finished under the disclosed spirit and changes or modification, all should be included in the scope of claims.
Claims (22)
1. a high-density IC package structure is characterized in that, this structure comprises: a substrate;
A plurality of metal levels are positioned on this substrate of part in order to as the circuit on this substrate;
The welded gasket of a plurality of tool attaching property of welding (Solder Wettability) is positioned on this metal level of part to form a plurality of weld interfaces;
One high-reliability screen covers these a plurality of metal levels and exposes this welded gasket on the surface of this high-reliability screen; And
Wherein, do not have weld-proof membrane (SolderMask) between above-mentioned metal level and the weld interface.
2. high-density IC package structure as claimed in claim 1 is characterized in that, comprises a plurality of openings in the above-mentioned high-reliability screen.
3. high-density IC package structure as claimed in claim 2 is characterized in that, above-mentioned welded gasket is positioned at a bottom of this opening.
4. high-density IC package structure as claimed in claim 2 is characterized in that, above-mentioned welded gasket is lower than this high-reliability screen at one first the height on plane on axially at one first the height on plane on axially.
5. high-density IC package structure as claimed in claim 4 is characterized in that, above-mentioned first axially is the direction perpendicular to a surface of this substrate.
6. high-density IC package structure as claimed in claim 2 is characterized in that, a sidewall of above-mentioned opening and one second axially presents an angle.
7. high-density IC package structure as claimed in claim 6 is characterized in that, above-mentioned second axially is the direction on the surface that is parallel to this substrate.
8. high-density IC package structure as claimed in claim 1 is characterized in that, above-mentioned welded gasket is higher than this high-reliability screen at one the 3rd the height on plane on axially at one the 3rd the height on plane on axially.
9. high-density IC package structure as claimed in claim 8 is characterized in that, the above-mentioned the 3rd axially is the direction perpendicular to a surface of this substrate.
10. high-density IC package structure as claimed in claim 1 is characterized in that, more comprises a mini projection (Mini-Bump) on the above-mentioned welded gasket.
11. high-density IC package structure as claimed in claim 1 is characterized in that, more comprises a prewelding platform (Presoldering) on the above-mentioned welded gasket.
12. high-density IC package structure as claimed in claim 1 is characterized in that, above-mentioned high-reliability screen is a non-photosensitive type dielectric material layer.
13. a method that forms high density structure dress integrated circuit is characterized in that this method comprises:
One substrate is provided;
Form a metal level on this substrate;
Form one first photoresist layer on this metal level of part, and in this first photoresist layer, form a plurality of openings;
Form the welded gasket of a plurality of tools attaching property of welding (Solder Wetability), wherein arbitrary this welded gasket is positioned at the bottom of arbitrary this opening and on this metal level;
Remove this first photoresist layer;
Form one second photoresist layer on this metal level of part;
With this second photoresist layer and this first welded gasket serves as that shielding removes this metal level of part and removes this second photoresist layer to form a plurality of circuit and a plurality of weld interface on this substrate, and wherein arbitrary circuit is this metal level and arbitrary weld interface is formed by this metal level and this welded gasket on it;
Form a high-reliability screen on this substrate, this welded gasket and this metal level; And
The high-reliability screen that removes part is to expose this welded gasket on the surface of this high-reliability layer.
14. the method for formation high density structure dress integrated circuit as claimed in claim 13 is characterized in that, comprises a plurality of openings in the above-mentioned high-reliability screen.
15. the method for formation high density structure dress integrated circuit as claimed in claim 14 is characterized in that above-mentioned welded gasket is positioned at a bottom of this opening.
16. the method for formation high density structure as claimed in claim 14 dress integrated circuit is characterized in that, above-mentioned welded gasket is lower than this high-reliability screen at one first the height on plane on axially at one first the height on plane on axially.
17. the method for formation high density structure as claimed in claim 16 dress integrated circuit is characterized in that, above-mentioned first axially is the direction perpendicular to a surface of this substrate.
18. the method for formation high density structure dress integrated circuit as claimed in claim 14 is characterized in that a sidewall of above-mentioned opening and one second axially presents an angle.
19. the method for formation high density structure as claimed in claim 18 dress integrated circuit is characterized in that, above-mentioned second axially is the direction on the surface that is parallel to this substrate.
20. the method for formation high density structure as claimed in claim 13 dress integrated circuit is characterized in that, above-mentioned welded gasket is higher than this high-reliability screen at one the 3rd the height on plane on axially at one the 3rd the height on plane on axially.
21. the method for formation high density structure as claimed in claim 20 dress integrated circuit is characterized in that, the above-mentioned the 3rd axially is the direction perpendicular to a surface of this substrate.
22. the method for formation high density structure dress integrated circuit as claimed in claim 13 is characterized in that above-mentioned high-reliability screen is a non-photosensitive type dielectric material.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB021218250A CN1180473C (en) | 2002-06-06 | 2002-06-06 | High-density IC package structure and its method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB021218250A CN1180473C (en) | 2002-06-06 | 2002-06-06 | High-density IC package structure and its method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1387253A true CN1387253A (en) | 2002-12-25 |
| CN1180473C CN1180473C (en) | 2004-12-15 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB021218250A Expired - Lifetime CN1180473C (en) | 2002-06-06 | 2002-06-06 | High-density IC package structure and its method |
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| CN (1) | CN1180473C (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101730376B (en) * | 2008-11-03 | 2012-09-26 | 欣兴电子股份有限公司 | Circuit structure with shielding effect and manufacturing method thereof |
| CN102945821A (en) * | 2012-11-28 | 2013-02-27 | 贵州振华风光半导体有限公司 | Integrating method of high-density thick-film hybrid integrated circuit |
| CN110690129A (en) * | 2019-09-24 | 2020-01-14 | 浙江集迈科微电子有限公司 | Three-dimensional heterogeneous stacking method with anti-overflow tin structure |
| CN112331619A (en) * | 2020-11-04 | 2021-02-05 | 华天科技(南京)有限公司 | Gravity magnetic induction chip side-mounting structure and method for improving side-mounting yield |
-
2002
- 2002-06-06 CN CNB021218250A patent/CN1180473C/en not_active Expired - Lifetime
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101730376B (en) * | 2008-11-03 | 2012-09-26 | 欣兴电子股份有限公司 | Circuit structure with shielding effect and manufacturing method thereof |
| CN102945821A (en) * | 2012-11-28 | 2013-02-27 | 贵州振华风光半导体有限公司 | Integrating method of high-density thick-film hybrid integrated circuit |
| CN102945821B (en) * | 2012-11-28 | 2015-07-29 | 贵州振华风光半导体有限公司 | The integrated approach of high-density thick-film hybrid integrated circuit |
| CN110690129A (en) * | 2019-09-24 | 2020-01-14 | 浙江集迈科微电子有限公司 | Three-dimensional heterogeneous stacking method with anti-overflow tin structure |
| CN110690129B (en) * | 2019-09-24 | 2021-05-28 | 浙江集迈科微电子有限公司 | Three-dimensional heterogeneous stacking method with anti-overflow tin structure |
| CN112331619A (en) * | 2020-11-04 | 2021-02-05 | 华天科技(南京)有限公司 | Gravity magnetic induction chip side-mounting structure and method for improving side-mounting yield |
| CN112331619B (en) * | 2020-11-04 | 2023-08-15 | 华天科技(南京)有限公司 | Gravity magnetic induction chip side-mounting structure and method for improving side-mounting yield |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1180473C (en) | 2004-12-15 |
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