CN1385992A - Timing recovery sampling circuit - Google Patents
Timing recovery sampling circuit Download PDFInfo
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- CN1385992A CN1385992A CN 01119230 CN01119230A CN1385992A CN 1385992 A CN1385992 A CN 1385992A CN 01119230 CN01119230 CN 01119230 CN 01119230 A CN01119230 A CN 01119230A CN 1385992 A CN1385992 A CN 1385992A
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- sampling circuit
- timing recovery
- signal
- recovery sampling
- analog
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Abstract
A timing receiving of sampling circuit contains a low pass filter receives a continuous first signal to screen the high frequency component of the first signal to generate a second continuous signal; a time recovery sampling circuit set at the back of the low pass filter, sampling and receiving the mentioned second signal to decide the preferable sampling points. Since low pass filters have the fuction of filtering high frequency component, it will widen the too narrow channel response so as to increase communication quality.
Description
The present invention relates to a kind of timing recovery sampling circuit.
See also Fig. 1.In digital communication system, receiver 11 receives after the signal, can deliver to the action that a receiving processor 2 carries out regularly affirmation and data read, wherein we often use analog-digital converter 12 (Analog-to-Digital Converter), with analog sample and be converted into digital signal and handled by receiving digital signals processor 13.For the performance (performance) that improves signal processing, utilize timing recovery sampling circuit 3 (timing recovery circuit) to decide the timing (timing) of sampling.This timing recovery sampling circuit comprises sampling clock pulse generator 15, the function of time 16 and channel estimation device 17, and the most frequently used timing recovery method is the value of utilizing after taking a sample, through equalizer 14 (equalizer) and channel estimation device 17 (channel estimator), find out the response (response) of passage (channel), and utilize channel response to form regularly function 16 (timing function), make clock pulse generator 15 adjust sampling regularly (sampling timing) with the value of timing function.Wherein channel response (channel response) is the output of a square-wave pulse (pluse) passage through a passage time.The most frequently used timing function is te=h
-1-α h
1, h wherein
-1And h
1It is the cursor of main cursor (main cursor) both sides.When channel response was too narrow, regularly function was promptly no longer suitable for this.
Fig. 1 is in the general digital signaling system, the signal (received signal) of taking a sample and receiving in baud rate (baud-rate) mode, handled the data (recovered data) that obtain restoring, again with these data of restoring, remove to estimate channel response in adaptive filter (adaptive filter) mode, as shown in Figure 2, that is, channel estimation device 17 is in order to the channel response of estimation as Fig. 2, h
-2, h
-1, h
0, h
1, h
2, h
3, and get h
-1And h
1Come the formation time function,, and adjusted with the judgement quality of sample time.
Again by taking out main cursor h in the response
0About cursor h
-1And h
1Form regularly function, h
-1-α h
1, judge with the value of timing function whether sampling is regularly appropriate, and adjusted sampling phase (sampling phase), make it to reach the sampling phase of the best, make system best signal noise ratio (SNR) be arranged (Signal-to-NoiseRatio).
Adopt this timing function, h
-1-α h
1Timing recover, its performance is very responsive to the shape (shape) of channel response, so to different passages, its α value difference is not just very big.Usually main wave band (mainlob) (being the waveform at the primary cursor place) width of channel response can change with the length of passage.When passage length shortened (jitty), main wave band just narrowed down, as the width of main wave band during less than 2UI (UI sample time spacing), as shown in Figure 3.The α value of this moment will alter a great deal, even changes polarity.α value is to get fixed value during general design, but when changing greatly in the face of passage length, adopt this kind regularly the timing of function recover promptly can't reach the signal noise ratio of the best.
The objective of the invention is to be to provide a kind of improved timing recovery sampling circuit, it can make narrow channel response broaden, so that the situation of the applicable any passage of its timing function.
For achieving the above object, timing recovery sampling circuit of the present invention, it comprises: a low pass filter receives first a continuous signal and also the high frequency composition of described first signal is filtered out, to produce a continuous secondary signal; And a timing recovery sampling circuit, be located at level behind the described low pass filter, sampling receives described secondary signal, with the preferable sampling point of decision channel response.
When described first signal during from a jitty, the channel response of described timing recovery sampling circuit is broadened, export a restored data to handle described secondary signal.
Wherein first signal is to be an analog signal.Channel response is to be a channel impulse response (channelimpulse response), and it has a main wave band (main lob).When described main wave band has described high frequency composition in described first signal, be less than a special time, and, revise described channel impulse response, make described main wave band greater than described special time by described filter.Described special time is two times sample time (sampling time).The speed that is decided by described timing recovery sampling circuit sampling described sample time, and its inverse is a sampling frequency, described sampling frequency is the frequency for a sampled signal.
The analog-digital converter of timing recovery sampling circuit is to be electrically connected to described filter, and with described sampled signal described secondary signal is taken a sample, and to produce an analog sample, described analog sample is exported a digital signal after changing.Its equalizer is electrically connected to described analog-digital converter, in order to remove the interfering components of one yard border interference (ISI) to produce an equalizing signal S4 according to described digital signal and symbol rank.Its timing recovery sampling circuit 3 then in order to estimate according to described equalizing signal described channel impulse response with a time error Te, and adjust the phase place of described sampled signal in view of the above.Above-mentioned equalizing signal S4 is described restore data.
Timing recovery sampling circuit is to get described time error by a timing function, its channel estimation device is electrically connected to described equalizer, in order to estimate described channel impulse response, and by described timing function to produce described time error, and its sampling clock pulse generator is electrically connected to described channel estimation device, to produce described sampled signal by described time error.
Adopt such scheme of the present invention, because low pass filter has the function of filtering high frequency composition, thus narrow channel response can be broadened, to realize purpose of the present invention.
Be clearer understanding purpose of the present invention, characteristics and advantage, the present invention is described in detail below in conjunction with accompanying drawing.
Fig. 1 is that existing timing recovers the sampling calcspar;
Fig. 2 is a channel response one;
Fig. 3 is a channel response two;
Fig. 4 is that timing of the present invention recovers the sampling calcspar.
See also Fig. 4.The present invention the invention provides a kind of improved timing recovery sampling circuit, it sets up a low pass filter 41 (low-pass filter), place before the sampling, make narrow channel impulse response (channel impulse response) be broadened greater than 2UI (two times sample times), and pulse wave (pulse) the shape correction that makes main wave band (main lob) must be symmetry, can reduce the excursion of α value like this, make fixing timing function preferable performance (performance) all be arranged different passage lengths.
The specification of this low pass filter 41 is to decide according to channel impulse response and sampling period, makes that narrower pulse wave can broaden, but enough originally wide channel responses then are not affected, in order to avoid increase the burden of other signal processing.
In other words, timing recovery sampling circuit of the present invention is made up of a receiving processor 2 and a filter 41.Low pass filter 41 is located at receiving processor 2 level before, so as to handling first a continuous signal s1, filtering in addition when the described first signal s1 has a high frequency composition, and keep the low frequency composition of the described first signal s1, to produce a continuous secondary signal s2, input to described receiving processor 2, the channel response of described receiving processor 2 is broadened, export a restored data s4 to handle described secondary signal s2.
Wherein, the first signal s1 is an analog signal.Channel response is a channel impulse response (channelimpulse response), and it has a main wave band (main lob).When described main wave band has described high frequency composition in described first signal, be, and revise described channel impulse response, make described main wave band greater than described special time by described low pass filter 41 less than a special time.Described special time is two times (sampling time) 2UI sample time.Be the speed that is decided by the sampling of described timing recovery sampling circuit described sample time, and its inverse to be a sampling frequency, and the frequency that described sampling frequency is sampled signal Fs.
The analog-digital converter 12 of receiving processor 2 is to be electrically connected to low pass filter 41, and with described sampled signal Fs described secondary signal s2 is taken a sample, and produces an analog sample x1, described analog sample x1 and output one digital signal x2 after changing.Its equalizer 14 is to be electrically connected to described analog-digital converter 12, therebetween more through a receiving digital signals processor 13, in order to according to described digital signal x2 and with+1 ,-1 ,+the symbol rank of 3 and-3 combinations, remove an interfering components to produce an equalizing signal, be release signal s4.Its timing recovery sampling circuit 3 then in order to according to the described channel impulse response of described equalizing signal (release signal s4) estimation with a time error Te, and adjust the phase place of described sampled signal Fs in view of the above.
Timing recovery sampling circuit 3 is to get described time error Te by a timing function 16, its channel estimation device 17 is electrically connected to described equalizer 14, in order to estimate described channel impulse response Hn, and by described timing function 16 to produce described time error Te, and its sampling clock pulse generator 15 is electrically connected to described channel estimation device 17, with by described time error Te, produce described sampled signal Fs, to adjust the phase place of described sampled signal Fs.Above-mentioned interfering components is that (ISI) disturbed on one yard border.
By above-mentioned diagram and explanation, characteristics of the present invention as can be known are to improve existing timing recovery sampling circuit with a low pass filter, make that narrower channel response can broaden, but enough originally wide channel responses are unaffected, thereby can promote communication quality.
Claims (25)
1. timing recovery sampling circuit comprises:
-low pass filter receives first a continuous signal and also the high frequency composition of described first signal is filtered out, to produce a continuous secondary signal; And
One timing recovery sampling circuit is located at level behind the described low pass filter, and sampling receives described secondary signal, with the preferable sampling point of decision channel response.
2. timing recovery sampling circuit as claimed in claim 1 is characterized in that, when described first signal during from a jitty, the channel response of described timing recovery sampling circuit broadens.
3. timing recovery sampling circuit as claimed in claim 2 is characterized in that, the channel response of described timing recovery sampling circuit is broadened, and is to export a restored data in order to handle described secondary signal.
4. timing recovery sampling circuit as claimed in claim 1 is characterized in that, described first signal is an analog signal.
5. timing recovery sampling circuit as claimed in claim 1 is characterized in that, described channel response is a channel impulse response.
6. timing recovery sampling circuit as claimed in claim 5 is characterized in that, described channel impulse response has a main wave band.
7. timing recovery sampling circuit as claimed in claim 6 is characterized in that, when described main wave band has described high frequency composition in described first signal, is less than a special time.
8. timing recovery sampling circuit as claimed in claim 7 is characterized in that, described main wave band is by the described channel impulse response of described low pass filter correction, makes described main wave band greater than described special time.
9. timing recovery sampling circuit as claimed in claim 8 is characterized in that, described special time is two times sample time.
10. timing recovery sampling circuit as claimed in claim 9 is characterized in that, be the speed that is decided by described timing recovery sampling circuit sampling described sample time, and its inverse is a sampling frequency, and described sampling frequency is the frequency of a sampled signal.
11. timing recovery sampling circuit as claimed in claim 10 is characterized in that, described timing recovery sampling circuit comprises:
One analog-digital converter is electrically connected to described low pass filter, and with described sampled signal described secondary signal is taken a sample, to produce an analog sample, described analog sample and output one digital signal after changing;
One equalizer is electrically connected to described analog-digital converter, in order to according to described digital signal and symbol rank and remove an interfering components to produce an equalizing signal;
One timing recovery sampling circuit, in order to estimate according to described equalizing signal described channel impulse response with a time error, and adjust the phase place of described sampled signal in view of the above.
12. timing recovery sampling circuit as claimed in claim 11 is characterized in that, described equalizing signal is described restore data.
13. timing recovery sampling circuit as claimed in claim 11 is characterized in that, described timing recovery sampling circuit is that regularly function is to get described time error by one, and it comprises:
One channel estimation device is electrically connected to described equalizer, in order to estimating described channel impulse response, and by described timing function to produce described time error; And
One sampling clock pulse generator is electrically connected to described channel estimation device, to produce described sampled signal by described time error.
14. timing recovery sampling circuit as claimed in claim 11 is characterized in that, described symbol rank are+1 ,-1 ,+3 and-3 combination.
15. timing recovery sampling circuit as claimed in claim 11 is characterized in that, described interfering components is that (ISI) disturbed on one yard border.
16. a timing recovery sampling circuit comprises:
One low pass filter is used and is handled one first signal, and in addition filtering when the described first signal tool, one high frequency composition is to produce a secondary signal;
One analog-digital converter is electrically connected to described low pass filter, and with a sampled signal described secondary signal is taken a sample, to produce an analog sample, described analog sample and output one digital signal after changing;
One equalizer is electrically connected to described analog-digital converter, in order to according to described digital signal and symbol rank and remove an interfering components to produce an equalizing signal; And
One timing recovery sampling circuit, in order to estimate according to described equalizing signal a channel impulse response with a time error, and adjust the phase place of described sampled signal in view of the above.
17. timing recovery sampling circuit as claimed in claim 16, it is characterized in that, described low pass filter is filtering in addition when described first signal has a high frequency composition, and when described first signal has a low frequency characteristic, keep original waveform, import described analog-digital converter described channel impulse response is broadened to produce described secondary signal.
18. timing recovery sampling circuit as claimed in claim 17 is characterized in that, described channel impulse response has a main wave band.
19. timing recovery sampling circuit as claimed in claim 18 is characterized in that, when described main wave band has described high frequency composition in described first signal, is less than a special time.
20. timing recovery sampling circuit as claimed in claim 19 is characterized in that, described main wave band is by described low pass filter, revises described channel impulse response, makes described main wave band greater than described special time.
21. timing recovery sampling circuit as claimed in claim 20 is characterized in that, described special time is the sample time for two times.
22. timing recovery sampling circuit as claimed in claim 21 is characterized in that, be the speed that is decided by described timing recovery sampling circuit sampling described sample time, and its inverse is the frequency of described sampled signal.
23. timing recovery sampling circuit as claimed in claim 16 is characterized in that, described timing recovery sampling circuit is that regularly function is to get described time error by one, and it comprises:
One channel estimation device is to be electrically connected to described equalizer, in order to estimating described channel impulse response, and by described timing function to produce described time error; And
One sampling clock pulse generator is to be electrically connected to described channel estimation device, with by described time error, produces described sampled signal.
24. timing recovery sampling circuit as claimed in claim 16 is characterized in that, described symbol rank be for+1 ,-1 ,+3 and-3 combination.
25. timing recovery sampling circuit as claimed in claim 16 is characterized in that, described interfering components is to disturb (ISI) for one yard border.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 01119230 CN1130883C (en) | 2001-05-14 | 2001-05-14 | Timing recovery sampling circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 01119230 CN1130883C (en) | 2001-05-14 | 2001-05-14 | Timing recovery sampling circuit |
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| Publication Number | Publication Date |
|---|---|
| CN1385992A true CN1385992A (en) | 2002-12-18 |
| CN1130883C CN1130883C (en) | 2003-12-10 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 01119230 Expired - Fee Related CN1130883C (en) | 2001-05-14 | 2001-05-14 | Timing recovery sampling circuit |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101320982B (en) * | 2007-06-06 | 2011-12-07 | 智原科技股份有限公司 | Time sequence reply parameter generation circuit and signal receiving circuit |
-
2001
- 2001-05-14 CN CN 01119230 patent/CN1130883C/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101320982B (en) * | 2007-06-06 | 2011-12-07 | 智原科技股份有限公司 | Time sequence reply parameter generation circuit and signal receiving circuit |
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| Publication number | Publication date |
|---|---|
| CN1130883C (en) | 2003-12-10 |
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