CN1383128A

CN1383128A - Parallel display method for display

Info

Publication number: CN1383128A
Application number: CN 02109233
Authority: CN
Inventors: 胡继炜
Original assignee: Individual
Current assignee: Individual
Priority date: 2002-03-04
Filing date: 2002-03-04
Publication date: 2002-12-04
Anticipated expiration: 2022-03-04
Also published as: CN1165035C

Abstract

The invention relates to the parallel display method for displays. Serial scanning input is adopted for all of the panel display now, displaying on screen as scanned. The method of serial scanning and displaying image can not display each frame of image in parallel, and blinks are existed inside frame and between frames. Before pixels are displayed, two cascaded latched circuits or device with latch function takes in effect in the invented method, constituting the set to realize the conversion from serial to paralle. Thus, the image is serially scanned, then display in paralle. The invented method eliminates blinks inside frame, and reduces the blinks between frames to minimum.

Description

Parallel display method for display

The present invention relates to parallel display method for display, in particular, the present invention relates to flat-panel monitor serial scan input, parallel synchronous output display packing.

No matter existing flat-panel monitor adopts which kind of addressing mode and control device, all is to adopt pointwise to line by line scan or line by line scan the method display image that the scan edge limit shows.That is to say that existing flat-panel monitor is to adopt the serial scan display packing to show every two field picture, utilizes people's vision temporality then, reaches the purpose of the image that shows that a frame is complete.Present display exists flicker in the row, interline flicker and interframe to glimmer owing to adopt pointwise line by line or demonstrations of lining by line scan.

No matter existing flat-panel monitor display packing adopts which kind of addressing mode, which kind of device, and the demonstration equivalent schematic of each display pixel can be represented with schematic block diagram shown in the accompanying drawing 1.Its course of work is: with (or ) row (or row) control line gating latch, or () the signal input latch on row (or row) signal wire begin to drive display pixel and show in the time of the latches signal.Latch described here be meant have addressing function, the electronic circuit of latch function and driving function or other device, or have addressing function, drive electronic circuit or other device of function.

Existing flat-panel monitor equivalence schematic block diagram as shown in Figure 2.Be the hard iron battle array of pass-out 3 * 3 only here for simplicity.The course of work of whole display is: 21a, 21b, 21c ... 21n capable (or row) control line, each row of control gating (or row), in the gating term of validity, 22a, 22b, 22c ... one 22n row (or row) signal wire serial input shows signal successively arrives latch.Latch drives pixel and shows in latch signal, and the pointwise of realization display is lined by line scan and shown or the demonstration of lining by line scan.As can be seen, existing flat-panel monitor is the serial scan input, and serial shows.

Parallel display method for display involved in the present invention is on the basis of existing plane display technique, increases electronic circuit or control device that one-level has latch function, drives function before each pixel, and its equivalent schematic block diagram is seen accompanying drawing 3.Latch 1 in the accompanying drawing 3 is electronic circuit or the control device with addressing function, latch function and driving function; Latch 2 is electronic circuit or other devices that have latch function, drive function.The course of work of each pixel is: (or

) row (or row) control line gating latch 1, (or

) in the term of validity, (or ) signal is input in the latch 1, then Latched signal and latching on control line control lock storage 2 input latches 1.Latch 2 begins to drive in latch signal advises display pixel to show.After signal was imported next time in latch 1 scanning, latch 2 existed

Control is imported down next time signal and is latched and drives the display pixel demonstration.

Parallel display method for display involved in the present invention, the principle equivalence schematic block diagram of parallel display circuit of all pixels of whole display or display control unit correspondence is seen accompanying drawing 4.For for simplicity, only draw 3 * 3 huge times here, in actual applications, should be m * n hard iron battle array, m and n are respectively any natural number, can be big or small arbitrarily huge battle array with purposes as required.The size of hard iron battle array also influences principle of the present invention and essence of the present invention, does not also influence concrete range of application of the present invention.

4 equivalent schematic in conjunction with the accompanying drawings, it is as follows now to describe principle of the present invention in detail:

41a, 41b, 41c ..., 41n (or 42a, 42b, 42c ..., 42m) row (or row) control line, each row of difference sequential control gating (or row), in each row of control line gating (or row) term of validity, latch 1 on the corresponding row (or row), import respectively successively or synchronously 42a, 42b, 42c ..., 42m (or 41a, 41b, 41c ..., 41n) signal on (or row) is to latch 1, latch 1 latchs respective signal to be shown.After each frame signal employing pointwise is lined by line scan or is lined by line scan and is input to all corresponding latchs 1 in the display, in this time before the next frame signal begins to scan input, control line 43a, the 43b of display lock storage 2,43c ..., all latchs 2 of 43n synchro control, latched signal on the corresponding latch 1 of parallel input.2 inputs of all latchs and latch corresponding shows signal after, drive the respective pixel display image.Up to the parallel input of next frame at first, realize parallel demonstration of every frame synchronization of image.After the pointwise of next frame signal is lined by line scan or is lined by line scan input all latchs 1 finish, latch 2 43a, 43b, 43c ..., under the 43n synchro control, synchronous input next frame signal, and latch and drive pixel and run simultaneously and show the next frame picture signal.Realize the demonstration of running simultaneously of image.As can be seen, the essence of parallel display method involved in the present invention, be that electronic circuit or control device that the latch on the display 1, latch 2 are formed are formed a functional string---and converter, realizing the serial scan or the addressing input of display, parallel drive shows.Be that serial scan input and line output show.

Owing to realized the parallel demonstration of every frame synchronization of image, eliminated the interior flicker of row and the interline flicker of display image.Owing to adopted the two-stage latch means, have only the signal switching time on the latch 2 switching time of two two field pictures, the interframe flicker is reduced to minimum, has realized approximate static demonstration of image.

Parallel control line 43a on the latch 2 in the accompanying

drawing

4,43b, 43c ..., 43n can walk abreast and connect, and also can connect work by multirow, also can be that any zones of different links together, driven in synchronism control lock storage 2 synchro control.

In the equivalent schematic mode as shown in Figure 4, when the display text image,, can realize that the static state of literal shows because latch has memory function.When display video image, can only refresh the part of variation, and the unchanged part of static demonstration reaches better visual effect.Peripheral drive circuit is designed to corresponding integrated drive electronics according to different application modes.

Realize that plain mode of the present invention is an a-Si TFT-LCD display.Now with regard to a-Si TFT-LCD display as application example of the present invention, illustrate that the present invention realizes the parallel method that shows.Accompanying drawing 5 is the corresponding equivalent schematic of existing each pixel of TFT-LCD.By TFT on-off element, Vs storage capacitors, V _LcLiquid crystal capacitance constitutes, and Vs is signal electrode, V ₈For scan electrode, Vc are public electrode.At selection phase (row flyback time), owing to applied V ₈, make on-off element become conducting state, so signal voltage Vs fully charges to liquid crystal capacitance and storage capacitors.At non-select time (almost being a frame time) owing to there is not a V ₈Effect, on-off element becomes off-state, is recorded in C _LcFully kept with the electric charge on the Cs.Accompanying drawing 7 drives synoptic diagram for basic circuit structure and the row order of existing a-SiTFT-LCD.Its course of work is: driver sequentially feeding sweep trace G1, G2, G3 ..., the Gn address signal, and by the X driver supply with synchronously signal wire D1, D2, D3 ..., the Dm shows signal.During each is selected, the signal that is recorded in each pixel capacitance will remain to before next address signal arrival, and liquid crystal pixel is driven.The quasistatic that realizes LCD shows.This display mode display image of lining by line scan.There is the flicker of interline flicker and interframe.Accompanying drawing 6 is for to realize single pixel equivalent schematic of the present invention with a-Si TFT-LCD LCD.Contrast accompanying drawing 5 and accompanying drawing 6 can find out that accompanying drawing 6 makes a farfetched comparison the many TFT switches of Fig. 5, a memory capacitance, a control line Vx.TFT1 in the accompanying drawing 6 and C _S1Be equivalent to the latch 1 in the accompanying drawing 3, the TFT2 in the accompanying drawing 6, C _S2Be equivalent to the latch 2 in the accompanying drawing 3, C _LcBe equivalent to the pixel in the accompanying drawing 3.See accompanying drawing 8 by the a-Si TFT LCD schematic equivalent circuit that accompanying drawing 6 equivalent electrical circuit are formed, its course of work is: V driver sequentially feeding sweep trace G1, G2, G3 ..., the Gn address signal, and by the X driver supply with synchronously signal wire D1, D2, D3 ..., the Dm shows signal, in each selection phase, be recorded in each C _S1On signal remain to before next address signal arrives.Frame signal scanning input finish before the next frame signal scanning input beginning in this time (in the frame inverse scan phase) Z driver supply with synchronously X1, X2, X3 ..., the Xn control signal, the corresponding CS1 of each pixel is gone up the shows signal that keeps is input to corresponding C _S2, C _LCOn.Each pixel C _S2, C _LCThe signal that keeps drives pixel and shows, and remains to the next frame signal when arriving.The also line output that realizes a-Si TFT-LCD LCD shows.Interline flicker and interframe flicker that former three end active-matrix liquid crystal displays exist have been eliminated.Need to prove, in accompanying drawing 8 active-matrix liquid crystal displays as accompanying drawing 6 compositions, require C _S1＞＞C _S2+ C _LC, could guarantee when parallel input C _S1On voltage and (C _S2+ C _LC) on the voltage approximately equal, thereby guarantee the accuracy of display image.Active device on the accompanying drawing 8 and memory capacitance can be integrated on the liquid crystal board.

Adopting in the accompanying drawing 8 equivalent schematic operational modes, adopt two TFT and storage capacitors to form two latchs, is one of example of the present invention.Latch in the equivalent schematic also can adopt integrated circuit to constitute latch, can reach better demonstration visual effect.

Claims

1, adopts two-stage latch means with signal addressing input function, latch function, driving function, has serial scan (addressing input) on the composition function, and line output drives the string that shows---and conversion equipment, realize the display pointwise line by line or the input of lining by line scan (addressing input), and the run simultaneously method of demonstration of line output driving pixel.Its method principle equivalent schematic is an accompanying drawing 3, and the equivalent schematic of one of its concrete application example is an accompanying drawing 8.

2, the concrete application example one in the claim 1 just for one of concrete utilization of the present invention is described, does not limit the present invention and applies to other display device and realize the present invention, is not limit range of application of the present invention and application approach yet.Can adopt and control the addressing input respectively, any device that parallel drive shows is realized the purpose that serial scan input of the present invention and line output show.

3, in one of concrete utilization example in the claim 1, and the line output demonstration, can be that all pixels of whole display show synchronously, also can be the multirow (or multiple row) of all pixels shows synchronously.Also can be the combination in any of any a few row or several row, display is divided into any several zone show synchronously respectively.It also can be the method that the multirow (or multiple row) of other combination in any shows with different Frequency Synchronization respectively.

4, the latch means in the claim 1 is meant the latch means with scanning input addressing function, latch function, driving function, does not limit and adopts which kind of device.Latch means wherein is meant the equivalent example on the function, has any device of signal latch function.The right that requires is to utilize to have the serial addressing of latching input signal, then and the method that shows of line output.

5, in the claim 1 and the display packing in 4, in the parallel display control method of latch, do not limit the identical frequency of frame frequency that adopts shows signal.Controlling the display frequency of running simultaneously of display, can be n times of shows signal frame frequency.N is a positive count, and the value of n depends on the physical characteristics of the display of employing, or adopts different parallel display frequencies according to the display effect that will reach.

6, in the claim 1, the serial scan of explanation input, and line output drives demonstration, i.e. serial scan input, parallel drive demonstration.Do not limit and adopt which kind of addressing mode, do not limit yet which kind of adopts drive display mode.Can adopt the serial addressing input of any-mode, parallel drive shows.Realize the serial addressing input of display, the parallel demonstration exports.

7, the serial scan in the claim 1 (addressing) input does not limit pointwise (addressing) input of lining by line scan.Can be every row parallel (addressing) input, serial scan line by line (addressing) input.Also can be multirow scanning (addressing) input respectively synchronously, every frame synchronization is parallel to be shown.

8, do not limit the kind and the version of serial scan (addressing) input and running output device in the claim 1, do not limit the structure and the constituted mode of display yet.Can adopt any kind of and version or constituted mode, reach serial scan (addressing) input, the method that parallel synchronous shows.