CN1379481A - MOS package and its making method - Google Patents
MOS package and its making method Download PDFInfo
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- CN1379481A CN1379481A CN 01109526 CN01109526A CN1379481A CN 1379481 A CN1379481 A CN 1379481A CN 01109526 CN01109526 CN 01109526 CN 01109526 A CN01109526 A CN 01109526A CN 1379481 A CN1379481 A CN 1379481A
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Abstract
This invention relates to a MOS (metal-oxide-semiconductor) component with its grid formed in the substrate channel and the bottom of the grid is on the same depth as source and drain so as to avoid completely forming unwanted diffusion area and increase the effective channel length. According to the processing method of improving MOS component in this invention, the said method contains the following steps: using the existing technology to form a heavy doped area, etching the substrate to define grid channel depositing polysilicon material to cover the substrate and channels, etching the polysilicon material to leave out the polysilicon material in the channel only. It's unnecessary to form light doped and drain areas any more in producing the semiconductor components.
Description
The present invention relates to a kind of metal-oxide-semiconductor (MOS) (Metal Oxide Semiconductor, MOS) assembly, and be particularly related to and a kind ofly have the flush type grid and be formed at and improve in the channel region and metal-oxide semiconductor assembly with self-aligning source/drain/drain electrode structure.The invention still further relates to the manufacture method of above-mentioned metal-oxide semiconductor assembly.
Fig. 1 is that a kind of metal-oxide semiconductor assembly sketch of the prior art is (wherein, indispensable in typical metal-oxide semiconductor assembly, and for the unessential characteristics of shortcoming of understanding prior art, such as grid oxic horizon and field oxide region etc., be omitted with simplified illustration.)。Metal-oxide-semiconductor (MOS) 100 is formed at at have first conductive state the semiconductor-based end 102 of (such as the P type), and grid 104 is formed in the substrate 102, has the heavy doping of first conductive state; And be source area 106 and drain region 108 in grid 104 down either side, both all have the heavy doping (such as the N type) of second conductive state.
One of them problem of known metal-oxide semiconductor assembly is exactly so-called short channel effect (Short Channel Effect), and as shown in Figure 1, channel 110 is the zone that is positioned at grid 104 belows, and between source area 106 and drain region 108; Channel region is more little, and the breakdown voltage of metal-oxide semiconductor assembly (Breakdown Voltage) is just low more.One of reason that causes short channel effect is that the heavy doping meeting of source electrode and drain region 106,108 causes the part dopant ion to diffuse into substrate 102 from source electrode and drain region 106,108; Therefore as shown in the figure, the diffusion region 112 with second conductive state extends between grid 104 belows and source electrode and the drain region 106,108.This can shorten the effective length of channel 110, and the effective length that shortens can make the breakdown voltage of metal-oxide semiconductor assembly become lower, and becomes inapplicable.
A kind ofly known be, make metal-oxide semiconductor assembly with lightly doped region in order to the method that reduces short channel effect, be commonly referred to as lightly doped drain (Lightly Doped Drains, LDDs).Fig. 2 is known a kind of sketch with metal-oxide semiconductor assembly 200 of lightly doped drain.
The manufacture method of metal-oxide semiconductor assembly 200 is as described below: at first, substrate 202 with first conductive state is provided, form one deck polysilicon layer and cover substrate 202, polysilicon layer is defined to form grid 204 again, this grid 204 may have the doping of first conductive state.As the cover curtain, will have the dopant ion of second conductive state with grid 204, and implant with low concentration and form lightly mixed drain area 204 in the substrate 202.Then, layer of oxide layer is deposited on the surface that whole substrate 202 comes out, carries out anisotropic etching to form side wall spacer 206.At last, utilize grid 204 and side wall spacer 206 conduct cover curtains, implant the dopant ion of high concentration, to form source electrode and drain region 208,210 with second conductive state.
Because lightly mixed drain area is not highly doped, the amount that dopant ion diffuses into substrate can reduce.Therefore, extend between grid 204 belows and source electrode and the drain region 208,210, the diffusion region 212 with second conductive state can be less, reduces short channel effect with the method.
The another one problem of existing metal-oxide semiconductor assembly is exactly aiming between grid and source/drain.The position of grid should be aligned between source electrode and the drain region very accurately, if grid can't extend to source electrode and drain region, it is imperfect that channel will become, and make assembly to operate.A kind of solution to the problems described above is to form grid, makes it can be overlapping with source electrode and drain electrode, and overlapping part should be enough big, with the permissible error (Tolerance) of tolerance cover curtain location and in source electrode and drain diffusion step the variable quantity of sideways diffusion., overlappingly may form parasitic capacitance at grid and source/drain interpolar, in order to reduce the generation of parasitic capacitance, grid can self-aligning form be made, to reduce overlapping part.A kind ofly carry out self-aligning method and be, utilize ion to implant or diffusion as mentioned above, make source electrode aim at the edge of grid with drain electrode, in the method, silicon wall system is in order to the cover curtain of conduct formation lightly doped drain between grid and sidewall.
Therefore, utilize and reduce short channel effect to increase effective channel length, the method that still can aim at formation gate/source/drain electrode automatically is to be worth development.
In view of this, one of main purpose of the present invention is exactly to be to provide a kind of metal-oxide semiconductor assembly, and wherein the grid fauna is imbedded in the intrabasement raceway groove.
Another main purpose of the present invention is to provide a kind of metal-oxide semiconductor assembly exactly, and wherein the degree of depth of its channel equates with source/drain regions joint (Junction).
Another main purpose of the present invention is a kind of metal-oxide semiconductor assembly is provided exactly, has better efficient channel length.
A main purpose more of the present invention is to provide a kind of self-aligning metal-oxide semiconductor assembly exactly, and grid and source/drain are not overlapping.
The present invention also has a main purpose to be to provide a kind of self-aligning metal-oxide semiconductor assembly exactly, does not need extra step to form lightly mixed drain area.
According to above-mentioned and other purpose of the present invention, a kind of semiconductor subassembly is proposed, its grid is formed in the intrabasement raceway groove, and preferably the bottom of grid is near the source electrode position identical with the degree of depth of drain region.With this, can eliminate any undesired diffusion zone fully, and increase efficient channel length.
Make the preferred approach of the metal-oxide semiconductor assembly of above-mentioned improvement according to the present invention, comprise the following steps: the substrate with first conductive state is mixed, to form the heavily doped second conductive state zone, this step can arrive any cover curtain technology.In the substrate of mixing, define gate pattern.The etching substrate is to define grid groove in substrate.With polycrystalline silicon material deposition cover in the substrate with raceway groove in.Polycrystalline silicon material can be with existing mode first conductive state that mixes, and this step is also without any need for a cover curtain technology.The polycrystalline silicon material that etching is mixed only stays the polysilicon in the raceway groove, forms grid with this.
Assembly of the present invention and method for production have solved the problem of mentioning in above-mentioned known technology, the raceway groove in doped region has formed the grid between source electrode and drain region, so therefore do not have any diffusion zone below grid, can improve efficient channel length with this.It is noted that at this, do not need additionally to form lightly mixed drain area when making this metal-oxide semiconductor assembly.In addition, because grid system is formed in the raceway groove, so can be aligned in automatically between source electrode and the drain electrode.But, because do not have overlappingly at grid and source/drain interpolar, produce so between grid and source/drain, do not have parasitic capacitance.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent, especially exemplified by a preferred embodiment, and conjunction with figs., be described in detail below:
Fig. 1 and Fig. 2 are the profiles of known metal-oxide semiconductor assembly;
Fig. 3 is the profile according to a kind of metal-oxide semiconductor assembly of preferred embodiment of the present invention;
Fig. 4 A-4D is the making flow chart according to a kind of metal-oxide semiconductor assembly of preferred embodiment of the present invention.
Embodiment:
Fig. 3 is the profile according to a kind of metal-oxide semiconductor assembly 300 of a preferred embodiment of the present invention.This metal-oxide semiconductor assembly comprises that tool first conductive state is (such as P
-) substrate 302, and comprise having the first conductive state heavy doping (such as P
+) flush type grid 304, this flush type grid 304 may equate with the top of substrate 302 fully.Source area 306 and drain region 308 are positioned at the both sides of grid 304, have second conductive state electrically opposite with first conductive state (such as N
+) heavy doping.Oxide layer or other insulating barrier 310 separate grid 304 and source electrode 306 and drain electrode 308, and channel 312 is the bottom that is placed in grid 304 of level.Lightly mixed drain area 314 may be because of the diffusion of heavily doped source electrode 306 with drain region 308 intermediate ions, and natural is formed in the substrate 302.
The more known metal-oxide semiconductor assembly of structure provided by the invention has more some advantages.The first because grid 304 is flush types, channel 312 can connect with source/drain and the degree of depth of bottom identical.The second, grid 304 is to be formed on etching to advance in the raceway groove of substrate, and is placed between source electrode and the drain electrode 306,308, is not above it; Therefore, in substrate 302, the diffusion zone that shortens efficient channel length can not be formed, short channel effect and the breakdown voltage that improves metal-oxide semiconductor assembly can be avoided.The 3rd, as mentioned above, gate/source/drain electrode system aims at automatically, and does not have overlappingly, does not need extra processing step to form lightly mixed drain area.
In brief, providing a kind of improvement metal-oxide semiconductor assembly with preferable channel, is automatic aligning, and can make by the processing step few than known technology.
Embodiment:
Fig. 4 A-4D is the making flow chart according to a kind of metal-oxide semiconductor assembly 300 of preferred embodiment of the present invention.It is noted that the processing step of explanation can be used for the metal-oxide semiconductor assembly of many different kenels, such as the person skilled in the art can understand, the processing step of narration can be in order to make P type metal-oxide-semiconductor (MOS) or N type metal-oxide semiconductor assembly.
At first, in substrate, form a heavily doped region.Shown in Fig. 4 A, substrate 302 has first conductive state, such as P
-, utilize existing technology that the heavy doping of second conductive state is carried out in substrate 302, such as N
+For example, substrate is doped the boron ion, and dopant dose is 10
12Cm
-2, implant energy is 100keV.Shown in Fig. 4 A, this step forms a heavily doped region 402, and a light dope diffusion zone 404 can be right after thereunder.It below diffusion zone 404 substrate 302 with first conductive state.
Then, in the substrate of mixing, form grid groove.Shown in Fig. 4 B, deposit a thick-layer, such as being silicon dioxide layer or silicon nitride layer, depositional mode is such as utilizing Low Pressure Chemical Vapor Deposition (LPCVD) to carry out.Describe and be etched with and define gate pattern, the substrate that etching defined is such as (Reactive Ion Etch RIE) carries out, in order to define grid groove 406 with reactive ion-etching.Wherein, grid groove 406 is preferably the same with the bottom of diffusion zone 404 dark, and this raceway groove can separate heavily doped region 402 and diffusion zone 404, in order to define source electrode 306, drain electrode 308, and lightly mixed drain area 314.Form grid oxic horizon 310 on raceway groove 406 surfaces and substrate 302 surfaces, generation type is such as oxidizing process.
Afterwards, in raceway groove, form grid.Shown in Fig. 4 C, polysilicon 408 depositions are covered whole assembly, deposition process is such as being LPCVD.Polysilicon 408 can fill up raceway groove and cover substrate, and the method that this polysilicon can be known is carried out the doping of first conductive state, and for example with energy 40KeV, implant dosage is 10
15Cm
-2P type ion.Grid oxic horizon 310 can prevent that substrate surface is by ions diffusion.
Shown in Fig. 4 D, eat-back the polysilicon 408 of doping with known method, till the height of grid oxic horizon 310 at substrate surface, this etching step does not need cover curtain technology.Polysilicon is only stayed in the raceway groove and is defined grid 304.
Metal-oxide semiconductor assembly 300 can utilize known subsequent step to finish, and this follow-up step is that those skilled in the art can reach easily, so do not repeat them here.
Noticing that whole technical process only needs one cover curtain step and twice etching, for making metal-oxide semiconductor assembly, is a kind of quick and economic method.
The present invention has solved the problem that prior art is mentioned at the assembly and the manufacture technology of above-mentioned proposition, can improve efficient channel length, and breakdown voltage is improved.Note making this metal-oxide semiconductor assembly, do not need to form in addition lightly mixed drain area.In addition, because grid is formed in the raceway groove, be to be aligned in automatically between source electrode and the drain electrode.Moreover, because between grid and the source/drain and zero lap, produce so between grid and source/drain, do not have parasitic capacitance.
Though the present invention with the preferred embodiment explanation as above; yet it is not in order to limit the present invention; any personnel that have the knack of this technology; without departing from the spirit and scope of the present invention; when can be used for various modifications and upgrade, so protection scope of the present invention should be as the criterion with the protection range that claims were limited.
Claims (12)
1. metal-oxide semiconductor assembly is characterized in that comprising:
One substrate has one first conductive state;
One grid is arranged in this substrate with this first conductive state;
The one source pole district has and the electrical one second opposite conductive state of this first conductive state, is arranged in this substrate of a first side of this grid;
One drain region has this second conductive state, is arranged in this substrate of a second side of this grid;
One grid oxic horizon is separated this grid and this source area and this drain region.
2. metal-oxide semiconductor assembly according to claim 1 is characterized in that: a bottom of this grid is dropped in this substrate, has a same depth with a bottom of this source area and a bottom of this drain region.
3. metal-oxide semiconductor assembly according to claim 2 is characterized in that: channel system is defined in this grid, and the below between this source area and this drain region.
4. metal-oxide semiconductor assembly according to claim 1 is characterized in that: this source area and this drain region further comprise a light doping section respectively.
5. metal-oxide semiconductor assembly according to claim 4 is characterized in that: this light doping section diffuses to and an end of this a grid degree of depth inequality.
6. a manufacturing has the method for the metal-oxide semiconductor assembly of a flush type grid, it is characterized in that comprising the following steps:
Mix in a surface to a substrate with one first conductive state, to form one second conductive state;
In the substrate of mixing, form grid groove in the dry-etching mode, and the substrate of separating this tool second conductive state is to define source area and drain region;
Form grid oxic horizon on this grid groove surface with this substrate surface;
Fill this grid groove with polysilicon, in order to form grid.
7. method according to claim 6 is characterized in that: this doping step further comprises carries out heavy doping to this substrate surface, and at the other formation of this substrate surface one heavily doped region, and below this heavily doped region, form a light doping section.
8. method according to claim 7 is characterized in that: the step that forms this raceway groove further comprises and forms this raceway groove, makes a bottom of itself and this light doping section have a same depth.
9. method according to claim 6 is characterized in that: after the step that forms this raceway groove, further be included on the surface of this raceway groove, with formation one grid oxic horizon on this substrate surface.
10. method according to claim 6 is characterized in that: this step of filling this raceway groove with polysilicon further is included in deposit spathic silicon in the substrate, to fill this raceway groove and to cover this substrate surface.
11. method according to claim 10 is characterized in that: further comprise to this first conductive state of polysilicon doping.
12. method according to claim 11 is characterized in that: the polysilicon that further comprises this doping of etching is to this substrate surface, and polysilicon is stayed in this raceway groove.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 01109526 CN1379481A (en) | 2001-03-30 | 2001-03-30 | MOS package and its making method |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 01109526 CN1379481A (en) | 2001-03-30 | 2001-03-30 | MOS package and its making method |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103872132A (en) * | 2012-12-07 | 2014-06-18 | 德州仪器公司 | Metal-oxide-semiconductor transistor (MOS) and method of fabricating same |
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2001
- 2001-03-30 CN CN 01109526 patent/CN1379481A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103872132A (en) * | 2012-12-07 | 2014-06-18 | 德州仪器公司 | Metal-oxide-semiconductor transistor (MOS) and method of fabricating same |
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