CN1379411A - Shift register with selective multiple shifts - Google Patents

Abstract

A shift register with selective multiple shifts is composed of a controller for outputing a timing signal and i shift signals (i=O-N), and a multi-shift circuit consisting of serially connected N register units comprising trigger and multiplexer. Each trigger outputs different bit addresses. The said multiplexers receive all the output signals of the controller. The j-th multiplexer (j=O-N-1) receives the bit address outputs of the triggers from j to j-(i+1).

Description

The shift register of selectivity multiple shift

The present invention relates to a kind of shift register, particularly relate to and a kind of storer is carried out the shift register of selectivity multiple shift that address refers to the position.

Fig. 1 illustrates an existing shift register 1.This shift register 1 is made of a plurality of D flip-flop DFF0-DFF3.Though, only show four D flip-flops in the drawings, yet the number of actual D flip-flop can be according to need and change and be not limited to four, at this for convenience of description, is representative with the shift register that comprises four D flip-flops.Each D flip-flop DFF0-DFF3 is when input end D has signal to enter, must wait until that input end T has the positive edge of clock signal Clock to trigger (becoming high level by low level) when entering, input signal just input end D institute input signal can be reached output terminal Q output, so can move to Next D flip-flop in regular turn in each sequential cycle.Though at this, setting D flip-flop DFF0-DFF3 for convenience of description triggers according to the positive edge of clock signal Clock and transmits signal, yet, in fact can be according to the needs of circuit design, the setting D flip-flop triggers or is just triggering with negative edge and transmitting signal according to the negative edge of clock signal Clock.Below cooperate Fig. 2 to Fig. 7 that an explanation is said in the displacement of input signal in proper order.

At first, input reset signal Reset (as Fig. 3), the action that each D flip-flop DFF0-DFE3 is removed earlier, make D flip-flop DFF0 be output as high level, and remaining D flip-flop DFF1-DFE3 output signal is a low level, so when the clock signal Clock that shows as Fig. 2 imports, the first positive edge at clock signal Clock triggered 11 o'clock, D flip-flop DFF0 output high level signal (Fig. 4) only, and remaining D flip-flop DFF1-3 output low level signal (as Fig. 5 to Fig. 7) all.Secondly, the second positive edge at clock signal Clock triggered 12 o'clock, the D flip-flop DFF3 that D flip-flop DFF0 is received is output as low level signal AD (3), so D flip-flop DFF0 output signal becomes low level (because the deferment factor of circuit itself, so the output signal AD of D flip-flop DFF0 (0) can postpone just to become low level after the second positive edge triggered for 12 a period of times), therefore D flip-flop DFF1 still can to receive D flip-flop DFF0 be high level AD (0) thus its output of output then be changed to high level (as Fig. 5), the output of D flip-flop DFF2-3 still is low level.Then, triggered 13 o'clock at the 3rd positive edge of clock signal Clock, only D flip-flop DFF2 is output as high level signal (as Fig. 6), and the output of remaining D flip-flop DFF0, DFF1, DFF3 is all low level.At last, triggered 14 o'clock at the 4th positive edge of clock signal Clock, only D flip-flop DFF3 is output as high level signal (as Fig. 7).So, shift register 1 is along with timing variations, then each D flip-flop DFF0-DFF3 exports high level signal in regular turn, therefore, the output signal of definable D flip-flop DFF0-DFF3 is address AD (0), AD (1), AD (2), AD (3) in regular turn, and each address points to the different word lines of memory crystal cell array respectively, open to control this address corresponding word lines, make several structure cell activations on this word line, at this moment, data can be write these structure cells or with data by reading in the structure cell.For instance, address AD (0), AD (1), AD (2), AD (3) represent article one word line, second word line, the 3rd word line, the 4th word line of storer in regular turn, so along with timing variations, these word lines are unlocked in regular turn, and data also can write these word lines in regular turn or be read by the structure cell on these word lines in regular turn.

So, can utilize high level signal to export and learn address, thereby open the word line of corresponding this address, the action that writes or read with structure cell this word line in which trigger.Yet, concerning shift register, except provide as the reading and writing address correct, speed also is an important issue.For shift register 1 in the past, moving to the N+2 address from N address need be through two sequential cycle.When so the data desire is jumped the address processing, for example after the data processing of corresponding N address is intact, skip the N+1 address, promptly desire is handled the data (will reading or write no matter be) of corresponding N+2 address, though these data when shift register 1 output address N all set, but still the two sequential cycles of need waiting for allow shift register 1 refer to that the position could use to address N+2, cause the delay of time.Therefore, the lifting of speed is restricted,, for example only needs a sequential cycle from N address to the N+2 address so jump the required time of position if can reduce address, even next all only need a sequential cycle during any address by the N address, can effectively reduce the data access time.

A purpose of the present invention is to provide a kind of shift register of realizing shortening the selectivity multiple shift of access time.

Another purpose of the present invention is to provide a kind of shift register of realizing the selectivity multiple shift of many data of zero access.

For achieving the above object, the shift register of a kind of selectivity multiple shift of the present invention, be to point to a unit cell arrays in order to produce address, the N row of this unit cell arrays have a word line respectively, respectively this word line has corresponding address value respectively, with address value along with this address signal, corresponding word lines is opened so that the structure cell on this word line is carried out reading and writing data, this shift register comprises a control circuit and a multiple shift circuit.This control circuit is in order to exporting an a clock signal and i displacement signal (0＜i＜N, i are positive integer), and when wherein a displacement signal was triggering level, then other displacement signal was positioned at not triggering level.This multiple shift circuit comprises N group serial register unit, respectively this register cell is made of a trigger and a multiplexer, respectively this trigger is exported different address, respectively this multiplexer receives the signal of these all outputs of control circuit, and j (0≤j≤N-1, j is an integer) individual multiplexer receives the output address of j to j-i+1 trigger, and corresponding respectively of having received in the address of this displacement signal respectively, respectively this multiplexer has received the trigger that address of selecting corresponding this triggering level displacement signal the address export the register cell of next stage to according to the displacement signal for triggering level in the displacement signal that has received from these.

The present invention is described in detail below in conjunction with drawings and Examples:

Fig. 1 is the synoptic diagram of shift register in the past.

Fig. 2 is the sequential chart of the clock signal of the shift register among Fig. 1.

Fig. 3 is the sequential chart of the reset signal of the shift register among Fig. 1.

Fig. 4 is the signal timing diagram that first trigger of the shift register among Fig. 1 is exported according to the sequential of Fig. 2 and Fig. 3.

Fig. 5 is the signal timing diagram that second trigger of the shift register among Fig. 1 exported according to the sequential of Fig. 2 and Fig. 3.

Fig. 6 is the 3rd signal timing diagram that trigger is exported according to the sequential of Fig. 2 and Fig. 3 of the shift register among Fig. 1.

Fig. 7 is the 4th signal timing diagram that trigger is exported according to the sequential of Fig. 2 and Fig. 3 of the shift register among Fig. 1.

Fig. 8 is the storer synoptic diagram of display application the present invention than Cui embodiment.

Fig. 9 is the partial schematic diagram of the present invention than the multiple shift circuit of Cui embodiment.

Figure 10 is the sequential chart of displacement clock signal among Fig. 9.

Figure 11 is the sequential chart of a displacement signal among Fig. 9.

Figure 12 is the sequential chart of another one shifting signal among Fig. 9.

Figure 13 is the address signal sequential chart that first order register cell is exported according to the signal of Figure 10, Figure 11 and Figure 12 among Fig. 9.

Figure 14 is the address signal sequential chart that second level register cell is exported according to the signal of Figure 10, Figure 11 and Figure 12 among Fig. 9.

Figure 15 is the address signal sequential chart that third level register cell is exported according to the signal of Figure 10, Figure 11 and Figure 12 among Fig. 9.

Figure 16 is the address signal sequential chart that fourth stage register cell is exported according to the signal of Figure 10, Figure 11 and Figure 12 among Fig. 9.

Figure 17 is the address signal sequential chart that the level V register cell is exported according to the signal of Figure 10, Figure 11 and Figure 12 among Fig. 9.

Figure 18 is the 6th grade of address signal sequential chart that register cell is exported according to the signal of Figure 10, Figure 11 and Figure 12 among Fig. 9.

Figure 19 is that the present invention is than the local sequential chart of Cui embodiment when reading.

Figure 20 be the present invention than Cui embodiment in writing fashionable local sequential chart.

Fig. 8 is the storer synoptic diagram of display application the present invention than Cui embodiment.In order to allow application of the present invention be easier to understand, at first do a brief introduction at storer.At this, storer 2 roughly is made of one N * M unit cell arrays 21, a data input buffer 23 and a sensor amplifier 25.This unit cell arrays 21 comprises N * M the structure cell (not shown) in order to temporal data.Each row of this unit cell arrays 21 have a word line respectively, make when this word line is opened, and also activation thereupon of this structure cell that lists, and each row has a bit line in order to when structure cell starts, writes structure cell with data or from the structure cell reading of data through this bit line.So this unit cell arrays 21 has N bar word line and M bit lines.These word lines electrically connect with the shift register 3 corresponding connections of present embodiment and the different address with shift register 3 outputs are corresponding respectively, make corresponding word lines open (repeating after the appearance) with the address that produces by shift register 3.These bit lines then are connected to data input buffer 23 and sensor amplifier 25 respectively.Data input buffer 23 desires to write the data of unit cell arrays 21 in order to breech lock by outside input, or strengthens the driving force that writes data rapidly correct data being written in the structure cell, or not only latch data but also strengthen the data-driven ability.Sensor amplifier 25 is in order to accelerate reading of data, because when chip design, consider to consume wafer area, so the driving force of structure cell itself can be very not strong (because of the reinforcement along with driving force, then the required area of structure cell also strengthens thereupon), in the case, if directly by the structure cell reading of data, except the cost long time, data-signal may be influenced by noise in the process that bit line transmits and produce error, make the numerical value possibility of read data signal wrong, thereby sensor amplifier 25 is designed to when data-signal has less difference, can judgment data signal correct value should be 1 or 0, and strengthens signal and make data-signal have enough driving forces.So sensor amplifier 25 can be accelerated reading of data, and the driving force of reinforcement data-signal is correctly to export the data transmission to outside, to use by the output terminal outputting data signals or for other elements.Below elaborate at the shift register of present embodiment, and represent with same-sign with previous shift register components identical.

At this, shift register 3 comprises a control circuit 4 and a multiple shift circuit 5 substantially.This shift register 3 receives a plurality of selection signals and a clock signal to export corresponding address signal AD, thereby the word line of corresponding this address signal AD is opened, can read data in these structure cells so that output via bit line and allow data on the data buffer 23 open structure cell on the word line or sensor amplifier 25 via the bit line input.

As Fig. 8, control circuit 4 receives two selection signal select1 and select2 and clock signal clock in order to decision bit location number of shift bits.The main application of control circuit 4 is to handle these input signals select1, select2 and clock, as change phase place, the driving force of signal, and these signals of correspondence produce two displacement signal shift1 and a shift2 and a displacement clock signal shift clock respectively, to export multiple shift circuit 5 to.At this, control circuit 4 comprises trigger and impact damper, to utilize the trigger breech lock to select signal select1, select2 and to strengthen driving force to produce corresponding displacement signal Shift1, Shift2 through impact damper, change so displacement signal shift1 and selection signal select1 have the identity logic level, and displacement signal shift2 has the variation of identity logic level with selecting signal select2.Each selects signal select1, select2 is a pulse wave signal that changes in high level and low level.In cycle, can only have one to select signal to be positioned at high level at same clock pulse, promptly wherein one select signal select1 (or select2) when being positioned at high level, then another selects signal select2 (or select1) must be positioned at low level.At this, also setting multiple shift device 5 triggers according to the positive edge of clock signal Clock and carries out displacement, yet, in fact can be according to the needs of circuit design, for example set multiple shift device 5 and trigger or just triggering with negative edge and transmitting signal according to the negative edge of displacement clock signal shift clock, it is cited to be not restricted to present embodiment.At this, each selects time that the positive edge of signal select1, select2 triggers to trigger (repeating after the appearance) early than the positive edge in corresponding clock pulse cycle, and select signal select1 for selection address number of shift bits is the signal of 1 (promptly increasing progressively number is 1), be the signal of 2 (promptly increasing progressively number is 2) and select signal select2 for selecting the address number of shift bits.In other words, when in a sequential in the cycle, if when selecting signal select1 to be high level, then next output address can increase progressively 1[such as AD (1) to AD (2)], if when selecting signal select2 to be high level, then next output address can increase progressively 2[such as AD (1) to AD (3)].

At this, multiple shift circuit 5 is that the register cell RE (0) by N serial connection is constituted to RE (N-1), and last register cell RE (N-1) also is connected in series back first register cell RE (0).Each register cell RE (0)-RE (N-1) is made of a D flip-flop DFF (0)-DFF (N-1) and a multiplexer MUX (0)-MUX (N-1).And be output as address AD (0) with the D flip-flop DFF (0) of first register RE (0), the D flip-flop DFF (1) of second register RE1 is output as AD (1), by that analogy, utilize ensuing register RE (2)-RE (N-1) to produce address AD (2)-AD (N-1), and with the address AD of high level as pointing to address.The output address that each multiplexer MUX (0)-MUX (N-1) receives with the D flip-flop of one-level receives displacement signal shift1, shift2 and displacement clock signal shiftclock to output address to the second input end input2 of the D flip-flop of first input end input1, previous stage and by control circuit 4, and then of selecting to import according to displacement signal shift1, shift2 in the address of input1 or input2 of multiplexer enters the next stage D flip-flop that is right after.At this, when displacement signal shift1 is high level " 1 ", then will export the D flip-flop (be about to first input end input1 and receive address output) of next stage with the output address of the D flip-flop of one-level to, and when displacement signal shift2 is high level " 1 ", then the output address of the D flip-flop of previous stage is exported to the D flip-flop (being about to the address output that the second input end input2 receives) of next stage.Whereby, can utilize the use of multiplexer and displacement signal shift1, shift2, make alternative output increase progressively 1 address or increase progressively 2 address.In order to allow the present invention be easier to understand, hereinafter, utilize an example explanation at the address shifting process.

Please in the lump with reference to Fig. 9, supposition N equals 6 in this example, when the beginning shift motion, must utilize reset signal Reset remove because of moved in the past in each D flip-flop DFF (0)-DFF (5) residual data, effectively to avoid the generation of misoperation, only first D flip-flop DFF (0) is input as the reset signal of high level " 1 ", make the address AD (0) of its exportable high level " 1 ", but other D flip-flops DFF (1)-DFF (5) then is input as the reset signal of low level " 0 ", removing the internal data of D flip-flop DFF (1)-DFF (5), so address of output low level all.At first cooperate with reference to Figure 13 to Figure 18, in at the beginning, two address signals that each multiplexer MUX (0)-MUX (5) is received are all 0, but after first the positive edge as the displacement clock signal shift clock of Figure 10 triggers 51, cooperate among Figure 13 to Figure 18 and show, because the relation of aforementioned homing action, so only the output address signal AD (0) of first order D flip-flop DFF (0) is a high level, and all the other D flip-flop DFF (1) are all low level to output AD (1)-AD (5) of DFF (5), so pointing to address is high level AD (0), and only the second input end input2 with the first input end input1 of the multiplexer MUX (0) of one-level and the multiplexer MUX (1) of the next stage (promptly referring to the second level) that is right after receives high level address signal AD (0), and the residue input end of all the other multiplexers receives and is all low level address signal.Secondly, triggering at displacement clock signal shift clock at 52 o'clock at the second positive edge is that the selection signal is that shift2 is a high level, and owing to select the time of the positive edge triggered time summary of signal shift2 early than the positive edge triggering of clock signal, so multiplexer MUX (0)-MUX (5) meeting elder generation is with the D flip-flop that outputs signal to next stage of the D flip-flop of the previous stage of the reception of the second input end input2, so the signal of only partial multiplexer MUX (1) output is a high level, and other multiplexers MUX (0), MUX (2)-MUX (4) output signal is all low level, therefore after the second positive edge triggers 52, third level trigger DFF (2) exports high level address signal AD (2), and this moment, the sensing address of address register was AD (2).Then, in the cycle, selecting signal shift1 is high level in ensuing the 3rd sequential, so only the trigger DFF (3) of the fourth stage receives high level signal, the sensing address of address register becomes AD (3).At last, in the cycle, selecting signal shift2 is high level, so the sensing address of address register becomes AD (5) in the 4th sequential.

As showing among above-mentioned example description and Figure 10 to Figure 18, the sensing displacement AD (0) of shift register only needs a sequential cycle to AD (2) and AD (3), so in this example provable, increase progressively 1 or 2 no matter point to address, all only need a sequential cycle to realize, obviously different existing shift register need increase progressively at 2 o'clock if point to address, then needed for two sequential cycles realized, so the present invention can shorten dramatically compared to existing shift register and produce the time increase progressively 2 sensing address, therefore whole sensing address generation time can effectively shorten, so the memory data access time also can effectively shorten.

Secondly, according to the embodiment of Fig. 8, just read respectively with writing and point to that address institute is corresponding to be read or write data and do a brief introduction.Simultaneously, data often were not an only data input or read for the speeds up memory data processing speed today.So in this example, set this storer and can write or read two data, make and respectively point to address except the word line of control and this sensing address same sequence number, more control the word line of next bar, for example: sensing address AD (0) control two word line WL0, WL1, sensing address AD (1) are control two word line WL1, WL2 or the like, cause an address to point to two adjacent word lines.Following elder generation reads order to data and explains.

Please in the lump with reference to Figure 19, the component register unit of intercepting multiple shift circuit 5 among this figure, supposition was originally read address and was pointed to AD (j-1) in advance, so the first output data Outputl is the data D (j-1) in the structure cell on the j-1 word line, and the second output data Output2 is the data D (j) in the structure cell on the j word line.First sequential that next reads sequential in the cycle displacement signal shift1 be high level, so the shift register address points to AD (j), the first output data Output1 is data D (j), and the second output data Output2 is data D (j+1).Second sequential that then reads sequential in the cycle displacement signal shift2 be high level, so the shift register address points to AD (j+2), the first output data Output1 is data D (j+2), and the second output data Output2 is data D (j+3).Secondly, third and fourth and five sequential that read sequential in the cycle displacement signal shift1 be high level, so the shift register address points to AD (j+3), AD (j+4), AD (j+5) in regular turn, the first output data Output1 is data D (j+3), D (j+4), D (j+5) in regular turn, and the second output data Output2 is data D (j+4), D (j+5), D (j+6).And the 6th and seven sequential that read sequential in the cycle displacement signal shift2 be high level, so the shift register address points to AD (j+7), AD (j+9) in regular turn, the first output data Output1 is data D (j+7), D (j+9) in regular turn, and the second output data Output2 is data D (j+8), D (j+10).So obviously as can be known, in the present invention, because no matter address points to why increase progressively number, all only need a sequential cycle to realize, so the corresponding data that these point to address also can be continuously by sensor amplifier 25 outputs, known relatively address incremental number order then needed the more time to produce greater than 1 o'clock and points to address, and caused the increase of whole time for reading, so the present invention also can effectively shorten time for reading.In addition, the present invention can utilize each address corresponding word lines number of design, in same sequential, read many data, and the user can utilize displacement signal to control the quantity of desiring reading of data, to shorten the data read time, when the displacement signal shift2 of for example continuous two sequential in the cycle is all high level, then the output data of the first output data Output1 and the second output data Output2 does not repeat, so the time of data read can reduce by half, even also make each address point to two word lines at shift register in the past, export two stroke counts synchronously and shorten the data read time according to this, but because address skips a grade and increases progressively (promptly referring to add 2) and increase progressively the sequential cycle that need double compared to usual address, so the time for reading of storer and shortening not yet in effect.

Next cooperate Figure 20 that writing of data done a brief introduction.With aforementioned read the action identical, supposition originally write address and pointed to AD (j-1) in advance, word line W (j-1) is opened, so first in the data input buffer 23 writes the data D (j-1) that desires to write this address among the data Output1 and writes in the structure cell on the j-1 word line, and owing to the mistake for fear of data writes, so on the word line and be provided with a detecting device, only when the displacement signal shift2 that confirms the next sequential cycle is high level, just two word lines of address correspondence are all opened, otherwise only opened word line with address same word preface.First sequential that next reads sequential in the cycle displacement signal shift1 be high level, so the shift register address points to AD (j), and because next sequential cycle meta displacement signal shift2 is a high level, so word line w (j) and w (j+1) open, two input data D (j) and D (j+1) be corresponding respectively to be write in the structure cell of word line w (j) and w (j+1).Second sequential that then reads sequential in the cycle displacement signal shift2 be high level, so the shift register address points to AD (j+2), input data D (j+2).Secondly, third and fourth and five sequential that read sequential in the cycle displacement signal shift1 be high level, so the shift register address points to AD (j+3), AD (j+4), AD (j+5) in regular turn, import data D (j+3), D (j+4), D (j+5) in regular turn, and the displacement signal shift2 in the cycle is a high level by the 6th sequential, and pointing to AD (j+5) in address has second data D (j+6) input simultaneously.And the 6th and seven sequential that read sequential in the cycle displacement signal shift2 be high level, so the shift register address points to AD (j+7), AD (j+9) in regular turn, the next sequential of pointing to AD (j+7) at address in the cycle displacement signal shift2 be high level, so import two data D (j+7), D (j+8) simultaneously, and address is when pointing to AD (j+9), input data D (j+9).So in the present invention, because each generation of pointing to address all only needs a clock signal, can avoiding in the past, shift register surpasses for 1 the required time that has more of address that increases progressively because of producing, therefore the present invention also can effectively shorten in the data address sensing time, simultaneously, owing to can utilize this advantage to write many data simultaneously, thereby also can effectively shorten the data write time.

It should be noted that, though in the present embodiment, for convenience of description, only utilizing address to increase progressively 2 example illustrates, but those skilled in the art should know, only need to increase and select signal and allow multiplexer accept the output of more a plurality of D flip-flops, then can reach no matter address increases progressively the advantage what all only need a sequential cycle, for instance, desire allows address increase progressively at 3 o'clock, then only need make each multiplexer MUX (0)-MUX (N-1) receive one again and select signal shift3, and except receive same one-level (for example: AD (j)) with the output address of previous stage D flip-flop (for example: AD (j-1)), the output address of two-stage D flip-flop before more receiving (for example: AD (j-2)), so can reach and make address increase progressively 3 effects (for example: AD (j-2) is to AD (j+1)) that but only need a sequential cycle.Address points to the effect which address required time all only needs a sequential cycle so the present invention can reach really, is not limited to address cited in the present embodiment and increases progressively 2 or 3.

According to aforementioned, the present invention has the following advantages really:

1. no matter differ how many displacements between two sensing address, all can make a sensing address directly be displaced to next in the cycle in a sequential and point to address:

Make in the present invention the individual displacement of control circuit 4 output i (0＜i＜N, i are positive integer) Signal shift, and (0≤j＜N, j is for just to make the multiplexer MUX (j) of each register cell Integer) receives these displacement signals and receive these D flip-flops DFF (j) to DFF (j-I+1) address AD (j)-AD (j-i+1) output, each displacement signal is respectively corresponding simultaneously One of the output of the D flip-flop that has received, and these displacement signals are to become in high-low level The signal of changing and in same sequential one displacement signal can only to be arranged in the cycle be high level, thereby make many Multiplexer MUX (j) can come according to the displacement signal of high level from these address AD (j)-AD (j-i+1) select an address to export next stage D flip-flop DFF (j+1) in, so The sensing of the address of displacement can be by AD (j-i+1) to AD (j+1), the address of least displacement at most Sensing can be by AD (j) to AD (j+1), so no matter address point to displacement what, all can be sharp Make in a sequential with displacement signal to point to required address in the cycle, so comparing in the past, displacement refers to To increasing progressively how many levels, then need what sequential cycles to produce address and point to, so the present invention is true Have in fact alternative multiple displacement and shorten the displacement effect of sensing time.

2. many data of zero access:

As described above, shift register of the present invention really can be done displacement with fast speed and point to, so when being applied to produce in the storer sensing of read/write address, the time that address points to can shorten, and some data are all carried out access with a sequential cycle, the speed of data access can promote, in addition, and can require to make the corresponding respectively word line that surpasses of each address according to the user, cause the user can utilize displacement signal to select to determine many of accesses or data, so can make the storer scope of application more extensive, the time of pointing to because of address effectively shortens simultaneously, so the speed of many data of access more can effectively improve.

Claims (4)

1. the shift register of a selectivity multiple shift, point to a unit cell arrays in order to produce address, the N row of this unit cell arrays have a word line respectively, respectively this word line has corresponding address value respectively, with address value along with this address signal, corresponding word lines is opened so that the structure cell on this word line is carried out reading and writing data, it is characterized in that this shift register comprises:

One control circuit, in order to exporting an a clock signal and i displacement signal (0＜i＜N, i are positive integer), and when wherein a displacement signal was triggering level, then other displacement signal was positioned at not triggering level; And

One multiple shift circuit, comprise N group serial register unit, respectively this register cell is made of a trigger and a multiplexer, respectively this trigger is exported different address, respectively this multiplexer receives the signal of these all outputs of control circuit, and j (0≤j≤N-1, j is an integer) individual multiplexer receives the output address of j to j-i+1 trigger, and corresponding respectively of having received in the address of this displacement signal respectively, respectively this multiplexer has received the trigger that address of selecting corresponding this triggering level displacement signal the address export the register cell of next stage to according to the displacement signal for triggering level in the displacement signal that has received from these.

2. the shift register of selectivity multiple shift as claimed in claim 1 is characterized in that:

Respectively this trigger is a D flip-flop.

3. the shift register of selectivity multiple shift as claimed in claim 1 is characterized in that:

Respectively this shift signal is the signal that changes in high-low level, is triggering level not and be triggering level and low level with the high level.

4. the shift register of selectivity multiple shift as claimed in claim 1 is characterized in that:

The quantity i of these displacement signals is the positive integers greater than 1.

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