CN1377162A - Data transmission device and method between physical layer and network layer - Google Patents

Data transmission device and method between physical layer and network layer Download PDF

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Publication number
CN1377162A
CN1377162A CN01112033A CN01112033A CN1377162A CN 1377162 A CN1377162 A CN 1377162A CN 01112033 A CN01112033 A CN 01112033A CN 01112033 A CN01112033 A CN 01112033A CN 1377162 A CN1377162 A CN 1377162A
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frame
field
sapi
value
data transmission
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CN100479418C (en
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余少华
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WUHAN INST OF POSTS AND TELECOMMUNICATIONS SCIENCE MINISTRY OF INFORMATION IND
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WUHAN INST OF POSTS AND TELECOMMUNICATIONS SCIENCE MINISTRY OF INFORMATION IND
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Abstract

The invention relates to a method and device for transferring data between a device on a physical layer and a device on a network layer. A variable SAPI value is adopted to encapsulate the all-new frame/unframed LAPS to SPE/VC of HDLC frame like. The LAPS frame consists of tag series, an addrss field, and control field, SAPL, an information field (Ipv4, Ipv6, or PPP protocol data unit), FCS field, an end tag series. The tag series indicates the start and end of a LAPS frame. The invention can adapt Internet/Intranet to telecom infrastructures. The IP signal can directly be adapted to SDH/SONET, simplified SDH/SONET, or other devices on the physical layer such as routes, exchanger etc. The invention can be used in the 32-bit processing, possessing adaptability.

Description

Data transmission device between physical layer and the network layer device and method
The present invention relates to the data network relevant with Internet/Intranet communicates by letter with open system, particularly relate to data transmission device and method between physical layer and the network layer device, for example the equipment such as interface unit of core and edge router, switching equipment, the network access equipment based on IP (Internet Protocol), ply-yarn drill and use in using as gigabit at a high speed are used for the IP signal directly is fitted to SDH (SDH (Synchronous Digital Hierarchy))/SONET (Synchronous Optical Network), simplifies SDH/SONET, wavelength division multiplexing (WDM) and other physical layer equipment.
At present, what main telecommunication apparatus or transmission channel were transmitted is IPv4 (Internet Protocol sheet basis 4) packet, to support the IP agreement and the various application relevant with IP are provided.One of best transmission channel is the basis that SDH and associated wavelength division multiplexing (WDM) Optical Transmission Network OTN are considered to broadband IP and broadband integrated services digital network (B-ISDN) physical layer.Over past ten years, SDH/SONET is extensive use in the whole world.
ITU (International Telecommunications Union)-TG.707 has narrated advantage and the multiplexing method of SDH, stipulated that the basic principle of SDH series speed, Network-Node Interface (NNI) and frame structure, 9 row take advantage of N * 270 row (N=1 wherein, 4,16, the international interconnection mode of total frame length 64,256), section overhead (SOH) and byte allocation thereof, synchronous transfer module (STM), element is multiplexing and be mapped as the form of STM-N at the NNI place.
The standard that the North America is equivalent to SDH is SONET, and it is the U.S. (ANSI, the American National Standards Institute) standard that is used for synchronous data transmission on the optical media.It is for digital network can international interconnect that people adopt standard, and existing conventional transmission system can pass through the advantage that some auxiliary devices be shared optical media.The basic rate of SONET is 51.84Mbps, and the multiple of basic rate is well-known light carrier series (STS-M, M=1,3,12,48,192,678).SONET is eight hytes (octet) the synchronous multiplexing scheme that has defined series of standards speed and form.SONET does not resemble its name, and it not only is used for optical link, has stipulated electrical code for monomode fiber, multimode fiber and CATV (cable TV) 75 ohm coaxial cable yet.Its transmission rate is the integral multiple of 51.84Mbps, can carry the T3/E3 bit synchronization signal, its also strong suggestion simultaneously adopts that G.703 the E1/E3/E4/T1/E2/T4 interface is as the physical layer of IP-over-SDH/SONET (IP is fitted on the SDH/DONET), and it is the domestic consumer's cut-in method by LAN (local area network (LAN)).
Two kinds of standards of SDH and SONET can both provide flank speed to arrive a series of line speeds of 9.953Gbps, and physical line rate might reach 39.813120Gbps.
Current IP is PPP (comprising LCP (LCP) and NCP (Network Control Protocol)) the over HDLC (High-Level Data Link Control) that utilizes RFC 2615 agreements to the adaptation method of SDH/SONET, comprises RFC 1661, RFC 1662, RFC 1570, RFC 1547, RFC1340.PPP can encapsulate more than 30 procotol that comprises IPv4, and still, PPP is for adaptive proposition between the agreement of modem dialup (fire compartment wall) at first, and the algorithm of PPP is very complicated.
When applying PPP over SONET or SDH, there is following deficiency:
(1) no standard support virtual container application at a low price, this will cause IP over SDH/SONET
The edge that can not be applied to Internet inserts;
(2) for 2.5Gbps and above speed, the hardware spending of forwarding engine is excessive, the spy
Be not for IP over SDH use to simplify the WDM of SDH/SONET frame structure especially
So.Because in RFC 2615, LCP and magic number (Magic Number) are used in suggestion,
The both is very complicated;
(3) under the situation of having used RFC 2615, the timer that resends among the PPP is default
Value is 3 seconds, and is too slow for high-speed link.In special engineering is used, requirement
The speed range of supporting is that (variation is approximately 2Mbit/s (megabit per second) to 10000Mbit/s
4032 times), therefore, the timer value that resends should be determined according to the circuit roundtrip delay
Fixed.But not definition in RFC 1619, this will cause with the equipment between the different vendor
May produce uncertainty when interconnected;
(4) IP over SDH/SONET in do not used the filling field of PPP in fact,
But its use still is retained among the RFC 2615, and in addition, this fills field and requires at the receiving terminal tool
Distinguish information field that defines in the RFC standard and the function of filling field fully, this has increased again
Processing expenditure.
(5) LCP comprises 10 configuration packet, 16 incidents and 12 actions, and more than 130
Individual protocol status is very difficult and costliness for the packet switch that realizes light.In order to illustrate
Above situation, table 1 show LCP when using traditional PPP over SONET/SDH standard
The incident of finite state machine and action schedule.
(6) because the introducing of PPP, cause between two routers link-attached parcel from
(approximately) 40 bytes of Ipv4 drop to minimum (approximately) 10 bytes of PPP, maximum like this bag
Ratio between the parcel is raised to 1600/10 (=160) from 1600/40 (=40), i.e. bag
Span (being decided to be the ratio between maximum bag and the parcel for the time being) increases 4 times.Thereby make router
Navigate to based on the Synchronous Processing of cell or isometric parcel (as 64 bytes) difficulty more, make
Get network performance parameter: packet loss, time delay, delay variations etc. are variation greatly.Up=(this layer is Tlu=This-Layer-Up lower layer is Up (low layer is last) action of table 1 event-action list event
On) Down=lower layer is Down (low layer is down) Tld=This-Layer-Down (this layer
For following) (Tls=This-Layer-is beaten in management to Open=administrative Open
Opening) (Tlf=This-Layer-is closed in management to Close=administrative Close to Started (this layer beginning)
Close) Finished (this layer finishes) TO+=Timeout with counter＞0 (meter Irc=Initialize-Restart-
Number device＞0 is then promptly) Count (initialization-restart-
Counting) TO-=Timeout with counter Zrc=Zero-Restart-
Expired (counter then completely promptly) Count (zero-restart-count) RCR+=Receive-Configure-Request Scr=Send-Configure-
(Good) (reception-configuration-request (good)) Request (transmission-configuration-ask
Ask) RCR-=Receive-Configure-Request
(Bad) (reception-configuration-request (bad)) RCA=Receive-Configure-Ack (reception-Sca=Send-Configure-
Configuration-affirmation) Ack (transmission-configuration-affirmation) RCN=Receive-Configure-Nak/Rej (meets Scn=Send-Configure-
Receipts-configuration-nothing affirmation/refusal) Nak/Rej (transmission-configuration-nothing
Affirmation/refusal) RTR=Receive-Terminate-Request (meets Str=Send-Terminate-
Receive the request of termination) and Request (transmission-termination-please
Ask) RTA=Receive-Terminate-Ack (reception-Sta=Send-Terminate-
Termination-affirmation) (receiving not, Scj=Send-Code-Reject (sends out Ack (transmission-termination-affirmation) RUC=Receive-Unknown-Code
Know sign indicating number) send sign indicating number to refuse) RXJ+=Receive-Code-Reject
(permitted)
or????Receive-Protocol-
Reject (receiving code refusal (permission) or reception
The agreement refusal) RXJ-=Receive-Code-Reject
(catastrophic)
or????Receive-Protocol-
Reject (receiving code refusal (fault) or reception
The agreement refusal) RXR=Receive-Echo-Request ser=Send-Echo-Reply (sends
Or Receive-Echo-Reply backhaul is replied)
or????Receive-Discard-
Request (receives the backhaul request or receives back
The request of abandoning is replied or received to journey)
In order to carry out exemplary illustration, Fig. 1 is the structure chart of ply-yarn drill in the conventional P PP over SDH router.As shown in Figure 1, part as router one, have a plurality of ply-yarn drill 2-1 ..., 2-N, each piece all links to each other with switching backplane unit (switch fabric unit) 3, for each piece ply-yarn drill, receive by OC-192c/48c/12c/3c or STM-64c/16c/4c/1 transceiver 6 from the class HDLC Frame of O/E (light /) modular converter 5, send to POS (PPP over SDH/SONET) mapper/go mapper 7 (also being framer/deframer) then; In POS framer/deframer 7, the PPP frame that is encapsulated in the HDLC frame is extracted out, be sent to then in the Packet Forwarding Engine 8, forwarding engine 8 and routing engine 4 synthetic operations, being used for PPP handles, routing engine 4 is the software of the embedded type CPU operation in the router, subclass and ply-yarn drill identifier or the ply-yarn drill port adjacency list combined mechanism of forwarding engine 8 by using one the IP address and the corresponding network parameter of routing table (Routing Table) or forwarding information base (FIB:Forwarding Information Base) are formed, packet is forwarded on the switching backplane 3, so that packet is sent to destination address.As the ppp feature of network layer handles is to realize in the forwarding engine on every ply-yarn drill and the routing engine in router.
Fig. 2 has illustrated and has realized the example that network layer PPP handles on traditional ply-yarn drill.For example, the data rate of supposing this moment is 2.5Gbit/s, among Fig. 2, the filtering function of PPP (LCP, NCP) can be by 50, the such filtering function of hardware positioning before forwarding engine of field programmable gate array more than 000 (FPGA) realizes that other LCP function then can utilize the form of the software resemble the routing engine to realize; Another kind of scheme is, all PPP, LCP, NCP function can both utilize the hardware resemble the forwarding engine to realize, but the door number of its FPGA will be above 500,000.In addition, the C language source code of PPP software surpasses 10,000 row, is worth tens thousand of dollars.
For the mapper on the ply-yarn drill/go the complexity of mapper chip and network processing engine chip, the how tame by inquiry manufacturer of inventor mapper/go the mapper chip solution, found following situation:
When being configured to the POS pattern, mapper/go the transmission HDLC processor of mapper that the HDLC frame signal is inserted among the SPE is carried out packet framing, interframe filling and is sent fifo error and recovers.In addition, no matter be preposition or rearmounted HDLC processor, all can select to carry out scrambler (x 43+ 1) function is carried out the transparency processing procedure that RFC1662 stipulates, also optionally produces the FCS (Frame Check Sequence) of 16/32 bit.
Receive the HDLC processor following function is provided: extract the HDLC frame, remove the transparency (EscapeCode), (if necessary) descrambling code is checked fcs error, randomly deletes HDLC address field and control field.LCP and NCP function are not included in mapper/go in the mapper chip.
POS PHY (physics) interface: the OC-3/STM-1 that defines following situation is 8 parallel-by-bits, the speed of every 25Mbps; OC-12/STM-4 is 16 parallel-by-bits, and every bit rate is 50Mbps; Be 32 or 64 parallel-by-bits during OC-48/STM-16, every bit rate is 100Mbps or 50Mbps.
The formation of processing, link establishment, checking, procotol and the link termination and the state transition table of different LCP bags among the PPP can perhaps be transferred to overall routing engine place by network processing unit and realize at the network processing engine place.Many manufacturers, all developing the diverse network processor engine as Agere, Broadcom, Conexant, C-port, IBM, Intel, Lucent, Maker, MMC network, Motorola, Sitera, softcom, TI and Vitesse (Europe, Japan and the Chinese company that also have other), the support package pattern is arranged, support cell (cell) pattern is arranged, also have two kinds of patterns all to support.For example existing company issues its network processing unit or enters commercialization, and it is the BGA of 800 multi-feets) encapsulation, need a series of software developments and testing tool in addition, could make up ply-yarn drill.This engine has the function of multi-protocols processor, there are many necessary function relevant with IP-based forwarding, as inlet flow scheduling, receive that stream is resolved, routing table inquiry and upgrade, receive editor, input rank management, output queue management, transmission editor, output signal scheduling, and the interface of SSRAM, SDRAM, and the SNMP network management or the like, cause engine very complicated.Usually use up till now based on microcode or based on the programming of low layer specification language.Next target is to set up a pure ASIC (application-specific integrated circuit (ASIC)) to realize that IP transmits.Because IP-based surface speed forwarding is still basic requirement, in two kinds of situations, the use of LCP and NCP agreement shows that this kind engine has increased extra burden in the above.But in traditional design, can not accomplish to reduce cost the major requirement of raising the efficiency.
From as seen above, traditional PPP over SDH/SONET solution be quite complicated, implement very difficult and expensive, speed is slow, not exclusively is fit to the high speed transmission, be not suitable for gigabit speed especially and use.
PCT International Application PCT/CN00/00195 (international publication number WO 01/06728A1 that the applicant submitted on July 13rd, 2000, open day: disclose a kind of data transmission device that between physical layer and network layer, transmits data 2001.1.25), the LAPS scheme that adopts the inventor to propose, on the address field of the frame of SDH/SONET, insert the SAPI identifier, represent packaged data type, solved to a certain extent IP is connected to the problems referred to above among the SDH/SONET.But,, need a kind of solution that has more flexibility because the data on the Internet all are based on 32.
One object of the present invention is to provide the data transmission device between a kind of physical layer and the network layer.It is simple, efficient, reliable, low-cost, has flexibility, is suitable for high speed data transfer application, as the router of gigabit or the above speed of gigabit, at the router at edge network node place etc.
A further object of the present invention is to provide the data transmission device between a kind of physical layer and the network layer, it be adapted to better from Internet based on 32 IPV4, IPV6 data.
Sending direction the invention provides a kind of data transmission device, is used for packet is sent to physical layer side equipment from the network layer side apparatus, comprising: first receiving device receives the packet of certain type from the network layer side apparatus; SAPI identifier generation device, the type of recognition data bag, and, produce the SAPI identifier according to the type of discerning; The first framing device, be used for following column format and encapsulate described data: beginning flag, address field, control field, contain the SAPI identifier SAPI field (2 eight hytes), contain information field, FCS field and the end mark of described packet, to form the frame of the first kind; The second framing device is used for first kind frame is encapsulated into payload part, and inserts suitable expense, to form the frame of second class; And first dispensing device sends to the second class frame in the physical layer side equipment.
Receive direction the invention provides a kind of data transmission device, is used for packet is sent to the network layer side apparatus from physical layer side equipment, and described packet is for to add suitable expense with first kind frame as payload, is encapsulated in the second class frame to form.Each first kind frame comprises: beginning flag, address field, control field, contain SAPI field (2 eight hytes), information field, FCS field and the end mark of SAPI identifier.Described device comprises: second receiving system is used for from physical layer side equipment receiving data bag; Second separates the frame device, is used for removing expense from the payload of the second class frame, and extracts first kind frame; First separates the frame device, extracts address field, control field from first kind frame, contains the SAPI field of SAPI identifier, the data in the information field; Judgment device, the value of SAPI field and the one group of preset value that comprises first value and second value are at least compared, if the value of SAPI field data and first value are complementary, just judge that the data of being extracted are first kind, if the value of SAPI field and the second class value are complementary, just judge that the data of being extracted are second classes; Second dispensing device is used for sending the packet extracted and the result of judgement to the network layer side apparatus.
The present invention also provide a kind of between network layer side apparatus and physical layer side equipment the data transmission device of transmits data packets, the data transmission device that it comprises above-mentioned transmission and receives both direction.
The present invention also provides a kind of router device, and it comprises a plurality of ply-yarn drills, has at least a ply-yarn drill to comprise the data transmission device of above-mentioned transmission and reception both direction.
The present invention also provide a kind of between network layer side apparatus and physical layer side equipment the data transmission method of transmits data packets, may further comprise the steps: receive certain type data packets from the network layer side apparatus; Recognition data bag type, and according to the type generation SAPI identifier of discerning; The first framing step encapsulates described data with following form: beginning flag, address field, control field, the SAPI field that contains the SAPI identifier, the information field that contains described packet, FCS field and end mark; The second framing step adds suitable expense with first kind frame, is encapsulated into payload part, forms the second class frame; And, the second class frame is sent to physical layer side equipment.
The present invention also provides a kind of data transmission method that packet is sent to network layer device from physical layer equipment, described packet is to form by first kind frame is added as payload that suitable expense is encapsulated in the second class frame, first kind frame comprises origin identification, address field, control field, contains the SAPI field of SAPI identifier, information field, FCS field and finish sign, said method comprising the steps of: receive the packet from physical layer side equipment; Second separates the frame step: remove expense, extract first kind frame from the payload of the second class frame; First separates the frame step: extract SAPI field and the data that are included in the information field from first kind frame; The value of SAPI field and the one group of preset value that comprises first value and second value are at least compared, if the value of SAPI field and first value are complementary, with regard to judging that the data of extracting are first kind,, just judge that the data of extracting are second classes if the value of SAPI field and the second class value are complementary; And, send the packet of extraction and the result of judgement to the network layer side apparatus.
Data link among the present invention and method can be applied to core and edge router, switching equipment, IP-based network access device, ply-yarn drill and interface unit or the like.
Below in conjunction with accompanying drawing the present invention is carried out the example explanation, but be not limited only to the figure in the accompanying drawing, same numeral is represented like among the figure.
Fig. 1 shows the ply-yarn drill structure in the conventional P PP over SDH router;
Fig. 2 shows a kind of execution mode that PPP handles in the network layer in traditional ply-yarn drill;
Fig. 3 A is an example according to the structure of network protocol stack of the present invention;
Fig. 3 B shows the IP over STM-N/ protocol stack structure according to employing LAPS of the present invention;
Fig. 3 C shows the IP over sSTM/ protocol stack structure according to employing LAPS of the present invention;
Fig. 4 illustrates the LAPS frame format among the present invention;
Fig. 5 A, 5B illustrate the relation between network layer, link layer and the physical layer, and relevant primitive relation;
Fig. 6 illustrates the framework of the IP over SDH router of use LAPS according to an embodiment of the invention;
Fig. 7 illustrates an embodiment according to IOSL framer of the present invention/deframer structure;
Fig. 8 A shows the topology example of the SPE/VC of STM-N;
Fig. 8 B illustrate use among SDH and the SONET path overhead (POH) structure;
Fig. 8 C illustrates the position of POH among the SPE/VC;
Fig. 9 illustrates the structure according to scrambler and descrambler in IOSL framer/deframer of the present invention;
Figure 10 is the comparison between RFC 2615 frame structures and the frame structure of the present invention;
Figure 11 is according to the present invention, uses the network interconnection example of IP over SDH structure;
The present invention has removed PPP processing procedure such as filtering function from the network layer handles device, and (SAPI) holds multiple logical links with the service access point identifier, encapsulates polytype data, as based on IPv4, based on the packet of IPv6 and other procotol.
The IP over SDH that adopts LAPS is the data communication architecture that Internet agreement and SDH network are combined.Fig. 3 A is according to network protocol stack topology example of the present invention, and when connecting Local Area Network to IP over SDH network, it has shown the protocol stack structure of input side and outlet side node.As shown in Figure 3A, IP over SDH is representing the interconnection of IP and SDH.Can provide SDH and MAC two kinds of physical interfaces at the gateway place, and network layer is IPv4/IPv6.
In IP over STM-N layer/protocol stack of Fig. 3 B and in layer/protocol stack of the IP over sSTM-n of Fig. 3 C, physical layer, link layer and network layer separate provision are SDH/SONET, LAPS and IPv4/IPv6/PPP/ intermediate system-intermediate system (IS-IS).
Fig. 3 B is according to the present invention, illustrates the IP over STM-N layer/protocol stack structure that adopts LAPS.Shown in Fig. 3 B, have two kinds of methods to put into virtual container: a kind of is that the LAPS frame is put into Lower Order Virtual Container, then according to the SDH multiplexing structure, utilize byte-interleaving to interleave the low order vc multiplexing in high-order VC, send multiplex section, regenerator section and O/E converting unit at last successively to, can extract the LAPS frame signal according to the anti-process of said process at receiver side; Another kind of mode is put into SPE with the LAPS frame exactly, maps directly in the high-order container, sends to multiplex section, regenerator section and O/E converting unit then successively, and receiver side just can extract the LAPS frame according to anti-process.
Fig. 3 C is according to the present invention, illustrates the IP over sSTM-n layer/protocol stack structure that adopts LAPS.Shown in Fig. 3 C, the LAPS frame signal can only be put into low order VCx (VC11, VC12, VC2), then according to the subclass multiplexing structure of SDH, utilize byte to interleave the low order vc multiplexing in the subclass multiplex section, send to multiplex section, regenerator section and O/E converting unit successively, receiver side can extract the LAPS frame by anti-process.
Fig. 4 illustrates the frame structure of LAPS according to the present invention.As shown in Figure 4, the frame structure of LAPS is made up of origin identification sequence, address field, control field (0x03), SAPI service access point identifier, information field (IPv4, IPv6 or ppp protocol data cell), FCS (Frame Check Sequence) and end identifier, and identifier (0x7E) has indicated the beginning/end of LAPS frame.
Fig. 5 A, 5B for example understand the primitive relation between LAPS, IP and the SDH.Communication between each layer is finished by primitive.Primitive, abstract says, is the logic exchange of information and control between expression data link layer and the 3rd layer or other upper-layer protocol.The method that they are not stipulated or restriction realizes.Shown in Fig. 5 B, DL-UNACK-DATA (request and indication) primitive is used for asking and indicating by the data link layer entity transmission of using UITS (not confirming the formula information transfer service) or three layers of IP bag (user data) or other upper-layer user's data of reception.PH-DATA primitive be used for asking and be designated as the data link layer peer-to-peer communications send by physical layer and/or will be sent to the data link frame that physical layer is gone.
MDL-ERROR primitive is to be used for taking place as the mistake as a result of communicating by letter with the data link layer peer-entities to the indication of connection management entity.When receiving the MDL-ERROR indication, the connection management entity will produce action.Parameter and primitive interrelate, and comprise and professional relevant information.In the situation of DATA primitive, supplemental characteristic comprises service data unit.Service data unit allows the service user that protocol Data Unit is sent to reciprocity service user's entity.For example, the DL-UNACK-DATA parameter comprises the 3rd layer of information.The PH_DATA parameter comprises the frame of data link layer.As user data and 6 DS (segmentation the is professional) code-point (codepoint) that uses for different services.
Primitive process has been determined the interaction between adjacent layer so that call and provide service.Service primitive has been represented the key element of process.Shown in Fig. 5 B.
The framework of the ply-yarn drill structure of IP over SDH (the being called for short IOSL later on) router of Fig. 6 use according to an embodiment of the invention LAPS.As shown in Figure 6, router comprise 2-1 ' ..., a plurality of ply-yarn drills such as 2-N ', each ply-yarn drill and a network node interfaces of determining; Switching backplane 3 carries out packet exchange between ply-yarn drill; Route is handled and network management unit 4 carries out the route processing and necessary network management is handled, as OSPFv2, BGPv4, RIPv1/v2, RSVP-TE, CR-LDP, system SNMP etc.Every ply-yarn drill comprise with the O/E module 5 of physical layer equipment interface, from/to the OC transceiver of O/E module reception/transmission data, carry out the FPGA of IOSL framer/deframer 11 that LAPS framing/separate frame handles, standard/rate adapted or the software code the network processing unit 12, according to the IP address of its reception, to its destination node transmit network processing engine 8, the standard/rate adapted of IP bag FPGA 13, from/to the serial Backplane Transceiver 9 of switching backplane unit 3 reception/transmission data.
Among Fig. 6, O/E is the light/electric module 5 with OC3/12/48/192 speed, and OC3/12/48/192 transceiver 6 clock generator that has been integrated with the chip of SONET/SDH compatibility, can be used in the SONET/SDH system with the work of 2.488Gb/s data rate.For the 2.488GHz clock that provides internal logic and output to retime, internal clock generator employing PHASE-LOCKED LOOP PLL TECHNIQUE is carried out frequency multiplication with the reference clock of 77.76MHz or 155.52MHz.8/16/32/64 parallel-by-bit interface adopts this machine (onboard) FIFO (first-in first-out), by parallel flexibly regularly framework is provided, has eliminated the consideration of loop timing design aspect.In addition, this equipment also provides the facilities and equipment loopback mode both and two loop timing patterns.
Among Fig. 6, IOSL (adopting the IP over SDH/SONET of LAPS) framer/deframer is carried out following function:
● will be by IPv4, the IPv6 of SAPI identification, PPP, IS-IS with based on Ethernet
Data envelope is put into the LAPS information field.
● parameter among the LAPS " 6 DS code-points " (RFC 2460 definition) can be used for finishing
Between IPv4/IPv6 and the LAPS, or the chain circuit function between IPv4/IPv6 and the PPP, with
Provide segmenting professional support; It is not applied to any framing of LAPS.The DS code-point
Be from the IP packet, to extract, with it as control information, in order to control formation algorithm.
● with transmission/section overhead interface of E1, E2, F1 and D1-D12, sending and connecing
Receive the Yuan Hesu of both direction treatment S ONET/SDH section, circuit and channel layer.
● by LAPS frame full duplex is shone upon into SONET/SDH payload, realize STS-
192/STM-64 or STS-48c/STM-16 or STS-12c/STM-4 or STS-3c/STM-1
The Data Stream Processing process.
● utilize multinomial (X 43+ 1) the LAPS signal is carried out motor synchronizing scrambler/descrambling.
● POS phy interface or Utopia (Utopia, a kind of interface standard name) are provided interface.
● be provided for controlling, 8 or 16 microprocessor of configuration and Stateful Inspection
Interface.
● meet ITU-T suggestion LAPS processing procedure X.85.
● meet ANSI T1.105, Bellcore GR-253-CORE and ITU G.707 (2000
Year April version) the SONET/SDH standard.
● IEEE is provided 1149.1 jtag test ports.
● support inner diagnostic loopback passage.
In above-mentioned IOSL framer/deframer, sending direction comprises following basic function: the LAPS frame is inserted in SPE (synchronous payload is sealed) frame; Interframe is filled and is transmitted the FIFO mistake and recovers; Scrambler (X 43+ 1); The transparency is handled; Produce 32 FCS.
Receive direction comprises following basic function: extract the LAPS frame; Remove the transparency (Escape Code); Descrambling (as being provided with); Fcs error is checked; Remove LAPS address field, control field and SAPI field.
According to one embodiment of present invention, the concrete structure of IOSL framer/deframer is shown in Figure 7 among Fig. 6, is transmitting and receiving the STS-3c/STM-1 processing procedure that both direction framer/deframer is finished standard.
Sending direction, LAPS frame are encapsulated among the SPE/VC of SONET/SDH, insert POH (path overhead) and TOH/SOH (transport overhead/section overhead), and the STS signal that obtains sends to parallel/serial convertor with the form of byte wide, arrives fiber optical transceiver again.As shown in Figure 7: IOSL framer/deframer comprises: at sending direction, TX FIFO (send FIFO) 18 receives packet and buffer memory from the network layer side apparatus, and the IP packet can be IPv4, IPv6, PPP, IS-IS or other; SAPI decision unit 19 is judged the type of data packet that receives, and produces a corresponding predetermined SAPI value; TX LAPS processing unit 22, be used for the form according to Fig. 4, promptly according to following form: origin identification, address field, control field (0x03), SAPI service access point identifier, information field (IPv4, IPv6 or ppp protocol data cell), FCS (Frame Check Sequence) and end sign install to SAPI and data envelope in the LAPS frame; The scrambler unit 23 that is used for the LAPS frame; SPE/VC pointer adjustment unit is adjusted the pointer of indicating the SPE/VC4 position; The SDH expense is inserted unit 33 and is inserted suitable expense; TX SDH/SONET framer 25 is packed the LAPS frame of descrambling among the SPE/VC4 of SDH/SONET frame into, forms the SDH/SONET frame; Line interface 26 sends the SDH/SONET frame by TX (transmission) circuit to physical layer equipment, as the O/E module of Fig. 6.
As shown in Figure 7, according to embodiments of the invention, TX LAPS processing unit can comprise a frame type indicators generation device 41, be used to produce the designator of type of the frame of the described first kind of expression, and described frame type indicators is inserted address field during the LAPS framing is handled.Described frame type indicators is set to " 0x04 " for the LAPS frame, and the PPP frame is set to " 0xff ", and other value is preserved for the frame of other type, or is used for frame format in the future.Particularly, for the IPV4 packet, the frame type indicators in the address field is " 0x04 " (one eight hyte), and control field is " 0x03 " (default value), and the SAPI identifier in the SAPI field is " 0x0021 " (two eight hyte); For the IPV6 packet, this SAPI field becomes " 0x0057 "; And for PPP bag or PPP/HDLC solution, frame type indicators is " 0xff " (one eight hyte), and control field is " 0x03 " (default value), and the SAPI identifier in the SAPI field is " 0x0021 " (two eight hyte).
Above-mentioned frame type indicators generation device 41 can provide separately, also can determine that device 19 is merged together the formation one with SAPI.
At receive direction, processing procedure conversely.When the STS signal that receives byte wide, IOSL framer/deframer 11 locating frames and TOH/SOH resolve pointer, stop TOH/SOH and POH, extract SPE/VC4, extract the LAPS frame then from the SPE/VC4 payload.The SONET/SDH processor is formed by receiving the SONET/SDH processor and sending the SONET/SDH processor.As shown in Figure 7, IOSL framer/deframer comprises: line interface 26 receives SDH/SONET frame (HDLC-like framing) from physical layer equipment; RX SDH/SONET deframer 27 is separated frame to SDH/SONET; SDH overhead extraction unit 34 is used to remove expense; Pointer resolution unit 28 is used for the location and resolves pointer, extracts SPE/VC4, and extract the LAPS frame from SPE/VC4; Descrambling unit 29 is to the LAPS frame descrambling that extracts; RXLAPS processing unit 30 is separated frame to the LAPS frame, extracts the SAPI and the packet of encapsulation from the LAPS frame; RX FIFO 20 is used for data cached bag and to the transmission of network layer side apparatus, for example the network engine among Fig. 68 sends packet and SAPI value as the IP bag.IOSL framer/deframer 11 also is included in receiver side and judges whether to need the connection management unit 36 retransmitted.
According to embodiments of the invention, as shown in Figure 7, RX LAPS processing unit also comprises a frame type recognition device 42, is used for extracting frame type indicators from address field, is encapsulated in frame type in the SDH/SONET frame with identification.If frame type indicators is " 0x04 ", then the frame of Jie Shouing is confirmed as the LAPS frame; If frame type indicators is " oxff ", then the frame of Jie Shouing is the PPP frame.
In addition, according to embodiments of the invention, RX LAPS processing unit also comprises SAPI extraction element 43, is used for extracting the SAPI value from the SAPI field of control field back.If frame type recognition device 42 determines that the frame type indicators in the address field is " 0x04 ", the frame that its expression is received is the LAPS frame, then SAPI extraction element 43 turns to two eight hytes of SAPI field, extract the SAPI value, the type of this SAPI value representation packet promptly, is " 0x0021 " for the IPV4 packet, for IPV6 packet or other packet, be " 0x0057 ".If frame type recognition device 42 determines that the frame type indicators in the address fields be " 0xff ", and SAPI is " 0021 ", and then the frame of Jie Shouing is confirmed as the PPP frame, and can send and do further PPP processing.
Above-mentioned frame type recognition device 42 and SAPI extraction element 43 can merge into a single whole, to carry out definite function: address field (one eight hyte) to preceding 4 eight hytes of each frame, control field (one eight hyte) and SAPI field (two eight hytes) are so that 32 processing.Obviously, preceding four eight hytes are " 04 03 00 21 " expression IPV4 bag, " 04 03 00 57 " expression IPV6 bag, the PPP bag of " ff 03 00 21 " expression encapsulation IPV4 packet.
IOSL framer/deframer also comprises POH monitor, the SDH expense monitor that monitors SOH, the microprocessor I/F (interface) 36 that is connected to Controlled CPU, the jtag port of testing usefulness that monitors POH, GPIO (general input and output) register that work register is provided; These all will illustrate successively at counterpart subsequently.
The data procedures that framer/deframer received and sent class HDLC will describe in detail subsequently.In the declarative procedure afterwards, correlation function and operation, functional block or unit can adopt executable program and/or hardware designs to realize, its details will not be given unnecessary details, to avoid unnecessarily having blured main aspect of the present invention.
The frame structure of class HDLC
Fig. 8 A illustrates the example of HDLC frame structure.Shown in Fig. 8 A, it comprises that payload (SPE/VC), RSOH (RSOH), administrative unit (AU) pointer and the MSOH of 261 bytes * 9 row are used as the SDH/SONET expense.The AU pointer part comprises H1, the H2 byte of indication payload original position, and RSOH partly comprises A1, the A2 byte that is used for determining frame position.
What Fig. 8 B showed is the structure of path overhead, what Fig. 8 C showed is the position of POH in the payload (SPE/VC), shown in Fig. 8 B and Fig. 8 C, POH comprises J1, B3, C2, G1, F2, H4, Z3, Z4 and the Z5 that is used for SONET respectively, J1, the B3, C2, G1, F2, H4, F3, K3 and the N1 that are used for SDH, and the POH of 9 bytes is placed on first row of payload.Can adopt the Adjacent Concatenation of VC (virtual container) and Virtual Concatenation mode to constitute physical channel based on payload.
Receiving SONET/SDH handles
RX deframer 27 is embodied as reception SONET/SDH processor.Receive that the TOH/SOH monitoring, the AIS that separate frame, descrambling, contain B1 and B2 monitoring that the SONET/SDH processor is used to realize the STS signal detects, pointer is handled, POH monitoring etc.Receive the SONET/SDH processor and realize following function:
● according to SAPI, identification and extraction LAPS field;
● SONET/SDH separates frame, and detect [A1A1A2A2] byte sequence and be used to separate frame,
OOF and LOF indication (single incident and second incident) is provided;
● adopt SONET/SDH frame synchronization descrambler 29, with multinomial (X 7+ X 6+ 1), right
The payload descrambling;
● realize that by expense monitoring block 32 expense monitors;
● pointer state detects or resolution unit 28 is checked the H1-H2 byte, sets up to receive to refer to
The state of pin (normal, LOP, AIS).If pointer state is normal words, read first
The H1H2 byte is determined the state of SPE/VC;
● POH monitoring block 31 is made up of J1, B3, C2 and G1 monitoring.Monitor these POH
Byte is with Discovery Status mistake or change;
● for whether the error rate of judging reception is higher or lower than two different thresholds that are provided with
Value, IOSL provides two kinds of B2 error rate threshold pieces, when surpassing threshold value, by interrupting newspaper
Accuse signal error (SF) and Signal Degrade (SD) situation.
Sending SONET/SDH handles
TX framer 25 is embodied as transmission SONET/SDH processor.Send the SONET/SDH processor and be used to realize of the encapsulation of LAPS frame, insert suitable substance P OH and TOH/SOH then, subsequently last STS signal is outputed on the parallel/serial transducer, arrive fiber optical transceiver again to SPE/VC.
● synchronous payload district/virtual container (SPE/VC) pointer is adjusted piece 24 and is adjusted pointer, will
Path overhead (POH) from the LAPS frame of system interface and its generation is multiplexing, generates SONET
SPE, or the VC of SDH;
● utilize expense insert module 33 to insert expense: the POH byte;
● adopt SONET/SDH frame synchronous scrambler 29 and multinomial (X 7+ X 6+ 1), to only
The lotus scrambler; Describe the LAPS processing procedure below in detail.The LAPS processing procedure
According to concrete condition of the present invention, IOSL framer/deframer 11 extracts frame signal/bag signal from SONET payload area (SPE), and frame signal/bag signal extracts via the LAPS processor.IOSL also supports direct mode operation simultaneously, allows SPE directly to pass through, and arrives system interface.The LAPS processor carries out LLC (logic control link) and other class LAPS framing based on the data-signal of bag.According to the present invention, the LAPS processor is the single channel engine, is used for data envelope is installed to the LAPS frame.The LAPS processor is for SONET/SDH, only to the datamation (is the integral multiple of byte as message-length) with byte align.According to one embodiment of present invention, as shown in Figure 7, the LAPS processor can be separated into and receive the LAPS processor and send the LAPS processor.
Encapsulation
By " the POS PHY/UTOPIA " of reconciliation sublayer or equivalence, LAPS link entity is from network layer or other upper strata received frame.Adaptive and primitive between IP, LAPS and the SDH closes and ties up to shown in Fig. 3 B, 3C and 5A, the 5B, and Fig. 4 has showed through the LAPS form after a kind of type information field of encapsulation.IP overSDH functional unit will all be imported the connection link that the LAPS information field is transmitted to its equity, former sending except the link port, and before transmitting, also allow the one or more incoming frames of buffer memory.
Receive the LAPS processor
The LAPS of RX LAPS processor 27 receives (Rx) processing procedure and mainly comprises following function.
SPE (synchronous payload zone) the eight hytes stream supposition of-reception comprises one or more companies
Continuous LAPS frame stream.
Consisting of of-LAPS frame structure: beginning flag sequence, address field, control field,
SAPI (service access point identifier), information field (IPv4, IPv6 or ppp protocol data
The unit), FCS (Frame Check Sequence) and end mark sequence.
-extract IPv4, IPv6, IS-IS or ppp protocol data cell, store Rx into
In FIFO (reception first in first out) module 20.
Receive the descrambling that LAPS processor 27 extracts LAPS frame signal, transparency removal, fcs error verification, SPE/VC payload, optional deletion control field, address field and SAPI, and carry out performance monitoring.
Remove field initial/finish after sign and the byte of padding, remaining payload comprises data field and FCS field, sees below the literary composition detailed description.Note in fact only needing a flag byte between two bag signals.Whole signs between the bag signal all abandon.
Particularly, receive the LAPS processor and will realize series function especially:
● the payload that receives is randomly carried out motor synchronizing descrambling (X 43+ 1 multinomial);
● detect and stop the LAPS frame, delimit sign as detecting frame;
● remove control escape (Control Escape) and fill;
● calculate optional FCS sign indicating number (32), itself and the FCS value that receives are compared.
In the performance monitoring register, accumulate mistake,, will export number if after detecting fcs error
Make mistakes according to being labeled as;
● the terminator sequence in the detected words throttling (0x7D, 0x7E);
● randomly delete address field, control field and SAPI field;
● provide optional packet the minimum and maximum length (SW is configurable) that detects, with data
Indicate that RX_ERR is to show error situation;
● produce the performance monitoring of eight hytes: the bag of fcs error, termination (abort), short bag,
Long bag, the bag that abandons because of the RX_FIFO mistake;
● randomly deletion is used to handle the bag filling under the far-end FIFO underflow situation;
● error situation is produced interruption;
● the parlor slit in the automatic deleted marker.
Describe the realization of the function of RX LAPS processor 27 below in detail.
LAPS frame synchronization
Initial/the termination of flag sequence (0X7E) sign LAPS frame.The SPE payload data of eight hytes search reception is sought flag sequence one by one, to determine the border of LAPS frame.Being used for eight octet value of distinguishing mark sequence can programmed configurations, and default value is 0x7E.
Two continuous flag sequences are formed an empty frame, can ignore simply.Therefore N continuous mark sequence can think N-1 empty frame.Too short frame, invalid frame can quietly abandon.Following situation appears in the LAPS frame, can think invalid frame.
A) do not have correct to be masked as the boundary with two; Or
B) eight bit byte between flag of frame is less than six; Or
C) contain wrong Frame Check Sequence; Or
D) the service access point identifier that comprises is not " 4 " (based on service of IPv4), " 6 "
(based on the service of IPv6), " 255 " (based on service of PPP) or be not received device and prop up
Hold;
E) comprise the control field and the SAPI value that can not be identified.
f)
The LAPS byte goes to fill processing procedure (transparent processing procedure)
It is on the LAPS frame that is applied to receive that the LAPS byte is removed filling process (also referring to escape conversion (escape transform) sometimes), and it is before FCS calculates, and carries out after the LAPS frame synchronization.By checking the whole LAPS frames between the starting and ending flag sequence, search control escape eight hytes, carry out byte and go to fill.After finding control escape eight hytes, from eight hytes stream, remove control escape eight hytes, and utilize one eight hyte to go to fill shielding eight hytes XOR is carried out with eight hytes in the back.Abort sequence should not be thought of as escape sequence.
Control escape byte value can pass through programmed configurations, and default value is 0x7D.Eight hytes go to fill shielding eight hytes can pass through programmed configurations, and default value is 0x20, and for example, 0x7E can be encoded to 0x7D, 0x5E, and 0x7D can be encoded to 0x7D, 0x5D.
Peeling off of SAPI protocol encapsulation field
The position of SAPI field before the LAPS information field.The SAPI field is that 2 eight hytes are long.Hexadecimal value " 0021 ", " 0057 " are represented respectively based on IPv4, based on the packet of IPv6.The regulation of other value can be referring to RFC 1700.Before frame was stored in Rx FIFO20, SAPI will be peeled off.
The LAPS terminator sequence
Terminator sequence (control escape after with flag sequence) can randomly detect in input LAPS frame signal.End that stops the LAPS frame of terminator sequence mark.
FCS calculates
The FCS field that receives needs verification, finish after eight hyte bytes go to fill, to LAPS initial/all eight hytes of finishing to delimit flag sequence (comprising the FCS field) calculate, and draw the FCS checksum value.Can adopt two kinds of different FCS types to finish verification.
First kind is to use generator polynomial 1+X 5+ X 12+ X 1616 CRC-CCITT that produce.16 FCS " good final FCS " value is that 0xF0B8 (notes: when the address word segment value of LAPS is arranged to " 11111111 ", during with RFC 2615 compatibilities, the calculating of 16 FCS can be with reference to RFC 2615, and in this case, the length of FCS becomes 2 eight hytes).Second kind is with generator polynomial (referring to X.85) 1+X+X 2+ X 4+ X 5+ X 7+ X 8+ X 10+ X 11+ X 12+ X 16+ X 22+ X 23+ X 26+ X 3232 CRC-32 functions that produce, " good final FCS " value is 0xDEBB20E3.
Minimum effectively FCS byte is to follow closely after last LAPS information field in the FCS field, at first the FCS byte of Dao Daing.At first the least significant bit (arriving at last) of each eight hyte is sent into the calculator of CRC.When the FCS checksum value that calculates and " good final FCS value " when not matching, think that then the FCS of LAPS frame makes mistakes, under the default situation, adopt 32 CRC to realize the FCS verification.
With self-synchronous scrambler (SSS) 1+X 43Descrambling
Fig. 9 B is the structure according to descrambler 29 among Fig. 7 of one embodiment of the invention.Shown in Fig. 9 B, descrambler comprises an XOR gate and one 43 s' shift register, and carry-out bit carries out XOR with input scrambled data position and calculates, and produces the position of not scrambling.
The data that receive are utilized motor synchronizing descrambler X 43+ 1 carries out descrambling, and the data bit of arrival is carried out descrambling according to input order.Descrambling can adopt three kinds of modes to move: complete solution is disturbed, part descrambling and descrambling not.The selection of three kinds of modes is determined by initial configuration.It is before finishing arbitrary LAPS framing function that complete solution is disturbed, and just uses SSS, and whole (all) contents of SPE payload all will be carried out descrambling.The part descrambling is meant except flag sequence and all LAPS eight hytes of stopping escape eight hytes uses SSS, after eight hytes go to fill and carrying out before the processing of Link Access Procedure-SDH protocol field the applying portion descrambling.Two kinds of descrambling processes can be set to " opening/break " independently.No descrambling is to forbid the descrambling function.Can not add the scrambler function, this is for extremely important with old device intercommunicating.Default situation is only complete solution to be disturbed handle to be set at out (enabling).
Long bag processing procedure
If the bag eight hyte numbers that write Rx FIFO during greater than long (MPS) value of maximum bag able to programme, are then thought bag " oversize ".
For long bag, write above the bag of MPS and may forbid to Rx FIFO.No matter this function enables or forbids, writing the long bag of Rx FIFO the last character is that EOP is (for SDH/SONET series speed STM-1/4/16/64, or OC-3/12/48/192, the interface configuration/bandwidth that is input to network processing unit is 8bit * 25MHz, 16bit * 50MHz, 32bit * 100MHz, 64bit * 50MHz, 64bit * 200MHz, 128bit * 100MHz).In addition, function is irrelevant therewith in the operation of Rx fifo error mark and discard.Notice that this option only could use when Rx fifo error mark and discard all enable.The default MPS of IPv4 is 1,600 eight hytes, and the MPS of IPv6 is for changing with programmed configurations.Under the default situation, have only the MPS of long bag to write Rx FIFO.
Short bag is handled
If the packet byte number that writes Rx FIFO during less than long (mPS) value of parcel able to programme, is then thought bag " too short ".
The default value of mPS is 40 bytes, can be configured between 8 to 65535 scopes.
The storage in Rx FIFO of SAPI and information field
For each LAPS frame, extract SAPI and information field, and deposit among the Rx FIFO, for STM-16c/OC-48c, align with 64 or 32 bit boundarys; For STM-4c/OC-12c, align with 16 bit boundarys; For STM-1/OC-3c, align with 8 bit boundarys.SAPI deposits Rx FIFO in and can be enabled/forbid.Default situation, SAPI field are to deposit Rx FIFO in.For example Rx FIFO when OC-48c/STM-16c be 512 words (32 * 100MHz), can hold down storage 2048 information field eight hytes altogether.Suppose that MPS is 1600 eight hytes, then it just can hold and be used for down the buffering area that a bag adds some extra expenses (about 448 bytes).A word can utilize the core clock frequency of 77.8MHz to write Rx FIFO.Each receives the interval (4 FCS eight hytes+1 flag sequence eight hytes) that minimum 5 eight hytes are arranged between the information field.Every 77.8MHz core clock cycle has 4 SPE payload eight hytes and arrives, and therefore, every 77.8MHz core clock cycle can write Rx FIFO with a word.Therefore for the SAPI/ information field of any size, writing interface at Rx FIFO all has enough bandwidth to store the SAPI/ information field.Write interface at Rx FIFO like this, have enough bandwidth to handle the reception of any LAPS payload stream.
Rx FIFO overflows event handling
IP over SDH/SONET deframer writes bag at receive direction to Rx FIFO.If Rx FIFO has been filled full (last free Bytes of Rx slot fifo is filled), will produce an alarm signal and overflow incident to the management interface report, the generation that FIFO overflows incident also can cause performance counter to add one simultaneously.In the case, EOP (end-of-packet) field that is stored in the last character of Rx FIFO will be configured to logical one automatically.
For the bag that the full incident of Rx FIFO occurs, remaining bag eight hyte (if there is) will can not be stored in Rx FIFO.Further, before receiving the programmable initializing signal of sky storage area, word can not be write Rx FIFO.Follow first word that full incident writes Rx FIFO closely and should be the word of SOP (unwrapping the beginning) mark.
The mistake processing procedure
The LAPS frame that some event definitions receive is " makeing mistakes ", for these erroneous frame, can adopt two kinds of different processing procedures:
(1) error flag.IP over SDH/SONET framer by the erroneous frame that Rx FIFO overflows destruction, is arranged to RX_ERR, corresponding LAPS erroneous frame with last the SAPI/ information field word that writes Rx FIFO with mark.
(2) bag abandons.Writing Rx FIFO is invalid corresponding to the word (bag) of all SAPI/ information fields of LAPS erroneous frame.
The connection management function
As shown in Figure 7, IOSL framer/deframer is included in the connection management unit 36 of decision error in the data transmission procedure or disconnection.This connection management unit 36 randomly is used for monitoring the Link State that receives the peer link frame.It only is a local event, the frame that use of not being correlated with between RX and TX two ends.
Connection management unit 36 specifically comprises timer T200 sum counter N200.
After-the initialization (default value of T200 and N200 was respectively 1 second and 3), link
Entity just enters the normal operating conditions of transmitter and receiver.
If-timer T200 is before receiving arbitrary frame (when comprising information frame and interframe
Between fill) counted fullly, the link entity will be restarted timer T200, and the retransmission count of successively decreasing
Device N200.
If-before receiving arbitrary frame signal, timer T200 meter is full, the repeating transmission meter
The number device has been kept to 0, and the link entity just utilizes the MDL-ERROR indication, connects to this locality
Take over the reason entity and indicate this situation, and restart timer T200 and compose N200 again
Value.
The value of-T200 and N200 can dispose, and T200 and N200 are configurable
Little value is respectively 100 milliseconds and 1.
Can obtain following statistics from the performance monitoring counter.The length of over-all properties monitor counter should be 32 long.
● receive empty LAPS frame
● receive oversize bag
● receive invalid frame
Describe the processing procedure of TX LAPS processor below in detail.
Send the LAPS processor
LAPS in the TX LAPS processor 22 sends (Tx) processing procedure and mainly comprises following function:
-from TX FIFO 18, read IPv4, IPv6 or ppp protocol data cell also
Be encapsulated in the LAPS frame, this LAPS frame satisfies and to be mapped to the requirement of SPE payload.
-LAPS encapsulation comprises: beginning flag sequence, address field, control field, SAPI
(service access point identifier), information field (IPv4, IPv6 or ppp protocol data cell),
FCS (Frame Check Sequence) field and end mark sequence.
SPE (synchronous payload zone) the byte stream supposition of-transmission comprises one or more continuous
LAPS frame stream.
Specifically: sending LAPS processor 22 provides the information insertion STS SPE based on bag.It provides, and generation, the parlor of sealing dress, FCS field are filled, the TX fifo error recovers and scrambler.Send the LAPS processor and finish following function:
● will seal and install in the LAPS frame.The FCS that utilize beginning flag (0x7E), chooses wantonly
Field, optional address, control field, SAPI and the trailer field sign of choosing wantonly (0x7E)
Each bag is encapsulated.
● optional motor synchronizing sends payload scrambler (X 43+ 1 multinomial).
● the transparency that X.85 requires according to ITU-T is handled and (is used to indicate and controls escape
Byte is filled).Carrying out byte between the starting and ending of field sign fills.Utilize two
Byte sequence is replaced any byte that is complementary with sign or control escape byte, this two byte
Sequence adds true form and hexadecimal (0x20) by control escape byte and carries out that XOR obtains
Value is formed.
● produce starting and ending field sign (0x7E), notice that a single sign is passable
Share by two bags.
● randomly Frame Check Sequence (FCS) field is produced 32 CRC.
● provide the function of inserting the FCS mistake, so that under SW control, test.
● the TX_PRTY mistake produces interrupts.
● but the concentration treatment of FIFO underflow is provided.When TX FIFO becomes empty prior to inclusion
During Shu Fasheng, just produce the FIFO underflow.When this thing happens, produce an interruption.
Bag can adopt following manner to finish: produce fcs error; Produce terminator sequence; Pass through SW
Configurable escape code inserts " filling (fill) " byte between the slit.
● produce the performance monitoring counting, comprising: fifo error event number, termination bag number, separated
The bag number (SW is configurable) of anti-the shortest and the longest bag long parameter.
The encapsulation of LAPS frame
Adopt flag sequence to describe each frame of data link layer according to the present invention.Sign is used to indicate the starting and ending of LAPS frame.According to the needs of speed, between the LAPS frame, insert flag sequence and make LAPS frame eight hytes stream also be applicable to SPE payload bandwidth.The LAPS frame that sends separates with a flag sequence at least, and flag sequence value eight hytes of insertion can programmed configurations, and default value is 0x7E.The end mark of former frame can be the beginning flag of back one frame.
LAPS?SAPI。Inserted the SAPI field before information field, the SAPI field value of insertion can pass through programmed configurations, and decides according to the type of data packet of encapsulation.SAPI is judged according to the type of input packet by decision unit.For based on IPv4, based on IPv6, corresponding value is respectively " 0021 ", " 0057 ".Other value sees also RFC 1700.
The LAPS control field.The back of address field is immediately following control field, and the control word segment value of insertion can be provided with, and default value is 0x03.
Address field is positioned at after the beginning flag, can be " 0x04 " or " 0xff ", also can change by programmed configurations.
LAPS Frame Check Sequence (FCS).FCS calculates all addresses, control, SAPI and information field, and it does not comprise flag sequence, does not also comprise FCS field oneself itself.Finish that to calculate be to carry out before filling carrying out byte.Can produce two kinds of FCS types.First kind is 16 CRC function, and it is by generator polynomial 1+x 5+ x 12+ x 16Produce.(note: when the address value of LAPS is arranged to " 11111111 ", when compatible, 16 FCS are with reference to RFC 2615 with RFC 2615, and in this case, the length of FCS becomes 2 eight hytes).Second kind is 32 CRC-32, and it is by generator polynomial (referring to X.85) 1+x+x 2+ x 4+ x 5+ x 7+ x 8+ x 10+ x 11+ x 12+ x 16+ x 22+ x 23+ x 26+ x 32Produce.
IOSL framer/deframer 11 is supported the generation and the verification of CRC-32 Frame Check Sequence (FCS).FCS at first sends minimum effective eight hytes, and it comprises high order system.Can adopt least significant bit order or highest significant position to calculate FCS in proper order by regulation IOSL device.
The FCS field is that all of address field, control field, SAPI field, information field are calculated, but does not comprise eight hytes that are used for the transparency of insertion.This does not also comprise flag sequence and FCS field oneself itself.In this dual mode, CRC generator and checker all are initialized to logical one.Finish after the calculating of FCS, the FCS value is the complement code of " 1 ".And with this new value insertion FCS field.
Before inserting the LAPS frame, with the FCS value calculated respectively with 0xFFFF or 0xFFFFFFFF, carry out XOR, corresponding respectively 16 or 32 s' FCS, the FCS value of calculating this moment is a complement code just.Minimum effectively FCS eight hytes (high order system) are the FCS bytes of inserting at first/sending, and it tightly is positioned at after the last information field byte.Each eight hyte is at first with in least significant bit (sending at last) the feed-in CRC calculator.Under the default situation, insertion be 32 FCS value.
Eight hytes are filled
LAPS eight hyte filling processs (also claiming the escape conversion sometimes) are after FCS calculates and carries out the part scrambler, and transmission LAPS frame is carried out.Seek control escape eight hytes between the starting and ending flag sequence of whole LAPS frames, when finding, 0x7E is converted into 0x7D, 0x5E.0x7D is converted into 0x7D, 0x5D.Terminator sequence should not be thought of as escape sequence.
Control escape eight hyte byte values can programmed configurations, and default value is 0x7D.Byte is filled flag byte can programmed configurations, and default value is 0x20.
With self-synchronous scrambler (SSS) X 43+ 1 scrambler
Fig. 9 A illustrates the structure of scrambler 23 among Fig. 7 of one embodiment of the invention.Shown in Fig. 9 A, scrambler 23 comprises an XOR gate and one 43 s' shift register, and the initial data of dateout and input is carried out XOR and calculated, and produces the scrambler data.
The data that send are utilized self-synchronous scrambler X 43+ 1 carries out descrambling, and each of transmission is according to their order of transmission scrambler successively.Scrambler can adopt three kinds of modes to move: full scrambler, part scrambler and scrambler not.The selection of three kinds of alternative is determined by initial configuration.Full scrambler is before it is mapped to SPE, just adopts SSS, and promptly the full content of SPE payload all will carry out scrambler; The part scrambler is meant that all LAPS eight hytes except flag sequence and termination escape byte all will adopt SSS.The part scrambler is that filling process is used before and after producing the PPP/LAPS field.Two kinds of scrambler processes can independent ON/OFF (on/off).No scrambler is meant forbids the scrambler function.Be not to add the scrambler function, this is for extremely important with old device intercommunicating.Default situation be only with full scrambling code setting for opening (enabling).
SAPI and information field
SAPI and information field can innerly produce, or obtain from Tx FIFO according to each LAPS frame, and this Tx FIFO aligns with 32 bit boundarys for STM-16c/OC-48c; STM-4c/OC-12c aligns with 16 bit boundarys; STM-1/OC-3c aligns with 8 bit boundarys.When inside produces, SAPI field size of inserting (1 or 2 bytes) or numerical value should programmed configurations, default value is 2 eight hytes, numerical value is 0021 (representative is based on the IPv4 business), when when TX FIFO obtains, the bag that deposits Tx FIFO in just inserts in the LAPS frame that generates as the SAPI/ information field.Under the default situation, the source of SAPI field is exactly Tx FIFO.
According to each LAPS frame, each wraps for STM-16c/OC-48c, aligns with 32 bit boundarys; STM-4c/OC-12c aligns with 16 bit boundarys; STM-1/OC-3c aligns with 8 bit boundarys.The size of Tx FIFO is a programmable configuration in the scope of 1 to 4096 word, and this moment, 1 word equaled 32.Under the default situation, size is 4096 words, equals the bag storage of 16384 eight hytes.
All that are stored in Tx FIFO effectively bag eight hytes all are read out, and are mapped in the SAPI/ information field of LAPS frame of generation.Data will be read from Tx FIFO, and in the mode of back-to-back (back-to-back) the LAPS frame will be mapped among the SPE.
Under the bag forward mode, when occurring an EOP (end-of-packet) marker word among the Tx FIFO at least, just begin to read bag.Under the word forward mode, when whole bag does not also store among the Tx FIFO, just can begin from Tx FIFO, to read bag.Default mode is the word forward mode.
Tx FIFO underflow processing procedure
From the process of TX FIFO sense data bag, if before reading EOP bag marker word, TxFIFO moves in a kind of unloaded mode of not expecting, will wrap the LAPS frame that shines upon and just can randomly utilize the LAPS terminator sequence to stop.If frame abandons because Tx FIFO underflow (hunger) causes thereafter, the LAPS termination request that produces by cpu i/f still is effective.
If optional termination option is to be arranged to close (off), the LAPS frame of transmission will finish according to the FCS field of calculating.When underflow took place, the residue packet portion of reading from Tx FIFO will be washed out (flush).Before finding the SOP marker word, always from Tx FIFO read data.Simultaneously, send empty frame.
Abort frame
Special byte code (0x7D 0x7E) is used to indicate frame to be terminated.If receive these bytes, relevant frame will be dropped.If bag sends to the chain circuit device of equity, then be labeled as mistake.
Describe the framer/deframer of one embodiment of the present of invention below in detail in the processing procedure of sending direction to data.
At sending direction, the IOSL device provides the function of inserting STS/STM SPE based on the data of bag.The mode of operation of this device can be by management control interface regulation.
Send fifo interface
In the IOSL device, the transmitting system interface is as " POS PHY/UTOPIA " compatible system interface work.
-transmission FIFO
The transmitting system interface is by link layer device control, link layer device at the sending direction of transmission path prior to the IOSL device.Link layer is provided to the interface of IOSL device, is used for synchronous all interfaces and passes on buffer (the being FIFO) clock of a rate-matched of this about provisioning request IOSL device employing.FIFO is of a size of 256 eight hytes.
The IOSL device also by FIFO pass on the bag situation (bag/cell initial/finish, whether the last character of bag signal forms the bag mistake by 1 or 2 bytes).
-transmission fifo error
In the IOSL device, by the state of IOSL assembly monitor FIFO.Whenever following condition, fifo error appearring: 1) receives IOS_TX_SOP before prior to receiving end-of-packet mark (TX_EOP indication); Or 2) assert that no longer after the TX_CLAV signal, IOS_TX_ENB is effective outside " send window ".By IOS_TX_FIFOERR_E=1 being set to management interface report fifo error incident.
The IOSL device comprises 8 fifo error counters, and counting is by each bag of fifo error events affecting.
When the performance monitoring counter was latched, this Counter Value was by IOS_TX_FIFOERR_CNT[7:0] latch, and remove the fifo error counter.
If because the last rising edge of LATCH_EVENT has a fifo error incident at least, (set) fifo error event bit IOS_TX_FIFOERR_SECE so just is set.
Under ios mode (IOS_TX_IOS=1), the IOSL device stops erroneous packets.
The processing of-IOS erroneous packets
Under the IOS operational mode (IOS_TX_IOS=1), provide following erroneous packets processing procedure:
--the indication of TX_ERR link layer
The transmitting system interface provides a kind of indicating means, when special packet comprises mistake, (sees the definition of IOS_TX_ERR) in the time of should being terminated or abandoning, and link layer device just can be indicated to the IOSL device.
The IOSL device comprises 8 fifo error counters, and count tag is each bag that the link layer of makeing mistakes receives.When the performance monitoring counter is latched (LATCH_EVENT becomes height), this Counter Value is by IOS_TX_IOS_LLPKT_ERRCNT[7:0] latch, and remove the fifo error counter.
If, link layer bag error event position IOS_TX_IOS_LLPKT_ERR_SECE so just is set because the last rising edge of LATCH_EVENT has a link layer bag mistake at least.
--minimum/maximum bag is long
As a kind of option, when the IOSL device is violated minimum/maximum bag length at the bag signal, can think that this bag is an erroneous packets, not with its transmission or termination.The size of bag only refers to the size of LAPS bag, does not comprise the byte of being inserted by the IOSL device (flag sequence, address, control, SAPI, FIFO underflow, the transparency or FCS byte).
Minimum and maximum bag length can be carried out programmed configurations by the management control interface.In the IOSL device, one group of value that register-stored is different is arranged, as top mPS, MPS.
-line side bag signal loopback
For test purpose, the IOSL device also provides loopback (Loopback) function for the user, and the bag that will extract from the SDH/SONET signal is put into the FIFO of sending direction, substitutes the data that receive from system interface therein.The LAPS of data experience transmitting terminal handles then, and is sent out back the SDH/LINE circuit.Loop fuction is effective when IOS_R_TO_T_LOOP is set to 1, when IOS_R_TO_T_LOOP is 0, forbids loopback, carries out the normal process process.
Loop fuction is mainly used in the device to test purpose.In the actual motion,, and be filled with packet in the SONET/SDH payload,, periodic mistake may occur because transmitting terminal can not adapt to the full rate of receiving terminal if receive clock is faster than tranmitting data register.
As a kind of selection scheme, the IOSL device can only insert a sign, and indicating is the end of a frame and the beginning of next frame.This controls by management interface, if IOS_TX_IOS_EOP_FLAG=1, the IOSL device inserts sign separately, shows the beginning and the end of frame; If IOS_TX_IOS_EOP_FLAG=0 (default value) just only inserts a flag sequence.
Generation in the FCS field is in particular cases forbidden, and the IOSL device is ignored IOS_TX_IOS_EOP_FLAG, still total for insert frame initial/the end mark sequence.This is a kind of off-gauge operation, because according to ITU-T X.85, the FCS field is compulsory, and this characteristic requires at test period, and receiving terminal guarantees suitable operational mode, and wherein, FCS is forbidden, and the bag of single byte is possible.
--address and control field
The beginning flag sequence that follows frame closely has two fields: be arranged to the address field of " 0x04 " or " 0xff " (also can pass through configuration change) and be defined as 00000011 control field.Under ios mode (IOS_TX_IOS=1), randomly, if IOS_TX_IOS_ADRCTL_INS=1, the IOSL device just inserts these fields.If IOS_TX_IOS_ADRCTL_INS=0 (default) does not just insert these fields.
--the transparency
Realize eight hyte filling processs herein, be also referred to as transparent processing procedure.Special byte---control escape (01111101 or 16 system 0x7D) is as a sign, and indicating these bytes need carry out special processing at receiver side.The control escape is used for the appearance of marker frame data specific coding.
After FCS calculating, the IOSL device is checked entire frame between any two flag sequences, sign indicating number that is designated 0x7E or 0x7D of every discovery, just with two eight hyte sequence replacings, this pair eight hyte sequences are got with true form and hexadecimal number 0x20 XOR by control escape eight hytes.The IOSL device carries out transparent processing procedure to the byte sequence of back, except being used to of being inserted by the IOSL device describes the flag sequence of frame signal.It is as follows the 0x7E processing procedure to occur in the payload (between the flag sequence):
0x7E is converted into 0x7D, 0x5E
0x7D is converted into 0x7D, 0x5D
The foundation of SPE
The IOS data flow is mapped in the payload in SONET/SDH synchronous payload zone (SPE) subsequently.The border of IOS eight hytes is the boundary alignments with SPE eight hytes.Because the IOS frame is elongated, allow it to cross over the border of SPE.In the running, when no LAPS frame can insert SPE immediately, just send flag sequence and fill time between the LAPS frame.This only just can carry out between whole frame.
The generation of SPE/VC
The structure of-SPE/VC
First row of SPE/VC are POH.Shown in Fig. 8 A-8C, the order for 9 bytes of SONET and SDH is shown below.
For ease of reference, the bandwidth of SDH virtual container and STM interface rate are respectively shown in table 2 and Fig. 3.
The bandwidth of table 2 SDH virtual container
Virtual container (VC) type VC bandwidth (kbit/s) VC net load (kbit/s)
????VC-11 ????1?664 ????1?600
????VC-12 ????2?240 ????2?176
????VC-2 ????6?848 ????6?784
????VC-3 ????48?960 ????48?384
????VC-4 ????150?336 ????149?760
????VC-4-4c ????601?304 ????599?040
????VC-4-16c ????2?405?376 ????2?396?160
????VC-4-64c* ????9?621?504 ????9?584?640
Table 3 STM interface rate
The STM type STM speed (kbit/s)
????sSTM-11 ????2?880
????sSTM-12 ????5?184
????sSTM-14 ????9?792
????sSTM-18 ????19?792
????sSTM-116 ????37?444
????sSTM-21 ????7?488
????sSTM-22 ????14?400
????sSTM-24 ????28?224
????STM-0 ????51?840
????STM-1 ????155?052
????STM-4 ????622?080
????STM-16 ????2?488?320
????STM-64 ????9?953?280
The SONET transmission rate is the integral multiple of STS-1 (51.840Mbps), and the multiple of current permission is as follows:
STS-1：51.840Mbps
STS-3：155.520Mbps
STS-9：466.560Mbps
STS-12：622.080Mbps
STS-18：933.120Mbps
STS-24：1244.160Mbps
STS-36：1866.240Mbps
STS-48：2488.320Mbps
STS-192：9?953?280Mbps
-POH
Path overhead has 9 bytes.First byte of path overhead is passage track byte J1.Its position for the TOH/SOH of SONET/SDH is indicated by relevant STS/AU pointer.Next joint has defined the transmission value of POH byte.Because the name between SONET and the SDH is different, before the name of SONET is listed in.
--passage track (J1)
The 205L device can be made as the passage trace message that in j1 byte, sends 16 bytes or 64 bytes.These message deposit IOS_TX_J1_[63:0 in] _ [7:0].If IOS_TX_J1SEL=0 is then with IOS_TX_J1_[15] _ [7:0] down number to IOS_TX_J1_[0] _ 16 byte sequences of [7:0], repeat to send j1 byte.Otherwise, send IOS_TX_J1_[63] _ [7:0] to IOS_TX_J1_[0] _ byte sequence of [7:0] lining.(under the SDH pattern, adopt 16 byte sequences usually, the SONET pattern then adopts 64 byte sequences.)
--channel B IP-8 (B3)
If B3_INV=0 just sends Bit Interleave check byte (BIP-8),, otherwise, generate odd (incorrect situation) as even parity check (normal condition).BIP8 calculates by all bytes (comprising POH) to last SPE/VC, and places the B3 byte of current SPE/VC.
According to the definition of BIP-8, first of B3 provides all bytes of last SPE/VC primary verification; Second of B3 provides all bytes of a SPE/VC deputy verification, or the like.
--marker (C2)
The marker byte indicates the composition of SPE/VC, with TX_C2_[7:0] in the C2 byte that insert to generate of setting.
--channel status (G1)
Path?REI。Receiving terminal monitors the mistake of B3 position in the SPE/VC that receives.The detected B3 mistake number of every frame (0 to 8) is transferred to transmitting terminal from receiving terminal, inserts sendaisle state byte G1, indicates as the far-end mistake.
If FORCE_G1ERR=1,4 MSB of G1 send (doing test uses) continuously with 1000.Otherwise, if PERI_INH=0, just it is set to equal the binary value (0000 to 1000, expression 0 to 8) of the nearest detected B3 mistake number of receiving terminal POH monitoring module.If other situation all is set to zero with it.
Path?RDI。The 5th of G1 can be used as passage/AU remote failure indication (RDI-P), perhaps the 5th, 6 and 7 of G1 the RDI-P designator as enhancing.Transmission value among the 5th, 6 and 7 of the G1 or from TX_G1_[2:0] register takes out (if PRDI_AUTO=0), perhaps the IOSL device generates RDI signal (if the PRDI_AUTO=1 of an enhancing automatically, and PRDI_ENH=1), perhaps take out (if PRDI_AUTO=1, and PRDI_ENH=0) by RDI signal.The the 5th, 6 and 7 the transmission value of G1 is as shown in table 4.
Table 4 passage RDI place value
????PRDI_ Auto ????PRDI_ ENH ????RX_PA ?IS ????RX_LO ?P ????RX_UN ?EQ ???? RX_ PLM 5,6 and 7 of G1
????0 ????x ????x ????x ????x ????Tx_G1[2 ??，0]
????1 ????0 ????1 ????x ????x ????100
????0 ????x ????x ????000
????1 ????1 ????x ????x ????101
????0 ????1 ????x ????110
????0 ????0 ????1 ????010
????0 ????0 ????0 ????001
As PRDI_AUTO=1, minimum transmission 20 frames of value recited above, in case sent 20 frames with identical value, just send faulty indication value correspondence in the table 1 current state.
The 8th (least significant bit) of G1 do not use, and is set to 0.
--other POH byte
The IOSL device is not supported remaining POH byte, all sends with fixing complete zero byte.These bytes comprise that passage subscriber channel (F2), location pointer (H4), passage growth/subscriber channel (Z3/F3), passage growth/passage APS channel (Z4/K3) and tandem connect monitoring byte (Z5/N1).
The SONET/SDH frame generates
SONET/SDH frame generation module is created STS-3c/STM-1 by generating transmission (section) expense (TOH/SOH) byte, using from the byte of SPE/VC and fill payload, all bytes of the SONET/SDH except that TOH/SOH byte first row are carried out scrambler.
-frame is arranged
Concerning input TX_FRAME_IN, the position of delta frame is fixed.The initial indication of frame output TX_FRAME_OUT and TX_FRAME_IN import the fixing but relation of non-regulation.Last 1 the clock cycle broad pulse of TX_FRAME_OUT and transmitting line output TX_DATA[7:0] relation of data byte is by IOS_TX_FOUT_BYTE_TYPE[1:0] and TX_FOUT_BYTE_NUMBER[3:0] register controlled.
-payload generates
SONET or SDH payload under normal circumstances form by filling from the byte of SPE/VC.The j1 byte of SPE/VC is placed on the 1st row the 10th row in STS-3c/STM-1 pattern (IOS_TX_SIG_MODE=0).
--AIS generates
(multiplex section, (administrative unit during AU) AIS PAIS sends, is suspended the normal generation of (suspend) SONET/SDH payload to MS) AIS (AIS) LAIS, or passage at circuit.The generation of IOS_TX_LAIS and IOS_TX_PAIS register controlled AIS.
If IOS_TX_LAIS or IOS_TX_PAIS=1, whole payload (9396 or 2349 byte) all is filled to complete 1 byte.
--there is not the generation of filling
Unless activated AIS, otherwise, if TX_UNEQ=1 just generates the SPE/VC (all SPE/VC bytes are all filled with the all-zero word joint) that does not have filling.
-TOH/SOH generates
SONET TOH byte is the same with SDH TOH byte usually.Hereinafter define all TOH/SOH byte values that generate.When SONET is different with SDH byte title, at first list the used title of SONET.Blank part in the standard is the undefined or nonstandardized technique reserve bytes in SDH among the SONET.The IOSL device is all used full zero padding with these bytes.
--AIS generates
In LAIS or PAIS transport process, suspend the normal generation of TOH/SOH byte.If IOS_TX_LAIS=1 normally generate TOH/SOH 3 row, but TOH/SOH remainder (and all SPE/VC bytes) transmits as complete 1 byte.If IOS_TX_PAIS=1, the pointer byte in the 4th row, all row bytes of TOH/SOH all normally generate.H1, H2 and H3 byte (and all SPE/VC bytes) transmit with complete 1 byte.
--frame byte (A1 and A2)
The frame byte of set form below normal the generation:
●A1：1111_0110＝F6；
●A2：0010_1000＝28。
For the purpose of testing, A1 and A2 can comprise mistake when generating.If A1A2_ERR=0 does not insert mistake.When A1A2_ERR=1, use A1A2_ERR_PAT[15:0] value and A1 and A2 carry out xor operation and in every group of 8 frames, generate m successive frame (wherein m is equivalent to A1A2_ERR_NUM[2:0] binary number).The MSB of A1 is and A1A2_ERR_PAT[15] XOR, the LSB of A2 is and A1A2_ERR_PAT[0] XOR.
--section track/regenerator section track (J0) and section growth/vacant (Z0) section track
During 16 successive frames, the IOSL device sends continuously and is included in IOS_TX_J0_[15:0] _ 16 byte formats of [7:0], from IOS-TX_J0[15] _ [7:0] byte begins to send by the order of successively decreasing.
ITU-T G.707 standard code 16 section track frames of section accessing points identifier (SAPI) of containing the 3rd/G.831 definition sends continuously with continuous J0 byte.Notice that having only frame beginning label byte is 1 at its MSB.
At present, SONET does not have the definition phase gesture function.Unless to similar section track field of SONET definition, all IOS_TX_J0 bytes should adopt 0000_0001 to fill, so that send metric 1 continuously in J0.
Duan Shengchang/vacant.
In STS-12c/STM-4 (IOS_TX_SIG_MODE=1) pattern, make to be equivalent to 2 to 12 binary system and send the Z0 byte in regular turn, in STS-3c/STM-1 (IOS_TX_SIG_MODE=0) pattern, be 2 to 3 (stipulating among the GR-253).
--section BIP-8 (B1)
If IOS_B1_INV=0, B1 Bit Interleave parity check 8 (BIP-8) sends with even check (normally), otherwise generates odd check (incorrect).BIP-8 draws after all calculate to the STS-3c/STM-1 frame behind preceding 1 scrambler, and inserts the B1 byte of present frame before scrambler.By definition BIP-8, first of B1 provides the parity check on first of all bytes of former frame, and second of B1 provides the parity check on second of all bytes of former frame, and the like.
--order line (E1 and E2) and section subscriber channel (F1)
Defined instruction line byte is used for carrying the digitized voice signal of two 64kb/s.F1 byte can use for network provider, and send piece and receive 3 serial inputs: IOS_TX_E1_DATA, IOS_TX_E2_DATA and TX_F1_DATA are used for being inserted among E1, the E2 and F1 byte that will send.From single 64kHz clock (IOS_TX_E1E2F1_CLK) of IOSL device output, so that provide clock reference for these three serials inputs.
First (MSB) of these bytes should begin pulse IOS_TX_FRAME_IN with incoming frame and align.After receiving last position of E1, E2 and F1 byte, the E1 that receives, E2 and F1 byte are inserted in the output SONET/SDH frame.
--data communication channel, DCC (D1-D12)
TOH/SOH has defined two kinds of DCC (data communication channel).Section/regeneration section dcc produces the channel of a 192kb/s with D1, D2 and D3 byte.Circuit/multiplexing section dcc produces the channel of a 576kb/s to the byte of D12 with D4.Transmitting terminal is imported by dual serial: IOS_TX_SDCC_DATA and IOS_TX_LDCC_DATA receive the DCC data.In order to guarantee bit synchronization, the IOS_TX_SDCC_CLK of two clock: 192kHz of transmitting terminal output; And the IOS_TX_LDCC_CLK of 576kHz.Clock signal makes that can be inserted into TOH/SOH for the code stream from IOS_TX_SDCC_DATA and IOS_TX_LDCC_DATA to register retimes.Make according to rising edge because retime, so IOS_TX_SDCC_DATA and IOS_TX_LDCC_DATA input should change at the trailing edge of IOS_TX_SDCC_CLK and IOS_TX_LDCC_CLK.
--pointer byte (H1, H2) and pointer action byte (H3)
H1 and H2 byte comprise 3 fields.Because SPE/VC and TOH generate synchronously, so need not to generate the variation pointer.In contrast, effectively H1 and H2 byte generate with fixed pointer value 522 (decimal system)=10_0000_1010 (binary system), and the H3 byte is fixed as complete 0.J1 byte is placed on the 1st row the 10th row among the SPE/VC in STS-3c/STM-1 pattern (IOS_TX_SIG_MODE=0) like this.
AIS generates: if IOS_TX_LAIS or TX_PAIS are effective, H1, H2 and H3 byte send with complete 1.When IOS_TX_LAIS or TX_PAIS variation, make two positions all become at 0 o'clock, the IOSL device sends first H1 byte with a new data flag that enables (NDF) in next frame.Utilize NDF field generation frame subsequently invalid in first H1 byte.
No AIS generates.First H1-H2 byte is to sending with positive constant pointer, at this moment:
●NDF＝0110；
●SS＝TX_SDH_PG，0；
● pointer value=10_0000_1010;
All other H1-H2 bytes are to sending with cascade indication byte, at this moment:
●NDF＝1001；
●SS＝TX_SDG_PG，0；
● pointer value=11_1111_1111;
--circuit/MS BIP-96/24 (B2)
Below in the explanation of B2 byte, different according to equipment mode (STS-12c pattern and STS-3c pattern), its number slightly changes.In order to describe the operation of two kinds of patterns, the agreement below adopting is distinguished the requirement of every kind of pattern: STS-3c.TOH/SOH has 12[3] individual B2 byte, they provide BIP-96[BIP-24] error detection capability.
Each B2 byte is the 12[3 of previous frame] byte in group one of byte provides BIP-8 parity check.B2 byte in the j row is that the byte that is positioned at j+12k (j+3k) row in the previous frame (TOH/SOH begin in 3 row except) provides BIP-8 parity check, wherein k=0 to 89.If B2_INV=0, BIP-8 sends with even check (normal state).Otherwise, generate odd check (mistake attitude).The BIP-8 value is calculated the byte of previous STS-3c/STM-1 frame before scrambler and is drawn, and inserts before scrambler in the B2 byte of present frame.
--APS channel and circuit/MS AIS/RDI (K1 and K2)
5 highest significant positions of K1 and K2 are as protecting exchange (APS) signal automatically.As AIS or remote failure indication (RDI), in SONET, they also are used for the APS signaling to 3 least significant bits of K2 in circuit/MS level.The IOSL device inserts IOS_TX_K1_[7:0 in the K1 byte that sends], in 5 MSB of the K2 byte that sends, insert IOS_TX_K2_[7:3].
3 LSB positions of K2 are controlled by 3 sources, and according to priority, they are:
● If (if) TX_LAPS=1, send (with all circuits/MS expense word with complete 1
Joint is the same).
● Else if (else if) LRDI_INH=0, and if (IOS_RX_LOS AND
NOT RX_LOS_INH), any among IOS_RX_LOF, IOS_RX_LOC or the IOS_RX_LAIS
One equals 1, and they are with 110 yards transmissions.When no matter when this special event is effective,
The K2 of minimum 20 frames is set to 110.
● Else (otherwise) transmission IOS_TX_K2_[2:0].
RX_LOS can be high effectively (IOS_RX_LOS_LEVEL=0, default value) or low effectively (IOS_RX_LOS_LEVEL=1).In inside, if IOS_RX_LOS_LEVEL=1, anti-phase IOS_RX_LOS produces IOS_RX_LOS.The R6-180 of GR-253 requires regulation detecting and to remove the LOS that receives to R-182, and the 125 μ s temporal interpolations of LOF or LAIS are gone into and removed RDI.
--synchronous regime (S1)
4 LSB of this byte transmit Synchronication status message.The S1 byte that transmission is set equals IOS_TX_S1_[7:0].
--circuit/MS REI (M1)
Receiving terminal is monitored the B2 bit-errors in received signal.The detected B2 mistake of the every frame scope of counting is 0 to 96 B2 position of every frame in the STS-12c/STM-4 pattern, or is 0 to 24 B2 position of every frame in the STS-3c/STM-1 pattern.Under normal circumstances circuit/MS remote error is indicated (REI) byte, and promptly the M1 byte is transmitted in detected B2 error count in the received signal.
By TX_M1_ERR=1 is set, the user can force to send the indication of REI mistake.This makes in the M1 byte any one counting (under the STS-3c/STM-1 pattern) in sending 24.If LREI_INH=0, the M1 byte equals nearest B2 error count.Otherwise, the M1 byte is set to complete 0.
--growth/undefined (Z1 and Z2)
Because the use of Z1 and Z2 byte does not have standardization.The IOSL device is filled these bytes with complete 0.
Scrambler in the HDLC framing
With a frame synchronization scrambler sequence input data are carried out scrambler, the scrambler generator polynomial is g (x)=x 7+ x 6+ 1.Beginning to locate scrambler initialization in a SPE/VC byte (being positioned at the byte of 1 row, 10 row in the STS-3c/STM-1 pattern) is 1111111, and all the SONET/SDH signals except that the first row TOH/SOH are carried out scrambler.For the purpose of testing, can be 1 scrambler to be lost efficacy by the SCRINH position is set.
As mentioned above, the LAPS frame is encapsulated among the SPE/VC in the SDH/SONET frame, and the LAPS frame can obtain from a plurality of virtual containers, is called so-called cascade.Pointer indication virtual container, the just original position of payload inserted.
The data handling procedure of one embodiment of the present of invention at receive direction below described.
The data handling procedure of receive direction
T is to loopback and the LOC of R
If R_LOOP=1, IOSL device receiving unit can be configured to the transmission signal that loopback (Loopback) generates.Otherwise, select the signal that receives from the SONET/SDH interface.In loopback, utilize the TX_SONETCLK input to determine to receive the clock of framer and other receiving circuit.If do not select loopback, the RX_SONETCLK input is used for determining the clock of this circuit.
The RX_SONETCLK input is lost with TX_CLK input watchdog timer.Do not detect conversion if RX_SONETCLK is last 16 TX_CLK cycles, the RX_LOC position then is set.If detected conversion, then remove it.If RX_LOC transforms to 1 or transform to 0 from 1 from 0, the RX_LOC_Ddelta position just is set.
Transport overhead monitors
The TOH/SOH monitor module is made up of J0, B2, K1K2, S1 and M1 supervision byte.Monitor these TOH/SOH bytes have inerrancy or state whether to change.
-J0 byte monitors
J0 monitors two kinds of operational modes, and a kind of SONET that is used for uses, and a kind of SDH that is used for uses.Under IOS_RX_J0=0 pattern (SONET), the J0 supervision comprises checks whether the J0 byte value mates unanimity in 3 successive frames that receive.When receiving identical J0 value, it is write IOS_RX_J0_[15] _ [7:0].
Under IOS_RX_J0=1 situation (SDH), the J0 byte can comprise 16 byte section track frames of a repetition, this frame section of comprising accessing points identifier.J0 monitors whether initial, the inspection receiver section track frame value that comprise locking 16 byte section track frames mate identical at 3 successive frames.When receiving identical frame value, it is write IOS_RX_J0_[15:0] _ [7:0].First byte (comprising the frame beginning flag) of section track frame writes IOS_RX_J0_[15] _ [7:0].
--framing
Except that the MSB of frame beginning flag byte, the MSB of all sections track frame byte is 0.J0 monitors 15 continuous J0 bytes of framer search, and searching at this byte MSB is 0, after the J0 byte MSB that connects be 1 Jo byte.When finding this sign indicating number type (pattern), framer enters in the frame, at this moment J0_OOF=0.In case J0 monitors framer in frame, it stays in the frame always has 1 MSB bit-errors at least in receiving 3 continuous segment track frames.If IOS_RX_J0=0, J0 frame byte is retained in In Frame state IOS_J0_OOF=0.When IOS_J0_OOF changes its state, the IOS_J0_OOF_Ddelta position is set.
--form is accepted and is compared
In case be in the frame, if IOS_RX_J0=1, the J0 monitor module is just searched the section track frame of 3 16 continuous bytes; If IOS_RX_J0=0 just searches the section track frame of 1 byte.When receiving 3 consecutive identical frames, the frame of acceptance just deposits IOS_RX_J0_[15:0 in] _ [7:0] (under the SONET pattern, deposit IOS_RX_J0_[15 in] _ [7:0]).The frame of accepting and the previous content of these registers compare, and when having stored a new value, the delta position of IOS_RX_J0-D just are set.
-BIP-96 (B2) verification
In the explanation of B2, according to the pattern (STS-3c) of equipment, number slightly changes below.For the operation of two kinds of situations is described, will utilize following agreement to come the requirement of deterministic model (STS-3c).Whether the B2 byte that the verification of IOSL device receives is correct BIP-8 value.(12 or 3 B2 combination of bytes form 1 BIP-96 or BIP-24 together).Remove the most preceding 3 row of TOH (being SOH in SONET, is RSOH) in SDH, whole 12 or 3 byte groups of every frame are calculated, obtain BIP-96 or BIP-24 even parity check.The data that receive are calculated after the descrambling, the value that obtains then with descrambling after the B2 value of next frame compare.Can obtain 0 to 96 or 0 to 24 do not match (B2 bit-errors) by comparing.The detected B2 bit-errors of every frame number can be inserted into the M1 byte of transmission.
--the B2 error count
The IOSL device comprises one 20 B2 error counter, when BIT_BLKCNT=0, and can be to each B2 bit error count; When BIT_BLKCNT=1, can count up to the frame of a rare B2 mistake.When the performance monitoring counter is latched (LATCH_EVENT becomes high level), the value of this counter is just by B2_ERRCNT[19:0] register latchs, and removing B2 error counter.If because the last rising edge of LATCH_EVENT, and when causing also having a B2 mistake at least, the B2 mistake second event bit B2ERR_SECE is set then.Adopt B2 error rate threshold module.
For whether the error rate of judging received signal is higher or lower than the different threshold values (signal fault and signal degrade condition) of two regulations, the IOSL device provides two B2 error rate threshold modules.If SF module or SD module decision error rate are higher than threshold value, B2_ERR_SF or B2_ERR_SD just are set.If corresponding error rate position has changed value, delta position B2_ERR_SF_D or B2_ERR_SD_D are set also.For every kind of error rate threshold module, the user can stipulate BLOCK (piece) register and 2 couples of THRESH (threshold value) and GROUP (group) register.In order to allow to be provided with and to remove the hysteresis of mode bit, each error rate threshold module has 1 couple of THRESH and GROUP register that state is set, and the 1 couple of THRESH and GROUP register come the removing state.Therefore the register that is used for the error threshold module is
Work as B2_ERR_SF=0, judge whether it should use: B2_BLOCK_SF[7:0],
B2_THRESH_SET_SF[7:0], and B2_GROUP_SET_SF[5:0] be provided with,
Work as B2_ERR_SF=1, judge whether it should use: B2_BLOCK_SF[7:0],
B2_THRESH_CLR_SF[7:0], and B2_GROUP_CLR_SF[5:0] remove,
Work as B2_ERR_SD=0, judge whether it should use: B2_BLOCK_SD[15:0],
B2_THRESH_SET_SD[5:0], and B2_GROUP_SET_SD[5:0] be provided with,
Work as B2_ERR_SD=1, judge whether it should use: B2_BLOCK_SD[15:0],
B2_THRESH_CLR_SD[5:0], and B2_GROUP_CLR_SD[5:0] remove.
K1K2 monitors
K1 and K2 byte are to be used to send Line/MS AIS or RDI, and are used for the APS signaling, monitor the change of their state.
The generation of-Line/MS AIS supervision and LRDI
3 LSB of K2 byte can be used in AIS or far-end faulty indication (RDI) on circuit/MS level.If for K2_CONSEC[3:0] successive frame receives that all they are " 111 ", and RX_LAIS just is set, RX_LAIS_OUT is output as height simultaneously; If for K2_CONSEC[3:0] successive frame do not receive that they are " 111 ", just remove RX_LAIS and RX_LAIS_OUT.When the RX_LAIS state changes, RX_LAIS_D delta position just is set.
-Line/MS RDI monitors
3 LSB of K2 byte also can be used to monitor simultaneously K2_CONSEC[3:0] receive " 110 " continuously or do not receive " 110 ", when this thing happens, just be provided with or remove RX_LRDI, RX_LRDI_D when changing state, RX_LRDI just is set.
-APS monitors
4 MSB of K1 byte and K2 byte are used to send the APS request and the number of channel, when receiving same numerical value for 3 successive frames, just it are write RX_K1_[7:0] and RX_K2_[7:4].The original value of value that will receive and register compares then, when depositing new 12 place values in, RX_K1_D delta position just is set.
Inspection K1 byte is watched its unsteadiness.If in 12 successive frames, when not having 3 successive frames to receive same K1 byte, the K1_UNSTAB position just is set, when all receiving same K1 byte, just remove continuous 3 frames.When K1_UNSTAB changes state, K1_UNSTAB_D delta position just is set.0 to 3 of K2 can comprise the APS pattern information, for K2_CONSEC[3:0] monitor whether these are continuous same sample value.Just write RX_K2_[3:0 when above-mentioned situation occurring], unless 1 of K2 byte and 2 value are " 11 " (showing circuit/MS AIS or RDI).When new value writes RX_K2_[3:0] time, RX_K2_D delta position is set.
3 delta position IOS_RX_K1_D, RX_K2_D and IOS_K1_UNSTAB_D are all relevant with the APS supervision, and APS interrupt signal APS_INTB can both be provided.In addition, these 3 kinds of deltas positions can also provide the summary interrupt signal INTB of standard.
-S1 monitors
Whether 4 LSB that monitor the S1 byte that receives are identical value, and under the SONET pattern, IOS_RX_SDH_S1=0 needs to monitor 8 successive frames; Under the SDH pattern, IOS_RX_SDH_S1=1 needs to monitor 3 successive frames.When these comprised identical Synchronication status message, just the value that will receive write RX_S1_[3:0].The value that the value that receives and this register is previous compares, and when having stored a new value, IOS_RX_S1_D delta position just is set.The supervision of S1 byte also is used for the message fault.If because last rising edge of LATCH_EVENT, and do not have message can satisfy above-mentioned effective criterion (whether it is identical with last received value or different), the S1 fault second event bit S1_FAIL_SECE just is set.
-M1 monitors
The B2 mistake that the M1 byte representation is detected in received signal by remote terminal.The IOSL device comprises 1 20 M1 error counter, and when BIT_BLKCNT=0, just counting is by each mistake of M1 indication; When BIT_BLKCNT=1, the M1 that receives with regard to counting is not equal to each frame of 0.When IOS_RX_SIG_MODE=1, under the BIT_BLKCNT=0 situation, the valid value range of M1 is 0 to 96; Other any value all is interpreted as 0 mistake.When RX_SIG_MODE=0 and BIT_BLKCNT=0, the valid value range of M1 byte is 0 to 24; Any other value all is interpreted as 0 mistake.When the performance monitoring counter was latched, the value of this counter was by M1_ERRCNT[19:0] register latchs, and removing M1 error counter.
If, the M1 mistake second event bit M1_ERR_SECE just is set because the last rising edge of LATCH_EVENT makes to also have 1 to receive the indication of M1 mistake at least.
Transmit road (drop) under the expense
Module output in road receives under the TOH/SOH E1, F1 and E2 byte, and 2 serial D CC channels.
-order line (E1 and E2) and subscriber channel section (F1)
3 serials output IOS_RX_E1_DATA, IOS_RX_E2_DATA and IOS_RX_F1_DATA comprise E1, the E2 of reception and the value of F1 byte.Independently 64kHz clock reference output (IOS_RX_E1E2F1_CLK) also is provided, and after the RX_FRAME_OUT rising edge, the MSB of E1, E2 and F1 byte appears at first 64kHz clock cycle.
-data communication channel, DCC, (D1-D12)
Two DCC have been defined among the TOH/SOH.Section/regeneration section dcc adopts D1, D2 and D3 byte to set up the channel of 1 192kb/s.Circuit/multiplexing section dcc adopts D4 to set up the channel of 576kb/s to the D12 byte.The road module is by 2 serial channel RX_SDCC_DATA and RX_LDCC_DATA output DCC data under the TOH/SOH.These channels are synchronous with output IOS_RX_SDCC_CLK and IOS_RX_LDCC_CLK.The output of DCC data changes at the trailing edge of RX_SDCC_CLK and RX_LDCC_CLK.
Pointer state is judged or pointer interpreter
Pointer state judges it is to check the H1-H2 byte, sets up the state of STS-3c/AU-4 reception pointer.
-state variation rule
Judge that in following pointer state according to the pattern (STS-3c) of device, numeral slightly changes in the explanation.For the operation of two kinds of situations is described, will utilize following agreement to come the requirement of deterministic model (STS-3c):
First pair of H1-H2 byte comprises the STS-3c/AU-4 pointer, monitors that this byte is right, and considers that they are one of following three states:
Normally (NORM=00)
Alarm indication signal (AIS=01)
Loss Of Pointer ((LOP=10)
Its remaining 11[2] the H1-H2 byte is used to monitor correct cascade indication.They are considered to one of following three state:
Cascade (CONC=11)
Alarm indication signal (AISC=01)
Loss Of Pointer (LOPC=10)
State storage separately is in IOS_PTR_STATE_[1:12] _ [1:0] [IOS_PTR_STATE_[1:3] _ [1:0]], IOS_PTR_STATE_[i wherein] _ [1:0] expression i is to the state of H1-H2 byte.Merge each then to independent H1-H2 byte, decide the STS-3c/AU-4 pointer state.
-STS-3c/AU-4 pointer state
The IOSL device provides buffer status position IOS_RX_PAIS and IOS_RX_LOP, is used to indicate the pointer state of the STS-3c/AU-4 pointer of reception, and they may be one of three state:
Normal (IOS_RX_PAIS=0 and RX_LOP=0)-IOS_PTR_STATE_[1] _ [1:0]
Be NORM (00), other PTR_STATE_[i] _ [1:0] be CONC (11).
Passage/AU AIS (IOS_RX_PAIS=1 and RX_LOP=0)-all
PTR_STATE_[i] _ [1:0] be AIS or AISC (01).
Loss Of Pointer (IOS_RX_PAIS=0 and IOS_RX_LOP=1)-all other situations
(PTR_STATE_[i] _ [1:0] value can not satisfy normal or passage/AU AIS situation).
IOS_RX_PAIS and IOS_RX_LOP signal offer passage remote failure indication (PRDI).Change by IOS_RX_PAIS_D and bright these state values of IOS_RX_LOP_D delta bit table.
The pointer interpreter unit
In Fig. 7 pointer interpreter unit 28, the H1-H2 byte is to being explained the initial location of thinking SPE/VC, and the pointer interpreter rule is as follows:
1. under normal operation, pointer finds the original position of SPE/VC.
2. current any variation of accepting pointer all will be left in the basket, and remove discontinuous 3 times and will receive 1 identical new pointer value, perhaps because in the rule 3,4 or 5 any one and preferential.Anyly receive identical new pointer value for 3 times and have precedence over rule 3 or 4 continuously.
3. work as IOS_RX_SDH_PI=0, if in 4 NDF positions at least 3 be matched with in invalid indication (0110) and the 10 bit pointer value positions at least 8 and be matched with the current I bit reversal pointer that receives, just show that this is a positive adjustment (justification).Following the byte in H3 byte back is positive byte of padding, and the current pointer value that receives adds 1 (mould 783).
Work as IOS_RX_SDH_PI=1, if at least 3 are matched with invalid indication (0110) in 4 NDF positions, in the pointer value I position 3 or more in multidigit and the pointer value D position 2 or still less the position be matched with current all bit reversal pointers that receive, and the SS position that any one receives is 10 or IOS_RX_SS_EN=0, just shows that this is a positive justification (justification).Following the byte after the H3 byte is positive byte of padding, and the pointer value of current acceptance adds 1 (mould 783).
4. work as IOS_RX_SDH_PI=0, if in 4 NDF positions at least 3 be matched with in invalid indication (0110) and the 10 bit pointer value positions at least 8 and be matched with the current D bit reversal pointer that receives, just show that this is a negative justification.The H3 byte is considered to negative byte of padding (it is the part of SPE), and the current pointer value that receives subtracts 1 (mould 783).
Work as IOS_RX_SDH_PI=1, if in 4 NDF positions at least 3 be matched with forbid the indication (0110), in the pointer value D position 3 or more in multidigit and the pointer value I position 2 or still less the position be matched with current all bit reversal pointers that receive, and the SS position that receives is 10 or IOS_RX_SS_EN=0, just shows that this is a negative justification.The H3 byte is considered to negative byte of padding (it is the part of VC), and the current pointer value that receives subtracts 1 (mould 783).
5. work as IOS_RX_SDH_PI=0, if in 4 NDF positions at least 3 be matched with and enable indication (1001), pointer value is between 0 to 782, the pointer of reception is replaced the current pointer value that has received.
Work as IOS_RX_SDH_PI=1, if in 4 NDF positions at least 3 be matched with enable the indication (1001), pointer value is between 0 to 782, and the SS position that any one receives is 10 or IOS_RX_SS_EN=0, and the pointer that receives is replaced the current pointer value that has received.
Utilize these pointer interpreter rules, the pointer interpreter module is judged the position of SPE/VC payload and POH byte.
-pointer is handled
About realize the pointers track algorithm in the IOSL device, the pointers track state machine is based on ITU-T and requires definite pointer track state machine, and is the same with ansi standard effective to Bellcore.The not conversion of the state machine from AIS to LOP (is logical one as the BELLCORE position is set) in the Bellcore pattern.
Used four pointers track state machines, each AU-4/STS-3c uses one.Pointers track adopts H11 and H21 byte, extracts pointer from the cascade of H1n and H2n byte, is explained as follows:
N=new data flag position is interpreted as: enables=1001 or 0001/1101/1011/1000, and normal or forbid=0110 or 1110/0010/0100/0111 (being tolerable single-bit mistake).
Position in the SS=pointers track state machine is long, if enable, the BELLCORE control bit is set to 0.When BELLCORE is set to 1, ignore these positions, but when it was set to 0, these positions were 10.
I=increases the position, is defined as the position 7 of H1n and the position 1,3,5 and 7 of H2n.
D=reduces the position, is defined as the position 8 of H1n and the position 2,4,6 and 8 of H2n.
Negative justification: 5 the D positions of reversing, accept majority rule.By being arranged on the Just ITU position among the OR#Conf 3 to 0, enable 8 in 10 objects of [GR-253] 03-92.
Positive justification: 5 the I positions of reversing, accept majority rule.By being arranged on the Just ITU position among the OR#Conf 3 to 0, enable 8 in 10 objects of [GR-253] 03-92.
For the STM-1/STS-3c operator scheme, pointer is a binary number, and scope is 0 to 782 (decimal system).It is one 10 a numerical value, and two two least significant bits from the H1 byte are wherein arranged, and with the cascade of H2 byte, forms the deviation of starting at 3 bytes with the H3 byte location.For example, to the STM-1 signal, pointer value is that 0 expression VC-4 3 byte places after the H3 byte begin, and offset field value 3 bytes that are 87 expression VC-4 after the K2 byte.
In the STM-4/STS-12 pattern 4 bytes-staggered AU-4 is arranged, therefore 4 H1/H2 bytes are arranged being used for determining their beginning of VC-4 separately (as the j1 byte position).In this case, the operation of 4 pointers track state machines is equal to the operation of 4 * STM-1/STS-3c.
When treatment S TS-12c/STM-4c, the pointers track state machine to grand 1 is used for locating the initial of VC-4-4c.Use H11 and H21 byte to carry out pointers track, pointer extracts from H11 and H21 cascade byte, and pointer interpreter is as described above.But the offset field that forms is the numerical value of one 12 byte, and its value begins to count from the H3 byte location.For example, to the STM-12c signal, pointer value is that 0 expression VC-4 position, 12 byte places after the H3 byte begins, and offset field value 12 bytes that are 87 expression VC-4 after the K2 byte.In correspondence grand (grand 2-4), also check cascade indication byte, monitor the LOP and the HPAIS of every state machine according to [G.783] annex C.Following state diagram has illustrated the state exchange of cascade indicating device.The conversion definition please refer to [G.783].
In addition, 8 digit counters are used for writing down positive and negative and adjust incident, and the NDF incident.Provide mode bit to be used to refer to the detection of negative justification, positive justification, NDF, null pointer, new pointer and cascade indication.When entering aforesaid LOP or LOPC attitude, LOP interrupt requests position will be set in corresponding OR#IRQ2 register.Equally, if entered AIS or AISC attitude, corresponding HPAIS interrupt requests will be set.
Path overhead monitors
The path overhead monitor module is monitored by J1, B3, C2 and G1 to be formed.These path overhead bytes are used for the wrong of monitored state or change.
-passage track (J1) is caught/is monitored
By inserting j1 byte, the IOSL device is supported two kinds of passage tracks (J1) catching method.First kind is mainly used in SONET, catches 64 continuous j1 bytes in STS-3c/AU-4.Second kind is used for SDH, searches 16 continuous j1 bytes of repetition.Detect 16 identical bytecode types (pattern) in 3 continuous incidents after, the J1 form is stored in the register of appointment.
--SONET J1 catches
When IOS_RX_SDH_J1=0 (SONET pattern), the IOSL device can be made as the sampling of catching the passage trace message.When J1_CAP converts 1 to from 0, the IOSL device is caught 64 j1 bytes continuously on particular branches (tributary), they are write IOS_RX_J1_[63:0] _ [7:0].
Do not have define channel track frame structure among the SONET, but GR-253 advises the sequence of one 64 byte really, this sequence is made up of a string ascii character, and null character (NUL) (00) has been filled 62 bytes, ends up being＜CR〉(0D) and＜LF (0A) byte.If be provided with the J1_CRLF position, the IOSL device is caught from receive byte with { 0A, first 64 byte character string that 0D} finishes on the j1 byte position.If J1_CRLF=0, IOSL device 1 is caught the j1 byte of next 64 bytes, does not consider their content.Catch in case finish, the IOSL device is provided with the J1_CAP_E event bit.
--16 byte J1 monitoring
If IOS_RX_SDH_J1=1 (generally being used for the SDH pattern), j1 byte comprise the passage track frame of 16 bytes of a repetition, it comprises PAPI.In this pattern, do not use J1_CAP, J1_CRLF and J1_CAP_E position.
J1 monitor comprise locking 16 byte lane track frames initial, whether 3 successive frames couplings are consistent to check receive path track frame value.When receiving an identical frame value, it is write IOS_RX_J1_[15:0] _ [7:0].First byte of passage track frame (it comprises the frame beginning flag) writes IOS_RX_J1_[15] _ [7:0].
Framing: except that the MSB of frame beginning flag byte, the MSB of all passage track frame bytes is 0.J1 monitors 15 continuous j1 bytes of framer search, and the MSB of this byte is 0, after connect j1 byte MSB be 1.In case search this form, framer enters in the frame, at this moment J1_OOF=0.In case in frame, staying in the frame always, J1 supervision framer in receiving 3 continuous passage track frames, has 1 MSB bit-errors at least.(in the SONET pattern, the indication of J1 frame remains on In Frame state, J1_OOF=0).If the J1_OOF state changes, J1_OOF_D delta position is set.
Form is accepted and is compared.In case in frame, the J1 monitor module is searched 3 16 continuous byte lane track frames.When receiving 3 consecutive identical frames, the frame of reception just deposits IOS_RX_J1_[15:0 in] _ [7:0].The frame that receives and the previous content of these registers compare.When having stored a new value, the delta position of RX_J1_D just is set.
-BIP-8 (B3) verification
The B3 byte that the inspection of IOSL device receives obtains correct BIP-8 value.By to all even check that calculates BIP-8 among every frame SPE/VC (comprising POH).The B3 value that receives of these values and next frame compares then, and the possibility of result relatively can be 0 to 8 do not match (B3 bit-errors), and this value will be inserted in the G1 byte of transmitting terminal.
The IOSL device comprises 16 B3 error counters, and this counter is to each B3 bit-errors (if BIT_BLKCNT=0) or have at least each frame of a B3 bit-errors (if BIT_BLKCNT=1) to count.When the performance monitoring counter was latched (LATCH_EVENT becomes high level), this Counter Value was locked as B3ERRCNT_[15:0] register, and remove the B3 error counter.
If because last 1 rising edge of LATCH_EVENT, and cause having at least a B3 mistake, B3 mistake event bit B3ERR_SECE for the second time then is set.
-signal label (C2) monitors
The C2 byte that supervision receives, affirmation receives the payload of right type.When continuous 5 frames receive same C2 value, the value that receives is write IOS_RX_C2[7:0] in.When receiving a new C2 value, the delta position of IOS_RX_C2_D is set.
The desired value that receives the C2 byte is retained in EXP_C2[7:0] in.If the value of current acceptance and desired value do not match, the value of acceptance does not meet following condition yet, and then the payload label register-bit IOS_RX_PLM that do not match is set to high level:
● all be 0, be not equipped with label;
● 01 (hexadecimal) has been equipped with non-special tag;
● FC (hexadecimal) has the payload error label;
● FF (hexadecimal), the label of withing a hook at the end.
If the current value that receives is complete 0, no label, and EXP_C2[7:0]!=00 (hexadecimal), it is high level that nothing outfit register-bit IOS_RX_UNEQ then is set.
IOS_RX_PLM and IOS_RX_UNEQ signal provide passage RDI insertion at transmitting terminal.When IOS_RX_PLM or IOS_RX_UNEQ state change, IOS_RX_PLM or IOS_RX_UNEQ delta position are set.
-channel status (G1) monitors
--passage REI monitors
The position 1 of the channel status byte B3 mistake number that 4 (4 MSB) expression remote terminal detects in the SPE/VC signal that it receives that puts in place.Be legal only at 0 to 8 binary value.If the value that receives is greater than 8, it is interpreted as 0 mistake (advising the same of defined G.707 as GR-253 and ITU-T).The IOSL device comprises one 16 G1 error counter, and it is to each mistake (if BIT_BLKCNT=0) counting of G1 indication, perhaps is not equal to each frame (if BIT_BLKCNT=1) counting of 0 to receiving 4 of G1.When the performance monitoring counter is latched (LATCH_EVENT becomes high level), the value of this counter is just by G1_ERRCNT[15:0] register lock, and empty the G1 error counter.
If because last 1 rising edge of LATCH_EVENT, and cause receiving at least a G1 mistake indication, G1 mistake event bit G1ERR_SECE for the second time then is set.
--passage RDI monitors
If IOS_RX_PRDI5=1, IOSL device can monitor G1 the 5th (RDI-P designator); If IOS_RX_PRDI5=0 can monitor the 5th, 6 and 7 of G1 (strengthening the RDI-P designator).Monitoring process comprises checks G1_CONSEC[3:0] whether the supervision place value of reception is identical continuously.When receiving identical value, 5,6 and 7 of G1 write IOS_RX_G1[2:0].Reception value and this register preceding value compare (3 all are written into, if but IOS_RX_PRDI5=1, only with the 5th and the IOS_RX_G1[2 of G1] compare).When new value of storage, the IOS_RX_G1_Ddelta position is set.
-other POH byte
The IOSL device does not monitor other remaining byte of POH.These bytes comprise that passage subscriber channel (F2), location pointer (H4), passage growth/subscriber channel (Z3/F3), passage growth/passage APS channel (Z4/K3) and tandem connect monitoring (Z5/N1) byte.
Receive the descrambling of payload
After from the SONET/SDH signal, extracting payload, payload data motor synchronizing X 43+ 1 descrambler 29 carries out descrambling.In all mode, the operation of register IOS_RX_DSCR_INH control descrambler.When IOS_RX_DSCR_INH=0 (default setting), descrambler operate as normal.Work as IOS_RX_DSCR_INH=1, descrambler is forbidden work.
The IOSL device provides one based on generator polynomial: X 43+ 1 motor synchronizing descrambler.
Receive the LAPS process
SPE extracts from the SONET/SDH frame herein, enters the LAPS processor then and does further processing.Under ios mode, IOS_RX_POS=1, the LAPS processing procedure is wrapped signal/frame with LAPS and is extracted from SPE.
-LAPS deframer
By put distinguishing mark sequence (0x7e) from the start/end of frame, from the SPE payload, extract the LAPS frame.
The IOSL device is checked each eight hyte in the payload, when form is that eight hytes of 0x7e are when being checked through, the IOSL device just thinks that this is the initial/end of 1 bag signal, check eight hytes of closelying follow thereafter then, if still be 0x7e, think that then they are the flag sequences that are used to fill bag signal slit, and it is abandoned.Follow the beginning flag sequence, and first eight hyte that to be not equal to first eight hyte of 0x7e be the LAPS frame.After finding the frame beginning flag, the IOSL device continues to check each eight hyte of payload, searches flag sequence.If found flag sequence, and its front byte for control escape byte (0x7d), then this frame is an abort frame; Otherwise, just think the normal ending of present frame.At the termination of FCS field forbidden in particular cases (seeing the 6.9.5 joint), between each frame, must detect the information that minimum is 2 flag sequences.
The deletion of-transparent byte of padding
The IOSL device recovers the original packet information flow with transparent byte filling process conversely.FIFO underflow byte sequence is to insert in the FIFO of transmitting terminal underflow process, if IOS_RX_POS_FIFOUNDR_MODE=1 needs to detect in transparent processing procedure, and deletion.The default value of this parameter value is for forbidding: IOS_RX_IOS_FIFOUNDR_MODE=0.Special FIFO underflow byte code can utilize register IOS_RX_IOS_FIFOUNDR_BYTE[7:0] configuration.
--the deletion of underflow byte
Under ios mode, the byte if IOS_RX_IOS_FIFOUNDR_MODE=1 is matched with FIFO underflow byte (IOS_RX_IOS_FIFOUNDR_BYTE[7:0]) is thereafter immediately following control escape byte (0x7d) then be dropped.
-erroneous frame
Under ios mode (IOS_RX_IOS=1), utilizing 1 special byte code (0x7d7e) to indicate this frame in 205 patterns is abort frame.If receive this byte, the frame that contains this byte is just for being terminated, and more eight hytes that need not continue to wrap are sent into FIFO; If this bag signal sends to link layer device, then be labeled as mistake.
The IOSL device comprises 18 digit counter, calculates each bag that detects terminator sequence.When the counter of performance monitoring is latched (LATCH_EVENT becomes high level), the value of this counter is by register IOS_RX_IOS_PABORT_ERRCNT[7:0] latch, and remove bag termination error counter.
If because of last 1 rising edge of LATCH_EVENT, and cause also having at least 1 bag to stop mistake, bag then need be set stop the wrong second event bit IOS_RX_IOS_PABORT_ERR_SECE.
As a kind of alternative, also can stop 1 bag by inversed F CS byte.This receives the LAPS processor for the IOSL device, is to have simplified fcs error.Its processing procedure is as the hypomere explanation.
As a kind of option, the IOSL device also can be considered as erroneous packets with bag, and whether violates minimum or maximum bag regulation according to it, and carries out mark.The size of bag only is meant and the bag signal magnitude of coming out from IOSL does not comprise flag sequence, address byte, control byte, SAPI, transparent byte, FIFO underflow byte and the FCS byte removed.Can long minimum value and the maximum of configuration packet by management interface.Register IOS_RX_IOS_PMIN[3:0] comprise long minimum value, the default value of this register is 0; Register IOS_RX_IOS_PMAX[15:0] contain the long maximum of bag, the default value of this register is 0x05E0.
When being when passing through management interface by instruction, the IOSL device can make the minimum and maximum verifying function prohibiting/enabling that wraps.It is long that minimum and maximum bag has been violated in any processing of register IOS_RX_IOS_PMIN_ENB and IOS_RX_IOS_PMAX_ENB (two default value is 0) control.When any one register was set to 1, the bag calipers of any violation correspondence was fixed, all can be labeled as mistake.
The IOSL device comprises 28 digit counters, and counting is violated the fault of the long restriction of minimum and the longest bag respectively.When the performance monitoring counter is latched (LATCH_EVENT becomes high level), Counter Value is by register IOS_RX_IOS_PMIN_ERRCNT[7:0] and IOS_RX_IOS_PMAX_ERRCNT[7:0] latch, and remove bag fault counter.
If because the last rising edge of LATCH_EVENT, and it is wrong to cause also having at least 1 bag size to break rules, and the long second event bit IOS_RX_IOS_PMIN_ERR_SECE or the IOS_RX_IOS_PMAX_ERR_SECE of fault of suitable bag just is set.
-Frame Check Sequence (FCS) field
(IOS_RX_IOS=1) calculates FCS under ios mode,, and in ending place of every frame the FCS byte is checked.This option is controlled by register IOS_RX_IOS_FCS_INH.IOS_RX_IOS_FCS_INH=0 enables FCS.The IOS_RX_IOS_FCS_INH=1 value is for forbidding FCS.Only adopt 32 verification sequence (CRC-32).
IOS_RX_IOS_FCS_MODE=0 makes this device be in the FCS-32 pattern.
The IOSL device provides CRC-32 function, adopts following generator polynomial: 1+x+x 2+ x 4+ x 5+ x 7+ x 8+ x 10+ x 11+ x 12+ x 16+ x 22+ x 23+ x 26+ x 32
The FCS field is calculated and is drawn all frame sign indicating number positions, except flag sequence and FCS field oneself itself.
If IOS_RX_IOS_FCS_BIT_ORDR=0 (default value) adopts highest significant position (being MSB earlier) order that the signal that receives is read into shift register; If IOS_RX_IOS_FCS_BIT_ORDR=1 adopts least significant bit (being LSB earlier) order that the signal that receives is read into shift register.Under any situation, after FCS calculated, data all were to adopt highest significant position to store, so that handle.
The FCS end value that obtains compares with the value that is received in the FCS field, if detect 1 mistake, just informs the management control interface, and corresponding counter adds 1, and last 1 sign of wrapping among the FIFO is designated as mistake.The IOSL device comprises 1 20 fcs error counter, each FCS CRC fault is counted, when the performance monitoring counter is latched (LATCH_EVENT becomes high level), the value of this counter is by register IOS_RX_IOS_FCS_ERRCNT[19:0] latch, and remove the fcs error counter.
If because the last rising edge of LATCH_EVENT, and cause also having at least 1 fcs error, the fcs error second event bit IOS_RX_IOS_FCS_ERR_SECE then is set.
After the FCS verification, stop FCS byte (they do not store FIFO into).If by management interface, the FCS verification is forbidden, last 2 or 4 bytes just send to FIFO.Suppose to detect 1 FCS that when sending to link layer device, mark bag signal is wrong (RX_ERR).
-LAPS frame stops
Under ios mode (IOS_RX_IOS=1), FCS monitors following LAPS byte after calculating, and randomly stops.
--flag sequence
The frame that is useful on is described to fill purpose with interframe and the flag sequence that occurs is all deleted.The starting and ending sign of frame information is still kept by the IOSL device, sends to link layer by RX_SOP and RX_EOP signal.
--address and control byte
Address and control byte (closelying follow preceding two 2 bytes of flag sequence in the LAPS frame) are to be monitored by the IOSL device.Supervision is to check effective address field and control field (0x0403 or 0xFF03).Do not match if detect, just think that this field compresses, do not send.If detect invalid value, these two bytes are not dropped, but deliver to link layer by ios interface.By being set, IOS_RX_IOS_ADRCTL_INVALID=1 informs that the management control interface detects invalid address and control field.By IOS_RX_IOS_ADRCTL_INVALID_D delta position is set is 1, shows that the state of IOS_RX_IOS_ADRCTL_INVALID changes.
If the effective address of detecting and control field (0xFF03), IOSL device just stop this two bytes, do not allow by, arrive RX FIFO.By IOS_RX_IOS_ADRCTL_DROP_INH=1 is set, can forbid deleting effective address and control byte, the default value of this register is 0 (Discard Enable automatically).
--the FCS byte
As mentioning in FCS one joint, the IOSL device also can stop 4 FCS bytes.If forbid the FCS verification by management control interface (IOS_RX_IOS_FCS_INH=1), expiry feature also is under an embargo, and last 4 bytes of LAPS frame send to link layer.
Receive fifo interface
The loopback of-system side bag signal
The bag semiotic function that the IOSL device provides loopback to accept by system interface for the user.
When SYS_T_TO_R_LOOP=1, directly deliver to reception FIFO from the bag that link layer device receives from sending FIFO, output postbacks out the link layer device of this cell data again.When SYS_T_TO_R_LOOP was set to 0, the bag data that receive in the SONET/SDH line signal sent to and receive FIFO, output to system interface then.
-FIFO processing procedure
The IOSL device will wrap data and write FIFO, prepare to output to link layer device by the receiving system interface.FIFO has 256 eight hytes.Together with the bag signal, following applicable identifier must be followed each word of FIFO: the beginning of bag, and the ending of bag, the inclusion tail has several eight hytes (1 still be 2) in 1 word, and wrap and whether make mistakes, or the like.In case detect 1 mistake in bag the signal, no longer include more byte in the bag signal and pack among the FIFO.
The IOSL device monitors the state of FIFO.By IOS_RX_FIFOOVER_E=1 is set, to management control interface report FIFO underflow event, the generation of FIFO underflow also can make corresponding performance monitoring counter increase simultaneously.
The IOSL device comprises the counter of 18 FIFO overflow error, and counting overflows affected each bag of incident because of FIFO.When the performance monitoring counter is latched (LATCH_EVENT becomes high level), the value of this counter is just by register IOS_RX_FIFOOVER_ERRCNT[7:0] latch, and remove FIFO overflow error counter.
If because the last rising edge of LATCH_EVENT, and cause also having 1 FIFO to overflow incident at least, FIFO overflow error event bit IOS_RX_FIFOOVER_ERR_SECE just is set.
In case the overflow error of detecting is sent into FIFO with regard to the byte that no longer includes bag.Under ios mode (IOS_RX_IOS=1), last 1 sign of bag signal is designated as mistake (RX_ERR).
This FIFO just before the receiving system compatibility interface, its objective is the rate-matched function of finishing between SONET clock zone and the link layer clock zone.
--the erroneous packets signal processing
Under ios mode (IOS_RX_IOS=1), the IOSL device adopts RX_ERR, will be labeled as mistake by the bag that the FIFO incident of overflowing is destroyed.
Invalid frame satisfies following condition:
1) not having correct is the boundary with two flag sequences;
2) eight hytes between the flag of frame sequence are less than 8;
3) include a Frame Check Sequence mistake;
4) comprising one does not match or unsupported service access point identifier with receiving terminal
(seeing that ITU-T X.85 A.3.3);
5) comprise a unrecognizable control word segment value;
6) end mark is the sequence above six 1.
Invalid frame will be abandoned by Lost, not notify transmit leg.Do not produce any action for this frame yet.
--receive data parity check
For the regulation of MAC-PHY, the IOSL device provides 1 parity bit, and it follows the word (IOS_RX_SYS_DAT[15:0]) of each eight hyte that sends to link layer or two eight hytes.Provide this parity check bit at the RX_PRTY pin.(IOS_RX_PRTY_MODE=0) provides odd when default; When IOS_RX_PRTY_MODE=1, provide even parity check.
The management control interface
The following describes the management control interface of IOSL, define the address of all registers that read or write by ppu.
The MSB of microprocessor bus address---ADDR[8:0] be that explanation mapping is direction of transfer (ADDR[8]=0) or receive direction (ADDR[8]=1).ADDR[7:0] be the special mapping of indication, differentiating these values is the detailed descriptions that utilize following every kind of mapping.Common configuration and situation mapping table are that ADDR[8 is set]=0.
Interrupt or polling operation
The management control interface can be operated in drives interrupts or poll pattern.Under two kinds of patterns, can both adopt IOSL apparatus registers position SUM_INT to judge whether the monitors register state of IOSL device changes, this information is positioned at the address 0x002 of generic configuration and total situation mapping table.
-interrupt source
--the transmission end
The transmission end register mapping table is almost whole regulation parameters, and its determines the composition of SONET/SDH signal, and the value of LAPS, SONET/SDH POH and SONET/SDH TOH/SOH is provided.Except these predetermined parameter, the transmission end register mapping table comprises that also system interface and general I/O monitor.If these indications are effective words, the SUM_INT position of register 0x002 will be high (logical one).If SUM_INT_MASK=0, the interruption output INTB of Microprocessor Interface becomes effectively (logical zero).
--receiving terminal
Table (TBD) also comprises total mode bit of receiving terminal, the SUM_INT position of these decision registers 0x002 simultaneously at register 0x005.If any position in total mode bit is " 1 ", and corresponding to shelter the position be " 0 ", and then the SUM_INT position is set to " 1 ".
Total mode bit of table (TBD) register 0x005 all is " 1 ", is " 1 " if the corresponding hyte in table (TBD) lining has one or more, need shelter separately TOH/SOH delta position and second event bit (table (TBD), address 0x104-0X106).
-interrupt generating
Interrupting under the generate pattern, the SUM_INT_MASK position of register 0x006 should be eliminated (becoming logical zero) in generic configuration and the total state mapping map.It allows the output of INTB to become effectively (logical zero). (! SUM_INT_MASK﹠amp; ﹠amp; SUM_INT).The IOS_RX_APS_INT_MASK position of receiving terminal should be eliminated (becoming logical zero) in addition, and this allows the output of APS_INTB to become effectively (logical zero). (! IOS_RX_APS_INT_MASK﹠amp; ﹠amp; IOS_RX_APS_INT).
If interrupt, microprocessor is at first read total status register 0x004-0x005, judges the grade of effective interrupt source, reads the particular register of this grade then, judges the accurate reason that interruption takes place.
-poll pattern
In order to suppress all hardware interrupts and under poll pattern, to operate, SUM_INT_MASK and IOS_RX_APS_INT_MASK position (becoming logical one) should be set.Under this pattern, under invalid (logical one) state, keep output INTB and the APS_INTB of IOSL.
Attention: SUM_INT_MASK and IOS_RX_APS_INT_MASK position can not influence the state of register-bit SUM_INT and IOS_RX_APS_INT.Can these bytes of poll, judge whether need more register inquiry.
Microprocessor Interface
Microprocessor Interface connects IOSL device and system CPU, and Microprocessor Interface can make all registers in the system CPU visit IOSL device.Microprocessor Interface can run on interrupts and two kinds of patterns of poll, and in the interrupt mode, the IOSL device can be supported a plurality of interrupt sources.No matter under which kind of interrupt mode, the IOSL device can be sheltered out interruption.
Compatibility with old PPP over SDH/SONET equipment
Figure 10 is the frame format of RFC 2615 and the comparison between the frame format of the present invention.As shown in the figure, if address field is set to 255 (SAPI=0021 simultaneously), the LAPS frame format is the same with PPP/HDLC almost, only need change to 0x16 to the signal mark of SDH or SONET from 0x18, therefore, adopt the IP over SDH of LAPS framer/deframer not need structurally to do any change, just can handle the PPP bag, and the PPP that extracts wrapped send network layer to and carry out the PPP processing with data transmission device of the present invention.
The implementation of embodiments of the invention is complementary and consistent with the scheme of the applicant's PCT international application CN00/00195.People wish to allow LAPS discern the packet of higher level with preceding four eight hytes, rather than only use preceding two eight hytes.The ppp protocol identifier is reused (reuse) in LAPS, and be matched with (on-the-wire) packet format on the line of PPP thus, its advantage is if LAPS needs to define the L2 signaling afterwards again, LAPS can include the PPP signaling in as a reference, and needn't abolish or change LAPS itself by any way.For example, LAPS is used for some item, and PPP is used for other.LAPS frame format of the present invention is a kind of selection that has more flexibility.In a word, adopt the manufacturer of LAPS and PPP will be required to check 4 bytes, certainly, preferably allow LAPS also do like this, come the recognition data bag just enough with two bytes to avoid manufacturer to think.
As for the LAPS frame format, information field is based on 32 IPV4$ or IPV6 data message.If total expense of LAPS comprises address field (one eight hyte), control field (one eight hyte), SAPI field (two eight hytes) and FCS field (four eight hytes), also be based on 32, this is favourable for implementing, especially to handling with high-speed data.In view of this, the present invention has done further improvement on the applicant's PCT application CN00/00195 basis.
According to embodiments of the invention, become 4 byte sequences from 2 byte sequences.So,＜04 03 0021〉and＜04 03 00 57 respectively expression encapsulated IPV4 and IPV6.Between the use of PPP or LAPS and LAPS SAPI, can not occur obscuring,, make it produce difference because can stipulate SDH VC-4 signal mark (C2 byte) for PPP or LAPS.
As for the FCS field, the frame format of embodiments of the invention can be avoided any and obscures, because minimum effective FCS byte (the highest coefficient) is the FCS byte that and then is positioned at first insertion/transmission of last information field byte back.Each byte is imported to the CRC calculator by the minimum order that effectively (transmits) position at last.Each that sends carries out scrambling with the order that they are sent out.
Figure 11 is the network interconnection example that adopts IP over SDH framework according to the present invention.Wherein solid line is represented the physical connection of SDH between the node; Packet switch between the node that dotted line is represented to advise; Dark node has been represented the network edge node of gateway effect; White nodes is represented network backbone node, can see the general picture of IP over SDH network like this from the node angle.What need highlight is: in the IP overSDH network, the IP over SDH Physical Interface of various different rates can be arranged on the link in network, as long as two reciprocity physical interfaces on the same link have same interface rate and physical parameter.
According to data type from network layer or upper strata reception, SAPI value of the present invention is variable, the data that can adapt to IPv4, IPv6, PPP, IS-IS, Ethernet or other type, for example, for the mpeg data transmission, SAPI can be arranged to " 64 " or " 128 " (also can change into other value by configuration feature).Framework of the present invention can be applicable to the SDH that IP is fitted to SDH/SONET, simplification, or IP is fitted to SDH, and then to WDM, or PDH (accurate SDH).For the PDH situation, the packaging information field of LAPS frame is not towards eight hytes towards the position.
From above-mentioned explanation as can be seen, the present invention has disclosed a kind of brand-new data transmission device and method, it can be applied to the IP signal directly is fitted to the core of SDH/SONET and edge router, switching equipment, IP-based network access device, ply-yarn drill, and is used for the high-speed interface unit of Gigabit.Advantage of the present invention is: simple, effective, reliable, low-cost, be fit to high speed data transfer application, the particularly application on network edge node.Device of the present invention and router can be configured to and resemble PPP over SDH ply-yarn drill or the such used equipment compatibility of router easily.The present invention can have more flexibility, and be adapted to better aspect the Internet based on 32 transfer of data and processing.
Below use preferred embodiment, narrated and illustrated principle of the present invention.Clearly, without departing from the spirit and scope of the present invention, on structure and details, can change invention.For example except SDH and SONET, the data transmission device of transmission and/or receive direction and method can be applied to physical layer equipments such as other SDH as simplification, accurate SDH, WDM, Ethernet, and hold other network layer protocol.All these variations and change all should drop in the claims range of definition.

Claims (43)

1. one kind is transferred to the data transmission device of physical layer equipment with packet from network layer device, comprising:
First receiving device is used for receiving from the network layer side apparatus packet of certain type;
SAPI identifier generation device is used for the type of recognition data bag, and produces the SAPI identifier according to the type of identification;
The first framing device is used for encapsulating described data with following form: beginning flag, address field, control field, the SAPI field that contains described SAPI identifier, the information field that comprises described packet, FCS field and end mark, to form first kind frame;
The second framing device is used for described first kind frame is encapsulated into payload part, and inserts suitable expense, forms the second class frame;
First dispensing device is used for the described second class frame is outputed to physical layer side equipment.
2. according to the data transmission device of claim 1, wherein also comprise the frame type indicators generation device, be used to produce the designator of the type of representing described first kind frame, and described frame type indicators is inserted into described address field by the described first framing device.
3. according to the data transmission device of claim 1, wherein said address field is one eight hyte, and described control field is one eight hyte, and described SAPI field is two eight hytes.
4. according to the data transmission device of claim 3, wherein, described SAPI field is " 0x04 " for the Ipv4 bag, is " 0x06 " to the Ipv6 bag, is " 0xff " to PPP associated packet or PPP/HDLC solution.
5. according to the data transmission device of claim 4, wherein, described address field, control field and SAPI field are " 04 03 00 21 " for the Ipv4 bag, to Ipv6 bag is " 04 03 0057 ", is " ff03 0021 " to the Ipv4 bag of PPP/HDLC solution.
6. the data transmission device one of any according to claim 1 to 5 wherein also comprises and realizes X 43+ 1 self-synchronous scrambler, this scrambler comprise 1 XOR gate and 43 bit shift register, and its output code flow and original input code flow are carried out XOR, produce transmission code; Pointer inserts device, is used for inserting at the described first kind frame pointer of indication payload original position; And described first receiving device is a FIFO, is used to receive the packet of importing with buffer memory; Described beginning flag and end mark are " 0x7E "; The described first framing device is carried out interframe and is filled; The described first framing device is carried out the transparency and is handled (filling of eight hytes), and 0x7E is encoded into 0x7D, and 0x5E is encoded into 0x7D with 0x7D, 0x5D; And the described first framing device utilizes generator polynomial 1+x+x 2+ x 4+ x 5+ x 7+ x 8+ x 10+ x 11+ x 12+ x 16+ x 22+ x 23+ x 26+ x 32To all eight hytes in the frame, remove beginning flag, end mark, and outside the FCS field itself, calculate 32 Frame Check Sequence fields.
7. according to the data transmission device of claim 6, wherein said payload part comprises a plurality of payload subdivisions of carrying described first kind frame, and the boundary alignment of the border of described first kind frame and described payload part; And described SAPI generating apparatus obtains SAPI from a FIFO.
8. according to the data transmission set of claim 7, wherein said former frame end mark can be the beginning flag that follows the frame subsequently of this former frame closely.
9. the data transmission set one of any according to claim 1 to 5 wherein also comprises big or small processing unit, has parcel long (mPS) and a maximum bag long (MPS), if the length of input bag, then produces wrong the indication greater than MPS or less than mPS; And the bag loopback apparatus that also comprises the line side, be used for the first kind frame from the extraction of the second class frame is looped back to a FIFO, the purpose that is used to test.
10. according to any one data transmission set in the aforementioned claim, wherein said physical layer is among SDH/SONET, simplification SDH/SONET, PDH (Pseudo-synchronous Digital Hierarchy) and the WDM, described packet from network layer is IPv4, IPv6, IS-IS, PPP information bag or mpeg data stream, each is corresponding with a predefined SAPI value respectively, described first kind frame is the LAPS frame, and the second class frame is the frame of class SDH/SONET; Wherein the DS code-point extracts from network layer data and is used to control the formation algorithm.
11. according to the data transmission set of claim 5, wherein said payload part is the cascade of SDH/SONETSPE virtual container or virtual container.
12. one kind is used for first kind frame is added that suitable expense is packaged into the second class frame and the data transmission set of packet from the physical layer side device transmission to the network layer side apparatus that form, each described first kind frame comprises beginning flag, address field, control field, SAPI field, information field, FCS field and end mark, and this device comprises:
Second receiving system is used for from physical layer side equipment receiving data bag;
Second separates the frame device, is used to remove expense, extracts first kind frame from the payload of the second class frame;
First separates the frame device, is used for extracting SAPI field and the data that are included in the information field from first kind frame;
Judgment device is used for the value with the SAPI field, and the value that presets with a group, comprise first value and second value at least compares, if SAPI field data value and first kind value coupling judge that then the value of extracting is the first kind; If the data value of SAPI field and second class value coupling judge that then the value of extracting is second class;
Second dispensing device, the packet and the court verdict that are used for extracting send to the network layer side apparatus.
13. according to the data transmission device of claim 12, wherein said address field is one eight hyte, described control field is one eight hyte, and described SAPI field is two eight hytes.
14. data transmission device according to claim 13, wherein, described judgment device comprises the frame type recognition device, be used for extracting frame type indicators from described address field, be encapsulated in the type of the first kind frame in the second class frame with identification, if described frame type indicators is " 0x04 ", then the frame that is received is confirmed as the LAPS frame; If frame type indicators is " 0xff ", then the frame that is received is the PPP frame.
15. data transmission device according to claim 14, wherein, described judgment device also comprises the SAPI extraction element, the SAPI field that is used for after being in control field is extracted the SAPI value, if it is " 0x04 " that described frame type recognition device is determined the frame type indicators in the address field, the frame that expression is received is the LAPS frame, then SAPI extraction element 43 turns to two eight hytes of SAPI field, extract the SAPI value, the type of this SAPI value representation packet promptly, is " 0x0021 " for the IPV4 packet, for IPV6 packet or other packet, be " 0x0057 ".If described frame type recognition device is determined frame type indicators in the address field for " 0xff ", and SAPI be " 0021 ", and then the frame of Jie Shouing is confirmed as the PPP frame, and can send and do further PPP processing.
16. data transmission device according to claim 15, wherein, described judgment device is determined to handle to preceding four eight hytes of each first kind frame: address field (one eight hyte), control field (one eight hyte) and SAPI field (two eight hytes) are so that 32 processing, wherein, preceding four eight hytes are " 04 03 00 21 " expression IPV4 bag, " 04 03 00 57 " expression IPV6 bag, the IPV4 bag of " ff 03 00 21 " expression PPP/HDLC solution.
17., wherein also comprise and realize X according to the data transmission device of claim 16 43The descrambler of+1 descrambling, described descrambler comprise 1 XOR gate and 43 bit shift register, and XOR is carried out in the scrambled data position of carry-out bit and input, to produce the position of descrambling; The pointer interpreter device is used for locating the beginning by the first kind frame that is encapsulated into the second class frame of this pointer indication; And described second dispensing device is the 2nd FIFO that is used to receive with packet that buffer memory extracts, and described beginning flag and end mark are " 0x7E "; Described first separates the frame device removes the interframe filling; Described first separates the frame device removes filling process, and with 0x7D, 0x5E is decoded as 0x7E, and with 0x7D, 0x5D is decoded as 0x7D; And
The FCS field that verification receives is by adopting generator polynomial: 1+x+x 2+ x 4+ x 5+ x 7+ x 8+ x 10+ x 11+ x 12+ x 16+ x 22+ x 23+ x 26+ x 32Between beginning flag and end mark to all eight hytes calculate the FCS verification and, and the value of result and FCS field compared, report fcs error as the unequal then network management entity in overall routing engine.
18. according to the data transmission set of claim 17, the SAPI value of wherein said extraction is stored among the 2nd FIFO, and, described the 2nd FIFO has parcel long (mPS) and the longest bag to grow (MPS), if the bag length of input is longer than MPS, or shorter than mPS, then produce a wrong indication.
19. according to the data transmission device of claim 19, wherein the end mark of former frame is the beginning flag immediately following the frame subsequently of this former frame.
20. according to the data transmission set among the claim 12-19 any, wherein said physical layer is among SDH/SONET, simplification SDH/SONET, PDH and the WDM, described first kind frame is the LAPS frame, the second class frame is a class SDH/SONET frame, and the packet that therefrom extracts is IPv4, IPv6, IS-IS, PPP information bag or mpeg data stream.
21. according to the data transmission device of claim 20, also comprise the connection management unit, described connection management unit comprises, timer, is used for monitoring whether no frame time of reception surpasses a preset value; With a counter, be used for the number of times of counter timer when full, if rolling counters forward is to a preset value, then the connection management unit is just judged a connection error, and the report of the network management entity in overall routing engine, wherein said timer preset value is 1 second, and the default preset count value of counter is 3.
22. the data transmission device of a transfer data packets between network layer side apparatus and physical layer side equipment comprises according to data transmission device one of any among the claim 1-11 with according to data transmission device one of any among the 12-21.
23. according to the data transmission set of claim 22, also comprise embedded type CPU, be used to carry out and relate to first kind framing/the separate processing procedure of frame device; And network layer handles device, described network layer handles device comprises a PPP processing unit, judging the address word segment value when described judgment device is 255 and during SAPI=" 0021 ", the packet that i.e. indication receives is the PPP information bag, when needing further to handle, described network processing unit is just carried out PPP (LCP, NCP) processing procedure to the data that transmit from described the 2nd FIFO, or PPP is wrapped signal is sent to overall routing engine.
24. a router device comprises a plurality of ply-yarn drills, and has at least a ply-yarn drill to comprise according to data transmission device one of any among the claim 1-11 with according to data transmission device one of any among the claim 12-21.
25. according to the router of claim 24, wherein said at least one ply-yarn drill also comprises embedded type CPU, is used to carry out relate to first kind framing/the separate processing procedure of frame device; With the network layer handles device, described network layer handles device comprises a PPP processing unit, judging the address word segment value when described judgment device is 255 and during SAPI=" 0021 ", the packet that i.e. indication receives is the PPP information bag, when needing further to handle, described network processing unit is just carried out PPP (LCP, NCP) process to the data that transmit from described the 2nd FIFO, or PPP is wrapped signal is sent to overall routing engine; Overall situation CPU is used for each ply-yarn drill is carried out routing engine and Network Management Function.
26. one kind is transferred to the data transmission method of physical layer side equipment with packet from the network layer side apparatus, comprises the following steps:
Receive the packet of certain type from the network layer side apparatus;
The type of recognition data bag, and according to the type generation SAPI identifier of discerning;
The first framing step, adopting down, column format encapsulates described data: beginning flag, the address field that comprises described SAPI identifier, control field, SAPI field, the information field that comprises described packet, FCS field and end mark field, to form first kind frame;
The second framing step is encapsulated into payload part with described first kind frame, inserts suitable expense, to form the second class frame;
The described second class frame is outputed to physical layer side equipment.
27. data transmission method according to claim 26, comprise also that wherein frame type indicators produces step, be used to produce the designator of the type of representing described first kind frame, and described frame type indicators is inserted into described address field in the described first framing step.
28. according to the data transmission method of claim 27, wherein said address field is one eight hyte, described control field is one eight hyte, and described SAPI field is two eight hytes.
29. according to the data transmission method of claim 28, wherein, described SAPI field is " 0x04 " for the Ipv4 bag, is " 0x06 " to the Ipv6 bag, is " 0xff " to PPP associated packet or PPP/HDLC solution.
30. data transmission method according to claim 29, wherein, described address field, control field and SAPI field are " 04 03 00 21 " for the Ipv4 bag, to Ipv6 bag is " 04 03 0057 ", is " ff 03 0021 " to the Ipv4 bag of PPP/HDLC solution.
31. the data transmission method according to claim 30 also comprises: the first kind frame to transmission is carried out X 43The motor synchronizing scrambler step of+1 scrambler function; And described beginning flag and end mark are that " 0x7E " described first framing step is carried out the interframe filling and transmitted the fifo error recovery; The described first framing step is carried out the transparency and is handled (byte filling), and 0x7E is converted to 0x7D, and 0x5E is converted to 0x7D with 0x7D, 0x5D; And the described first framing step comprises and utilizes generator polynomial 1+x+x 2+ x 4+ x 5+ x 7+ x 8+ x 10+ x 11+ x 12+ x 16+ x 22+ x 23+ x 26+ x 32To all eight hytes in the frame, remove beginning flag, end mark, and outside the FCS field itself, calculate 32 Frame Check Sequences.
32. according to the data transmission method of claim 31, wherein said former frame end mark is the beginning flag that follows the frame subsequently of former frame closely.
33. according to the data transmission method of claim 32, wherein before the input packet was handled, the described input packet of buffer memory carried out rate adapted.
34. according to data transmission method one of any among the claim 26-33, wherein said physical layer is SDH/SONET, simplify one of SDH/SONET, PDH (Pseudo-synchronous Digital Hierarchy) and WDM; Described packet from network layer is IPv4, IPv6, IS-IS, PPP information bag or mpeg data stream, and each corresponds respectively to a predefined SAPI value, and described first kind frame is the LAPS frame, and the second class frame is the frame of class SDH/SONET.
35. one kind adds that as payload suitable expense is encapsulated into the data transmission method of packet from the physical layer side device transmission to the network layer side apparatus that forms in the second class frame with first kind frame, described first kind frame comprises beginning flag, address field, control field, SAPI field, information field, FCS field and end mark, and this method may further comprise the steps:
From physical layer side equipment receiving data bag;
Second separates the frame step, removes expense, extracts first kind frame from the second class frame;
First separates the frame step, extracts SAPI information and the data that are included in the information field from first kind frame;
With the value of SAPI field, the value that presets with a group, comprise first value and second value at least compares, if the SAPI field data value and the first value coupling judge that then the value of extracting is the first kind; If the data value of SAPI field and the second value coupling judge that then the value of extracting is second class;
The packet and the court verdict that extract are sent to network layer device.
36. according to the data transmission method of claim 35, wherein said address field is one eight hyte, described control field is one eight hyte, and described SAPI field is two eight hytes.
37. data transmission method according to claim 36, wherein, described comparison and decision steps comprise the frame type identification step, be used for extracting frame type indicators from described address field, be encapsulated in the type of the first kind frame in the second class frame with identification, if described frame type indicators is " 0x04 ", then the frame that is received is confirmed as the LAPS frame; If frame type indicators is " 0xff ", then the frame that is received is the PPP frame.
38. data transmission method according to claim 37, wherein, described comparison and decision steps also comprise the SAPI extraction step, the SAPI field that is used for after being in control field is extracted the SAPI value, if it is " 0x04 " that described frame type recognition device is determined the frame type indicators in the address field, the frame that expression is received is the LAPS frame, then the SAPI extraction step turns to two eight hytes of SAPI field, extract the SAPI value, the type of this SAPI value representation packet promptly, is " 0x0021 " for the IPV4 packet, for IPV6 packet or other packet, be " 0x0057 ".If described frame type recognition device is determined frame type indicators in the address field for " 0xff ", and SAPI be " 0021 ", and then the frame of Jie Shouing is confirmed as the PPP frame, and can send and do further PPP processing.
39. data transmission method according to claim 38, wherein, described comparison and decision steps are determined to handle to preceding four eight hytes of each first kind frame: address field (one eight hyte), control field (one eight hyte) and SAPI field (two eight hytes) are so that 32 processing, wherein, preceding four eight hytes are " 04 03 00 21 " expression IPV4 bag, " 04 03 00 57 " expression IPV6 bag, the IPV4 bag of " ff 03 00 21 " expression PPP/HDLC solution.
40., wherein also comprise descrambling step execution X according to the data transmission method of claim 39 43+ 1 descrambling produces not scrambled data streams; And described beginning flag and end mark are " 0x7E "; Described first to separate the frame step be to remove interframe to fill; Described first separates the execution of frame step removes filling process, and with 0x7D, 0x5E is decoded as 0x7E, and with 0x7D, 0x5D is decoded as 0x7D; And the FCS field that verification receives is to adopt generator polynomial: 1+x+x 2+ x 4+ x 5+ x 7+ x 8+ x 10+ x 11+ x 12+ x 16+ x 22+ x 23+ x 26+ x 32Between beginning flag and end mark to all eight hytes calculate the FCS verification and.
41. according to the data transmission method of claim 40, wherein the end mark of former frame is the beginning flag immediately following the frame subsequently of this former frame.
42. according to the data transmission method of claim 41, wherein before data were sent to network layer, buffer memory dateout bag was to carry out rate adapted.
43. according to data transmission method one of any among the claim 35-42, wherein said physical layer is one of SDH/SONET, PDH (Pseudo-synchronous Digital Hierarchy) and WDM of SDH/SONET, simplification; Wherein first kind frame is the LAPS frame, and the second class frame is the frame of class SDH/SONET, and the packet of Ti Quing is IPv4, IPv6, IS-IS, PPP information bag or mpeg data stream thus.
CNB011120339A 2001-03-27 2001-03-27 Data transmission device and method between physical layer and network layer Expired - Lifetime CN100479418C (en)

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