CN1149794C - Interfacing apparatus and method for adapting ethernet directly physical channel - Google Patents

Interfacing apparatus and method for adapting ethernet directly physical channel Download PDF

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CN1149794C
CN1149794C CN 00800854 CN00800854A CN1149794C CN 1149794 C CN1149794 C CN 1149794C CN 00800854 CN00800854 CN 00800854 CN 00800854 A CN00800854 A CN 00800854A CN 1149794 C CN1149794 C CN 1149794C
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data transmission
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sdh
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CN1316146A (en )
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余少华
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信息产业部武汉邮电科学研究院
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Abstract

本发明公开了一种直接适配以太网到物理信道的接口装置和方法,该装置和方法采用LAPS将MAC帧封装到SDH/SONET SPE/VC中。 The present invention discloses a method adapted directly to the Ethernet interface device and method for the physical channel, the apparatus and method using LAPS the MAC frame is encapsulated into SDH / SONET SPE / VC of. LAPS封装包括起始标志序列、地址字段(SAPI,服务访问点标识符)、控制字段(0×03)、信息字段(IPv4、IPv6或PPP协议数据单元)、FCS字段(帧校验序列)和结束标志序列。 LAPS package comprises start flag sequence, address field (the SAPI, Service Access Point Identifier), control field (0 × 03), information field (IPv4, IPv6, or PPP protocol data unit), the FCS field (Frame Check Sequence) and It marks the end of the sequence. 标志序列(0×7E)指明LAPS帧的起始/结束。 Flag sequence (0 × 7E) starting / ending specified LAPS frame. 本发明可用于在电信SDH/SONET传输设备上提供以太网接口或设置在数据通信设备如核心和边缘路由器、交换机设备、基于IP的网络接入设备、线卡、接口单元和用于高速情况如Gigabit的接口单元等提供远程接入功能。 The present invention may be used to provide Ethernet interface or provided over a telecommunications SDH / SONET transmission device in a data communication device such as core and edge routers, switch devices, IP based network access equipment, line cards, and a high speed interface unit such as the case providing remote access function Gigabit interface unit and the like. 通过简化SDH/SONET如简化的SDH/SONET,以太网可应用于DWDM。 By simplifying the SDH / SONET simplified as SDH / SONET, Ethernet may be applied to DWDM.

Description

以太网直接与物理信道适配的接口装置和方法 Ethernet interface directly with the devices and methods adapted to the physical channel

技术领域 FIELD

本发明涉及与Internet/Intranet(因特网/内部网)和LAN有关的数据网络和电信网络,特别涉及以太网直接与物理信道适配的接口装置和方法,其在电信SDH/SONET传输设备上提供以太网接口,或为远程接入数据通信设备如核心和边缘路由器、交换设备、基于IP的网络接入设备、线卡以及在高速应用中所采用的接口单元提供例如将MAC帧与SDH/SONET直接适配的功能。 The present invention relates to the Internet / Intranet (Internet / Intranet) and LAN related to telecommunications networks and data networks, and more particularly to apparatus and method for Ethernet interface adapted to the physical channel, which directly provide ether telecom SDH / SONET transmission equipment network interface, or a data communication device for remote access, such as core and edge routers, a switching device, IP-based network access device, and a line card interface unit employed in high-speed applications, for example, the MAC frame to SDH / SONET directly adaptation functions.

背景技术 Background technique

目前需要扩展包括以太网、快速以太网和千兆以太网在内的以太网应用。 Currently we need to extend Ethernet applications, including Ethernet, Fast Ethernet and Gigabit Ethernet, including. 在基于电信的物理信道上传送以太网(由IEEE 802.3工作组定义),以连接专网和公网内的LAN、Internet/Intranet是一种简单、价廉的技术。 Physical channel based on Ethernet telecommunications transmission (defined by the IEEE 802.3 Working Group) to LAN, Internet connection in the public network and private network / Intranet is a simple, inexpensive technique.

ITU-T G.707描述了SDH的优点和复用方法,规定了一组SDH比特率、网络接口节点(NNI)的总则和帧结构、9行N×270列的全部帧大小、分段开销及其字节分配、同步传送模块(STM)的国际互连安排、在NNI单元将元素复用和映射到STM-N的格式。 ITU-T G.707 describes the advantages and SDH multiplexing method specifies a set of SDH bit rate, frame size of all network interface node (the NNI) and the General frame structure of 9 rows N × 270 columns, the overhead segment and the byte allocation, scheduling module international interconnection (STM) transmitted in synchronization, the NNI complex elements mapped in the unit and into STM-N format.

在北美,与SDH对应的是SONET。 In North America and SDH corresponds SONET. SONET是美国(ANSI)的在光介质上同步数据传送标准,简称同步光网络。 SONET is the U.S. (ANSI) synchronous data transmission on optical media standards, referred to as synchronous optical network. 人们制定标准以使数字网络能够实现国际互连,以及已有传输系统能够通过支路设备能够充分利用光介质的优势。 People develop standards so that digital networks can interconnect internationally, as well as the existing transmission system to be able to take advantage of optical media through tributary device. SONET定义了一个速率为51.84Mbps的基本速率、一套在基本速率倍数的光载波级。 SONET defines a basic rate for the rate of 51.84Mbps, Optical Carrier Level set at a multiple of the base rate. SONET是一种八位组同步复用方案,定义了一系列的标准速率和格式。 SONET is a synchronous multiplexing scheme octets, the standard defines a set of rate and format. 尽管名字是光载波,但它并不仅仅限于光学链路,也定义了用于单模光纤、多模光纤以及CATY 75欧姆同轴电缆的电气标准。 Although the optical carrier name, but it is not limited to optical links, also it defines a single mode fiber, multimode fiber, and electrical standards CATY 75-ohm coaxial cable. 传送速率是51.84Mbps的整数倍,它可以用来携带T3/E3位同步信号。 It is an integer multiple of the transmission rate of 51.84Mbps, which can be used to carry T3 / E3 bit synchronization signal. 它也强烈建议采用G.703的E1/E3/E4/T1/E2/T4接口作为IP-over-SDH/SONET的物理层,以方便用户通过LAN接入。 It is also strongly recommended use of G.703 E1 / E3 / E4 / T1 / E2 / T4 interfaces as IP-over-SDH / SONET is a physical layer, to facilitate user access through LAN.

SDH和SONET都提供了用于一系列线速的标准,最大线速为9.953Gbps,实际可能的最大线速约为20Gbps。 SDH and SONET standard provides for a series of wire-speed, maximum line speed is 9.953Gbps, practically possible maximum line speed of about 20Gbps.

现有的将以太网和SDH/SONET组合在一起的数据通信结构用PPP(点到点协议)和HDLC(高级数据链路控制),它在IETF(因特网工程任务组)中被规定为RFC1619。 Existing Ethernet and a data communication structure SDH / SONET combined with PPP (Point to Point Protocol) and HDLC (High Level Data Link Control), which is defined as in RFC1619 IETF (Internet Engineering Task Force). 然而,在将RFC1619应用到以太网/快速以太网/千兆以太网与SDH/SONET的组合时,RFC1619存在以下主要缺陷:(1)整套应用方案没有一个统一的国际标准支持,这造成不同制造商的设备间在专网或公网中互连困难;(2)对于2.5Gb/s及以上速率,硬件转发部分开销太大,用于IP over WDM情况更是如此,因为RFC1919推荐使用LCP(链路控制协议)和魔数(MagicNumber),这两者都十分复杂。 However, in the RFC1619 apply to Ethernet / Fast Ethernet / Gigabit Ethernet combination with SDH / SONET's, RFC1619 following major shortcomings: (1) set of application program does not support a uniform international standards, which result in different manufacturing between devices in the private network provider or public network interconnect difficulties; (2) for 2.5Gb / s and above rate, too costly hardware forwarding part for IP over WDM is particularly true, since the LCP is recommended RFC1919 ( link control protocol) and the magic number (MagicNumber), both of which are very complex.

(3)使用RFC1619时,重发定时器的默认值在PPP中为3秒,这对于高速链路,过于迟钝。 (3) using the RFC1619, the retransmission timer defaults to 3 seconds in PPP, which for high-speed links, too slow. 在具体工程应用中,要求支持2Mb/s(位/秒)到10000Mb/s的速率范围(相差4032倍),因此重发定时器的值应根据线路往返的时延确定。 In particular engineering applications, it is required to support 2Mb / s (bits / sec) to 10000MB / s rate range of (4032-fold difference), and therefore the retransmission timer value should be determined according to the round trip delay line. 但是,这些在RFC1619中都没有作出规定,从而在不同厂商的设备互连时会出现不确定性。 However, these are not provided in RFC1619, so that there will be uncertainty in the interconnect devices from different manufacturers.

(4)LCP有10种配置包(Configuration Packet)、16种事件(Event)和12种动作(action)、及超过130种协议状态,这导致在MII和SDH/SONET间难以实现光分组交换,且费用昂贵。 (4) LCP 10 configurations packet (Configuration Packet), 16 elite event (Event), and 12 kinds of actions (Action), and more than 130 kinds of protocol state, which makes it difficult to realize optical packet switching between the MII and SDH / SONET, and expensive. 为了说明上述情况,表1列出了采用通常PPP over SDH/SONET标准在LCP有限状态机(Finite-State Machine)上的事件和动作。 To illustrate the above, Table 1 shows the usual PPP over SDH / SONET standard LCP events and actions in the finite state machine (Finite-State Machine) is.

(5)IP over SONET/SDH中几乎没有使用PPP的填充字段,但RFC 2615依然保持填充字段。 (5) IP over SONET / SDH almost no padding field used in PPP, RFC 2615 but remains padding field. 此外,该填充字段要求接收端能够区分信息字段和RFC标准定义的填充字段,这样又增加了处理开销。 Furthermore, the field requires filling the receiving end can distinguish between information fields, and padding field defined by RFC standards, which in turn increases the processing overhead.

Ethernet over SDH/SONET(EOS)的最重要的特点是:(a)它既可用于SDH/SONET电信网,也可用于基于以太网的数据通信网。 Ethernet over SDH / SONET (EOS) is the most important features: (a) It can be used for SDH / SONET telecommunication network can also be used for Ethernet-based data communications network.

--带长距离以太网接口的SDH/SONET设备端到端连接;--带SDH/SONET接口的以太网交换机。 - long distance with SDH / SONET device with an Ethernet interface end; - with SDH / SONET Ethernet switch interface.

(b)在SDH/SONET终端用多芯片实现分出/插入(add/drop)10/100M以太网信号。 (B) in the SDH / SONET terminal implemented with a multi-chip drop / insert (add / drop) 10 / 100M Ethernet signal.

(c)可用于前兆路由器的线卡。 (C) a precursor for the router line card.

表1.事件和动作 Table 1. Events and actions

综上所述,现有的以太网和SDH/SONET结合方案复杂、实现起来困难以及费用昂贵、缓慢、不稳定、不适合高速数据传送,特别是千兆速率的应用。 In summary, existing Ethernet and SDH / SONET scheme binding complex, difficult to implement and expensive, slow and unstable, is not suitable for high speed data transfer, in particular Gigabit applications.

发明内容 SUMMARY

因此,本发明的主要目的是提出一种改进的方法和装置,用于提供物理层设备和网络层设备间例如以太网交换机和SDH/SONET网络的点到点连接、全双工、双向同时运行。 Therefore, a primary object of the present invention is to provide an improved method and apparatus for providing a point to point connection between the physical layer device and a network layer devices such as Ethernet switches and SDH / SONET network, the full-duplex, bidirectional run . 本发明提出了一种新的电信SDH/SONET传输设备和远程接入数据通信设备间通信方式,将MAC帧直接适配到SDH/SONET中。 The present invention provides a novel telecommunication between SDH / SONET transmission equipment and data communications equipment remote access communication system, the MAC frame is adapted to directly SDH / SONET in.

为达到上面以及其他的目的,本发明提供一种从上层设备向下层设备传送数据包的数据传输装置,包括:第一接收装置,用于从上层设备接收数据包,将所述数据包转换成第一类帧;第一处理装置,用于将SAPI标识符所指示的数据包的字段和信息字段一起封装到所述第一类帧中,形成第二类帧;第二处理装置,用于将所述第二类帧封装到净荷部分,并且插入相应于所述数据包的适当开销,形成第三类帧;和第一发送装置,用于将所述第三类帧输出到下层设备。 To achieve the above and other objects, the present invention provides a data transmission device from the upper layer to a lower layer means the device transmitting data packets, comprising: a first receiving means for receiving data packets from an upper layer device, the data packet is converted into the first frame; a first processing means for encapsulating data field and the information field of the packet identifier SAPI indicated by the first type of frames together to form a second type of frames; a second processing means for encapsulating the second type frame to the payload portion, and is inserted in an appropriate corresponding overhead of the packet, a third type of frames are formed; and a first transmitting means for outputting the third frame to a lower class device . 其中,所述第一处理装置将所述第二类帧封装成包括起始标志、含SAPI标识符的SAPI字段、控制字段、包括所述数据包的信息字段、FCS字段和结束标志的帧格式。 Wherein the first processing means to the second type of frames includes a start flag package containing SAPI identifiers SAPI field, control field, information field includes a frame format of the data packet, and the FCS field of the end flag .

本发明还提供一种从上层设备向下层设备传送数据包的数据传输方法,包括下列步骤:从所述上层设备接收和缓冲数据包,适配上层设备的速率和下层设备的速率,将该数据包转换成第一类帧;将SAPI标识符所指示的数据包的字段和信息字段一起封装到所述第一类帧中,形成第二类帧;将所述第二类帧封装到净荷部分,并插入所述数据包的适当开销,形成第三类帧;和将所述第三类帧输出到下层设备。 The present invention also provides a method for transmitting data from the upper layer to the lower device packet transfer device, comprising the steps of: receiving from said upper device and the packet buffer, the rate adaptation rate upper and lower equipment device, the data packet into a first type of frames; packaged with the field and the packet information field indicated by the SAPI identifier category to the first frame, a second type of frames; encapsulated payload to the second type of frames section, and inserted into the appropriate packet overhead, forming a third frame type; and the third output frame to the lower class device. 其中,所述第二类帧被封装成包括起始标志、含SAPI标识符的SAPI字段、控制字段、包括所述数据包的信息字段、FCS字段和结束标志的帧格式。 Wherein the second type comprises a frame is encapsulated as a start flag, containing SAPI identifiers SAPI field, control field, information field comprising the data packet, and the FCS field of the frame end flag format.

本发明还提供一种从下层设备向上层设备发送由第一类帧形成的数据包的数据传输装置,包括:第二接收装置,用于从所述下层设备接收数据包;帧解析装置,用于从所述第一类帧中移去开销;第三处理装置,用于从所述第一类帧的净荷部分提取包含在信息字段中的数据和SAPI字段,形成第二类帧;确定装置,用于比较SAPI字段的值与预设值,并且当SAPI字段数据值等于所设定的值时,确定输出实际提取的数据;第四处理装置,用于将所述第二类帧转换成与数据包相应的第三类帧;和第二发送装置,用于将提取的数据包发送到所述上层设备。 The present invention further provides a data transmission apparatus a data packet to the upper layer forming a first type of frames transmitted by the apparatus from the lower apparatus, comprising: a second receiving means for receiving said data packet from the lower layer apparatus; frame analysis means for removing overhead from the first to the category frame; a third processing means for extracting the data contained in the information field and SAPI field from the payload portion of the frame of the first type, forming a second type of frames; determining means for comparing the value with a preset value of the SAPI field, and when the SAPI field data values ​​equal to a set value, determines the actual output of the extracted data; fourth processing means for converting the second type of frames the packet corresponding to the third frame type; and a second transmitting means for transmitting the extracted data packet to the upper layer device. 其中,每个所述第二类帧包括:起始标志、地址字段、控制字段、信息字段、FCS字段和结束标志,所述SAPI字段位于所述地址字段。 Wherein each of the second type of frames comprising: a start flag, address field, control field, information field, the FCS field, and end flag, the address field is located in the SAPI field.

本发明还提供一种从下层设备向上层设备发送由第一类帧形成的数据包的数据传输方法,包括下列步骤:从所述下层设备接收数据包;从所述第一类帧中移去开销;从所述第一类帧的净荷部分提取SAPI字段和包含在信息字段中的数据,形成第二类帧;将SAPI字段的值与预设值进行比较,当SAPI字段数据值等于所设定的值时,确定输出实际提取的数据;将所述第二类帧转换成与所述数据包相应的第三类帧;和将提取的数据包发送到所述上层设备。 The present invention also provides a method for transmitting data packets to an upper layer formed of a first type of frames transmitted by the apparatus from the lower apparatus, comprising the steps of: receiving data from the lower layer packet; first class is removed from the frame overhead; extracting the payload portion from the frames of the first type and data contained in the SAPI field information field, forming a second type of frames; SAPI value with a preset value field is performed by comparing the data value is equal SAPI field when the set value, determines the actual output the extracted data; converting the second type of frames corresponding to the data packet with a third type of frames; and the extracted data packet to the upper layer device. 其中,每个所述第二类帧包括:起始标志、地址字段、控制字段、信息字段、FCS字段和结束标志,所述SAPI字段位于所述地址字段。 Wherein each of the second type of frames comprising: a start flag, address field, control field, information field, the FCS field, and end flag, the address field is located in the SAPI field.

本发明还提供一种在上层设备和下层设备之间发送数据包的数据包接口装置,包括根据上述的数据传输装置和根据上述的数据传输装置。 The present invention also provides a packet interface means for transmitting data packets between the upper device and the lower device, comprising the said data transmission means and said data transmission apparatus according to. 其中所述第二类帧被封装成包括起始标志、含SAPI标识符的SAPI字段、控制字段、包括所述数据包的信息字段、FCS字段和结束标志的帧格式。 Wherein the second type comprises a frame is encapsulated as a start flag, SAPI identifiers SAPI field contains, control field, information field comprising the data packet, and the FCS field of the frame end flag format. 其中还包括:微处理器接口装置,用于使所述数据接口装置能接入其内的所有寄存器;用于测试的JTAG端口;用于暂时缓冲输入/输出配置数据的GPIO寄存器。 Further comprising: a microprocessor interface means, for causing said data interface means can access all registers therein; a JTAG test port; for temporarily buffering the input / output configuration data of the GPIO registers.

通过参照附图对本发明实施例的详细描述,本发明的其他方面和优点将变得更加清楚。 DRAWINGS The detailed description of embodiments of the present invention, other aspects and advantages of the present invention will become more apparent.

附图说明 BRIEF DESCRIPTION

通过参照附图的如下详细说明,不难理解本项发明:图1所示为本发明Ethernet over LAPS的总的示意图,它提供点到点、全双工、同时双向运行,图中采用了以太网帧、LAPS和SDH间的关系来表示。 By the following detailed description with reference to the accompanying drawings easy to understand the present invention of which: Figure 1 is a schematic view of the overall Ethernet over LAPS the present invention is shown, which provide point to point full duplex simultaneous two-way operation, the ether used in FIG. the relationship between the network frame, LAPS and SDH are represented.

图2所示为STM-N中的Ethernet over LAPS的层/协议栈。 Figure 2 is a STM-N in the Ethernet over LAPS layer / protocol stack.

图3为sSTM中的Ethernet over LAPS的层/协议栈。 3 is sSTM the Ethernet over LAPS layer / protocol stack.

图4为本发明的LAPS帧格式。 FIG 4 is a LAPS frame format of the invention.

图5为Etbernet over LAPS的示例性协议配置。 FIG 5 is a configuration example of Etbernet over LAPS protocol.

图6为根据本发明在Ethernet over LAPS中的协调子层/MII和LAPS/SDH间的关系。 FIG 6 is a relationship between / MII and LAPS / SDH according to the present invention, the Reconciliation sublayer of Ethernet over LAPS.

图7所示为本发明实现千兆以太网和SDH适配的功能单元的示例性配置。 Figure 7 shows an exemplary configuration of functional means implemented Gigabit Ethernet and SDH adapted to the present invention.

图8所示为MAC、LAPS链路层和物理层间的原语关系。 Figure 8 shows the relationship between the primitive MAC, LAPS link layer and physical layer.

图9所示根据本发明实施例用于将MAC帧直接与SDH/SONET适配或简化SDH/SONET的Ethernet over SDH/SONET接口装置框图。 As shown in FIG. 9 embodiment according to the present invention will be directly related to the MAC frame SDH / SONET or adaptation SDH / SONET the Ethernet over SDH / SONET interfaces simplified block diagram of apparatus.

图10所示为IEEE 802.3以太网MAC帧格式的示意图图,图中在阴影部分定义LAPS信息字段格式。 FIG. 10 is a schematic diagram of an Ethernet IEEE 802.3 MAC frame format, in the hatched portion in FIG LAPS defined information field format.

图11所示为封装MAC字段后的LAPS帧格式。 Figure 11 is a LAPS frame format of the encapsulated MAC field.

图12A所示为STM-N的SPE/VC结构实例。 FIG. 12A shows the STM-N SPE / VC structure instance.

图12B所示为SONET和SDH的POH示意图。 FIG. 12B is a schematic diagram of the SONET and SDH POH.

图12C所示为STS-3c SPE或VC-4结构示意图。 Figure 12C is a STS-3c SPE or VC-4 a schematic structural diagram.

图13所示为图9中转换器19的详细方框图。 FIG 13 is a detailed block diagram in FIG. 9 of the converter 19.

图14所示为带2个EOS端口的以太网2层交换机的示意图。 Layer 2 Ethernet switch with two ports schematic EOS 14 shown in FIG.

图15所示为根据本发明实施例的SDH专用网连接带EOS装置的10BASE-T和100BASE-T2层交换机、1000BASE-x交换机的示意图。 FIG 15 10BASE-T and 100BASE-T2 layer switch means connected with EOS, a schematic diagram is shown SDH private network according to an embodiment of the present invention, the switch 1000BASE-x.

图16所示为根据本发明实施例的SDH公网连接IEEE 802.3以太网3层交换机的示意图。 Figure 16 shows the SDH public network according to embodiments of the present invention, a schematic view of IEEE 802.3 Ethernet Layer 3 switches connected.

具体实施方式 detailed description

下面参考所附附图,对本发明优选实施例予以详细说明。 Referring to the accompanying drawings, preferred embodiments of the present invention to be described in detail. 在下面的说明中,对于那些众所周知的功能或结构将不进行详细的说明,以免以不必要的细节掩盖本发明。 In the following description, those well-known functions or constructions will not be described in detail so as not to obscure the present invention with unnecessary detail.

本发明将以太网适配到SDH/SONET或简化SDH/SONET网络。 The present invention is adapted to the Ethernet SDH / SONET or simplified SDH / SONET network. 连接以太网交换机和SDH/SONET网络是提供Ethernet over WAN的十分吸引人的方式。 Connecting Ethernet switches and SDH / SONET network to provide a very attractive way of Ethernet over WAN. 连接一个或多个以太网交换机端口对以太网是透明的。 Connecting one or more Ethernet ports on Ethernet Switch is transparent.

为清楚起见,下面给出本说明和附图所采用的缩写。 For clarity, given the abbreviation used in the present description and drawings below.

AUI 附件单元接口FCS 帧校验序列GMII 千兆位介质独立接口IPX 因特网包交换LAPS SDH链路接入规程LAN 局域网LLC 逻辑链路控制MAC 介质接入控制MAU 介质附属单元MDI 介质相关接口MII 介质独立接口SDH 同步数字体系STM 同步传送模块sSTM 同步传送模块子模块 Attachment Unit Interface AUI frame check sequence FCS GMII Gigabit Media Independent Interface Internet packet exchange IPX LAPS SDH Link Access Procedure LAN Local Area Network LLC Logical Link Control MAC Medium Access Control accessory unit MAU media dependent interface MDI MII media independent media SDH synchronous transport module Interface sSTM synchronous digital hierarchy STM synchronous transport module submodule

VC 虚容器SAPI 业务接入点标识符PLS 物理层信令PCS 物理编码子层PMA 物理介质附件PHY 物理层设备PMD 物理介质相关UITS 否定应答信息传送业务HDLC 高级数据链路控制SPE 同步净荷包络(envelope)TCP 传输控制协议UDP 用户数据报协议图1为本发明Ethernet over LAPS总体方案示意图,它提供点到点、全双工、同时双向运行,它采用以太网帧、LAPS和SDH间的关系来描述。 Virtual container VC SAPI Service Access Point Identifier PLS physical layer signaling physical coding sublayer PCS PMA Physical Medium Attachment physical layer device PHY Physical Medium Dependent PMD UITS negative acknowledge information transfer service level data link control HDLC synchronous payload envelope SPE (envelope) TCP transmission control protocol UDP user datagram protocol Figure 1 is a schematic view of the overall program Ethernet over LAPS invention, which provides point to point full duplex simultaneous two-way operation, which uses the relationship between the Ethernet frame, the LAPS and SDH to describe.

如图1所示,LAPS用在802.3(802.3u/802.3z分别代表以太网/快速以太网/千兆以太网)链路层和MAC子层之间,物理层定义为包括各种高阶和低阶VC的SDH,第二层由三个子层组成:LLC/MAC/LAPS。 1, with the LAPS between 802.3 (802.3u / 802.3z represent Ethernet / Fast Ethernet / Gigabit Ethernet) link layer and the MAC sublayer, the physical layer is defined to include various higher order and the lower order VC SDH, the second layer is composed of three sub-layers: LLC / MAC / LAPS. LAPS是一种典型的HDLC,包括数据链路业务和协议规范,它们已被用于采用LAPS的IPover SDH。 LAPS is a typical the HDLC, including data link traffic and protocol specification, they have been adopted for the LAPS IPover SDH.

在这种结构中,只有一个由LAPS链路层提供给MAC子层、供以太网/快速以太网/千兆以太网的MAC帧使用的接入点。 In this configuration, only by a LAPS link layer to the MAC sub-layer for Ethernet / Fast Ethernet / Gigabit Ethernet MAC frame used in the access point. 例如SAPI是“28(十进制)”。 E.g. SAPI is "28 (decimal)." 在MAC子层的整个MAC帧,在传送时,作为原语的参数被映射到LAPS链路层。 Throughout the MAC sublayer of the MAC frame, when transmitted is mapped to a link layer as a parameter LAPS primitive. 在LAPS子层,把映射的MAC帧看作是没有改变它们的大小和序列的LAPS信息字段(它包括目的地地址、源地址、长度/类型、MAC客户数据、PAD字段(如有的话)和完整MAC帧的FCS字段)。 In LAPS sublayer maps the MAC frame is not considered to change the information field LAPS their size and sequence (which includes a destination address, source address, length / type, MAC client data, the PAD field (if any) complete and FCS field of the MAC frame). LAPS链路层适配UITS,采用原语和参数通过相应业务接入点与SDH物理层进行交互。 LAPS link layer adaptation UITS, using primitives and parameters by interacting with the corresponding service access point SDH physical layer.

LAPS是一种物理编码子层,通过SDH虚容器和接口速率提供点到点传送。 LAPS is a physical coding sublayer, provides point SDH virtual containers and transmitted via the interface rate. 所支持的UITS是无连接模式业务。 Supported UITS is a connectionless mode service. 在LAPS和SDH间采用速率适配。 Using rate adaptation between LAPS and SDH. 它提供一种调节以太网MAC MII速率到SDH VC速率的机制,由于SDH和MAC分别以周期性和突发性方式运行,它也阻止进入SDH VC的MAC帧被写到SDH开销。 It provides an adjustable rate to a mechanism for the MII Ethernet MAC SDH rate of the VC, since the SDH and MAC are operating in a periodic and unexpected manner, it can also block access to the VC SDH MAC frame is written to the SDH overhead. 另一方面,也可在LAPS子层和协调子层之间采用速率适配。 On the other hand, may be employed between the rate adaptation LAPS Reconciliation sublayer and the sublayer.

SDH传送被看作是一种面向八位组的同步点到点全双工链路。 SDH synchronous transmission is viewed as a point to point full duplex link octet oriented. SDH帧是一种面向八位组的同步复用映射结构,它规定了一系列的标准速率、格式、和映射方法。 SDH frame is an octet-oriented synchronous multiplexing and mapping structure, which provides a standard set of rates, formats, and mapping methods. 表2所示为VC的带宽值,表3为目前规定的STM接口速率。 Table 2 shows the bandwidth value VC, Table 3 interface rate STM predetermined current. 无需使用控制信号。 Without using a control signal. 在向同步净荷包络中插入或从中提取信息期间,使用自同步扰码/解扰(X11+1)函数。 During insertion or extraction of information from the synchronous payload envelope, a self-synchronizing scrambling / descrambling (X11 + 1) function.

表2.SDH虚容器带宽 Table 2.SDH bandwidth of the virtual container

表3.STM接口速率 Table 3.STM interface rate

SONET传送速率是是STS-1(51.840Mbps)的整数倍,下面是SONET目前使用的倍率:STS-1:51.840MbpsSTS-3:155.520MbpsSTS-9:466.560MbpsSTS-12:622.080MbpsSTS-18:933.120MbpsSTS-24:1244.160MbpsSTS-36:1866.240MbpsSTS-48:2488.320MbpsSTS-192:9953.280Mbps图2所示为STM-N中的Ethernet over LAPS的层/协议栈。 SONET transmission rate is a STS-1 (51.840Mbps) integer multiple SONET rate following is currently used: STS-1: 51.840MbpsSTS-3: 155.520MbpsSTS-9: 466.560MbpsSTS-12: 622.080MbpsSTS-18: 933.120MbpsSTS -24: 1244.160MbpsSTS-36: 1866.240MbpsSTS-48: 2488.320MbpsSTS-192: 9953.280Mbps shown in FIG. 2 is a STM-N in the Ethernet over LAPS layer / protocol stack. 在LAPS下方,有两种方式置入VC:(1)把LAPS帧置入低阶VC,根据SDH复用结构通过八位组交错将低阶VC复用到高阶VC,以复用段、再生段和电/光/无线电段顺序传送,然后,在接收端以相反顺序提取LAPS帧;(2)将LAPS帧置入SPE,SPE直接映射到高价VC,以复用段、再生段和电/光/无线电段顺序传送,然后,在接收端以相反顺序提取LAPS帧;图3为sSTM中的Ethernet over LAPS的层/协议栈。 LAPS below, there are two ways into VC: (1) the LAPS frame into lower order VC, VC lower order octet interleaving the multiplexed higher order VC according to SDH multiplex structure through to the multiplexing section, regenerator and electrical / optical / radio section transmission sequence, then the receiving end in the reverse order to extract frames LAPS; (2) into the LAPS frame SPE, SPE is mapped directly to the high VC, to multiplexing section, regenerator and power / optical / radio section transmission sequence, and then, at the receiving end to extract the reverse order LAPS frame; FIG. 3 is a sSTM the Ethernet over LAPS layer / protocol stack. 在这种情况下,将LAPS帧置入低阶VC(VC11、VC12和VC2),根据SDH子复用结构通过八位组交错将低阶VC复用到子复用段,随后以再生段和电/光/无线电段顺序传送它们,然后在接收端以相反顺序提取LAPS帧;图4为本发明的LAPS帧格式。 In this case, a LAPS frame dropping lower order VC (VC11, VC12 and VC2 of), according to the SDH multiplex structure by the sub-octets multiplexed lower order VC used interleaving sub-multiplex section, regenerator and subsequently electrical / optical / radio section sequentially transmit them, then at the receiving end to extract the reverse order LAPS frame; LAPS frame format of FIG 4 of the present invention. 如图4所示,LAPS包封由起始标志序列、地址字段(SAPI,业务接入点标识符)、控制字段(0x03)、信息字段(IPv4、IPv6或PPP协议数据单元)、FCS(帧校验序列)和帧结束标志序列,标志序列(0x7E)确定LAPS帧的起始和结束。 4, the LAPS encapsulation by the start flag sequence, address field (the SAPI, Service Access Point Identifier), control field (0x03), Information field (IPv4, IPv6, or PPP protocol data unit), the FCS (Frame check sequence) and the frame end flag sequence, a flag sequence (0x7E) determining the start and end LAPS frame.

图5为Ethernet over LAPS的示例性协议配置。 FIG 5 is a configuration example of Ethernet over LAPS protocol. 在这种情况下,一个以太网接口通过SDH接入另外一个以太网接口的输入/输出网关。 In this case, an access to another Ethernet interface Ethernet interface input / output gateway by SDH. 网关上设置两种类型的SDH和MAC物理接口,网络层维持不变,仍然是IPv4/IPv6/IPX。 And setting two types of MAC SDH physical interface, a network layer gateway unchanged, still IPv4 / IPv6 / IPX.

图6为根据本发明在Ethernet over LAPS中的协调子层/MII和LAPS/SDH间的关系。 FIG 6 is a relationship between / MII and LAPS / SDH according to the present invention, the Reconciliation sublayer of Ethernet over LAPS. 在这种情况下,在MAC功能子层下面,设置以太网快/速以太网/千兆以太网三种类型的物理接口,在SDH端通过LAPS实现MAC子层和SDH物理层的适配。 In this case, the MAC sublayer functional below, is provided fast Ethernet / Speed ​​Ethernet / Gigabit Ethernet three types of physical interface, the adaptation sub-layer and the MAC SDH physical layer by the SDH LAPS end.

LAPS链路实体通过协调子层和等价的MII(介质独立接口)从MAC层接收帧,这里没有地址过滤功能,LAPS和MAC的FCS计算分别参考ITU-T建议X.85/Y.1321和IEEE 802.3标准。 LAPS link entity through the Reconciliation sublayer and equivalent the MII (media independent interface) frame received from the MAC layer, there is no address filtering function, and MAC FCS calculation LAPS each reference ITU-T Recommendation X.85 / Y.1321 and IEEE 802.3 standard. Ethernet over LAPS的功能单元将所有输入的LAPS信息字段转发到除了源链路端口外的其对等连接链路,在转发前将一个或多个输入帧进入缓冲器。 Ethernet over LAPS functional units LAPS forward all information fields and other input is connected to its link source link in addition to the port, before forwarding one or more input frames into the buffer.

图7所示为根据本发明实施例实现千兆以太网与SDH的适配的功能单元的示例性配置。 Figure 7 shows an embodiment Gigabit Ethernet and SDH exemplary configuration of the function unit adapted in accordance with the present invention. 如图所示,只采用全双工方式。 As shown, the only full-duplex mode. 图中说明了IEEE 802.3以太网连同LAPS/SDH的功能单元。 FIG Ethernet IEEE 802.3 is illustrated in conjunction with LAPS / SDH functional unit. 在SDH端,实现MAC子层和SDH物理层的适配,千兆以太网提供双电缆或4电缆接口、单模光纤接口、多模光纤接口和非掩蔽双绞线接口。 In SDH end, adapted to achieve the MAC sublayer and the physical layer of the SDH, Gigabit Ethernet provides a dual cable or cable connector 4, the single-mode optical fiber interface, a multimode optical fiber interface and a non masked twisted pair interface.

图8所示为MAC、LAPS链路层和物理层间的原语关系。 Figure 8 shows the relationship between the primitive MAC, LAPS link layer and physical layer. 图中,LAPS提供一个SAP,值为28(十进制)的SAPI(服务访问点标识符)用于以太网/快速以太网/千兆以太网。 FIG, LAPS a SAP, a value of 28 (decimal) the SAPI (Service Access Point Identifier) ​​for Ethernet / Fast Ethernet / Gigabit Ethernet. 原语“DL_UNACK_ACK request”用于从MAC层发送MAC帧到LAPS链路层,原语“DL_UNACK_DATA indication” 用于从LAPS链路层接收数据包到MAC链路层。 Primitive "DL_UNACK_ACK request" for transmitting the MAC frame to the link layer from the MAC layer LAPS, primitive "DL_UNACK_DATA indication" for receiving a data packet from the link layer to the MAC LAPS link layer. 在LAPS链路层和物理层之间,原语“PH_DATA request”用于建立从LAPS到物理层的链路,原语“PH_DATAindication”表示从物理层向LAPS链路发送用于链路建立的命令;原语“PH_DATA request”用于从LAPS链路层发送数据包到物理层,而原语“PH_DATA indication”用来从物理层接收数据包到LAPS链路层。 LAPS between the link layer and the physical layer, primitive "PH_DATA request" from the LAPS for establishing a link to the physical layer, primitive "PH_DATAindication" represents the LAPS link transmission command for link establishment from the physical layer ; primitive "PH_DATA request" for data packet transmission from the LAPS link layer to the physical layer, the primitive "PH_DATA indication" to the data packet received from the physical layer to the link layer LAPS.

图9所示为根据本发明实施例的Ethernet over SDH/SONET中将MAC帧直接与SDH/SONET或简化SDH/SONET适配的接口装置框图。 Figure 9 shows the embodiment of the Ethernet over SDH embodiment of the present invention / SONET frame in the MAC SDH / SONET interfaces a block diagram of apparatus adapted to the SDH / SONET directly or simplified. 本发明的Ethernet over SDH/SONET接口装置(在下文中简写为EOS装置)可设置在电信SDH/SONET传输设备中以提供以太网接口,或设置在远程接入数据通信设备中,以提供155M、622M、2.5Gbps或10G的以太网接口,甚至连接在电信SDH/SONET传输设备和远程接入数据通信设备之间,以直接适配MAC帧到SDH/SONET。 The present invention Ethernet over SDH / SONET interface device (hereinafter abbreviated as EOS device) may be provided in the telecommunication SDH / SONET transmission device to provide Ethernet interface, or a remote access is provided data communication apparatus to provide 155M, 622M , 2.5Gbps or 10G Ethernet interface, or even a connection between the telecommunications SDH / SONET transmission device and a remote access to the data communication apparatus, adapted to direct MAC frames to SDH / SONET.

EOS装置在传送和接收两个方向执行标准的STS-3c/STM-1处理。 EOS means two transmission and reception directions to perform standard STS-3c / STM-1 processing.

在发送方向,以太网速率被适配到SDH/SONET速率,MII帧转换成LAPS帧,LAPS帧封装到SDH/SONET SPE/VC中。 In the transmit direction, is adapted to Ethernet speed SDH / SONET rate, converted into a MII frame LAPS frame, LAPS frame is encapsulated into SDH / SONET SPE / VC of. 插入POH和TOH/SOH,所得到的STS信号以八位组宽传送到并行/串行转换器,然后通过线路端接口传送到光纤收发器。 Inserting POH and TOH / SOH, STS resulting signal is transmitted to octet wide parallel / serial converter, and then transmitted to the optical transceiver through the line side interface.

如图9所示,在发送方向,EOS装置1包括:发送(TX)FIFO 8,用来接收和缓冲来自以太网端的数据包(如IPv4或IPv6包、或PPP包、MPEG包、语音包以及其他数据包),将MII速率适配到LAPS的速率,例如适配并行突发的100M MII帧到周期性的155M LAPS帧;TX LAPS处理单元7,用于根据图4所示的格式将SAPI和数据包封装到LAPS帧中;扰码单元6,用来对LAPS帧进行扰码;SPE/VC生成单元5,用于产生指示SPE/VC位置的指针;SDH开销插入单元4,用来插入开销;TX SDH/SONET成帧器3,用来将扰码后的LAPS帧封装到SDH/SONET帧的SPE/VC中,形成SDH/SONET帧。 Shown, in the transmit direction, the EOS device in FIG. 91 comprises: transmitting (TX) FIFO 8, for receiving and buffering data packets from the Ethernet terminal (e.g., IPv4 or IPv6 packets or PPP packets, MPEG packets, and voice packets other data packet), the MII to the rate adaptation rate of LAPS, for example, a parallel adapter frame to the MII burst 100M 155M periodic LAPS frame; LAPS the TX processing unit 7, according to the format shown in FIG. 4 SAPI and the encapsulated data packet to the LAPS frame; scrambling unit 6, it is used to scramble LAPS frame; SPE / VC generating unit 5 for generating a pointer indicative of SPE / VC position; the SDH overhead insertion unit 4, for insertion cost; the TX SDH / SONET framer 3, for the scrambling code after LAPS frame is encapsulated into SDH / SONET frames SPE / VC to form a SDH / SONET frame.

在接收方向,其处理过程与此相反。 In the receive direction, which is opposite to this process. 接收八位组宽的STS信号,Ethernetover SDH/SONET的接口装置给帧和TOH/SOH定位,解释指针,终止TOH/SOH和POH,提取SPE/VC4,然后从SPE/VC4净荷中提取出LAPS帧。 Receiving octet wide STS signal, Ethernetover SDH / SONET frames to the interface means and TOH / SOH positioned, the pointer interpretation, termination TOH / SOH and POH, extraction SPE / VC4, and then extracted from the LAPS SPE / VC4 payload frame. SONET/SDH处理器由一个接收SONET/SDH处理器和一个发送SONET/SDH处理器组成。 SONET / SDH processor of a received SONET / SDH processor and transmitting a SONET / SDH processors.

图9中,在接收方向,EOS装置1包括:接收(RX)帧解析器(deframer)9,用于对接收到的SDH/SONET帧进行解析;SDH开销提取单元16,用来移去SDH/SONET帧的开销;指针处理单元10,用来定位和解释指针,提取SPE/VC4,从SPE/VC4分离出LAPS帧;解扰单元11,用于对提取的LAPS帧进行解扰;接收处理单元12,用于对LAPS帧进行帧解析,抽取封装在LAPS帧中的SAPI和数据包;接收FIFO 13,用于缓冲数据包,确定SAPI,将LAPS速率适配到MII的速率,例如,将周期性的155M的LAPS帧适配到并行突发的100M MII帧,发送数据包如IP包以及SAPI。 9, in the receive direction, the EOS device 1 comprising: a receive (RX) frame parsers (deframer) 9, for the received SDH / SONET frame parsing; SDH overhead extraction unit 16 for removing SDH / overhead of the SONET frame; pointer processing unit 10, for positioning the pointer interpretation and extracted SPE / VC4, LAPS frame separated from SPE / VC4; descrambling unit 11, configured to descramble LAPS frame extraction; reception processing unit 12, for LAPS frames analyzing the frame, extracts the encapsulated data packet and SAPI LAPS frame; receiving FIFO 13, for buffering the data packet, determining SAPI, adapting the rate to a rate of MII LAPS, for example, the period of the 155M to 100M MII LAPS frame adaptation parallel burst frame, the data packet as an IP packet transmission and SAPI. EOS装置1还包括:用于监控TOH/SOH字节在各种状态的错误变化情况的SDH开销监控单元14;和监控POH字节在各种状态的错误变化情况的POH监控单元15。 EOS device 1 further comprising: a monitoring unit for monitoring the SDH overhead TOH / SOH bytes various changes state error 14; and the monitoring unit monitoring POH POH bytes of error changes in the various states 15.

接收处理单元中设置的确定单元(未示出)用来确定接收到的数据包的类型,生成一个相应的预定SAPI,校验发生在帧中的错误。 Determination means provided in the reception processing unit (not shown) for determining the type of the received packet, generates a corresponding predetermined the SAPI, parity error has occurred in the frame.

此外,EOS装置1还包括:转换器19,它使上层设备的数据包与输入到第一接收装置的输入数据包在发送方向同步,以及使从第二发送装置中提取的数据包与上层设备的的数据包在接收方向同步;线路端接口2,用于通过TX线路发送SDH/SONET帧到外围SDH/SONET支持设备,如O/E模块(未示出),以及通过RX线路接收SDH/SONET帧;微处理器I/F(接口)18,它能够使EOS装置1接入其中的所有寄存器;用于测试的JTAG端口12;以及用于临时缓冲输入/输出包的通用输入输出(GPIO)寄存器21。 Furthermore, the EOS device 1 further comprising: a converter 19, which enables the upper layer packet and input to the input device receiving a first packet in synchronous transmission direction means, and causing the second transmission means from the extracted data packets in the upper layer device synchronization of data packets in the receive direction; line end interface 2, a frame transmitting circuit TX via SDH / SONET to the peripheral SDH / SONET support apparatus, such as O / E module (not shown), and received by the RX-line SDH / SONET frame; a microprocessor I / F (interface) 18, it is possible to access all the EOS device 1 registers therein; a JTAG test port 12; and a general purpose input output temporarily buffering the input / output packet (GPIO ) register 21.

EOS装置的主要功能是:●处理SDH/SONET段、线和通道层的信源和信宿,在发送和接收方向均有传送/分段E1、E2、F1和D1-D12开销接口。 The main function of EOS means that: ● processing SDH / SONET section, the source line and the channel layer and a sink, both transmission / sections E1, E2 in the transmit and receive directions, F1, and D1-D12 cost of the interface.

●通过以全双工映射LAPS帧到SDH/SONET或简化SDH/SONET净荷,实现STS-48c/STM-16或STS-12c/STM-4或STS-3c/STM-1数据流的处理。 ● LAPS frame by the full duplex mapped to SDH / SONET or simplified SDH / SONET payload, the processing implemented STS-48c / STM-16 or STS-12c / STM-4 or STS-3c / STM-1 data streams.

●用LAPS的多项式(X43+1)实现自同步扰码器/解扰器。 ● polynomial of LAPS (X43 + 1) to achieve self-synchronizing scrambler / descrambler.

●提供一个MII接口。 ● provides a MII interface.

●提供用于控制、配置和状态监控的8位或16位微处理器接口。 ● providing 8-bit or 16-bit microprocessor interface is used to control, configuration and status monitoring.

●LAPS处理与ITU-T建议X.86兼容。 ● LAPS deal with ITU-T Recommendation X.86-compatible.

●兼容SDH/SONET规范如ANSI T1.105、Bellcore GR-253-CORE和ITUG.707。 ● compatible with SDH / SONET specification as ANSI T1.105, Bellcore GR-253-CORE and ITUG.707.

●提供IEEE 1149.1 JTAG测试端口。 ● provide IEEE 1149.1 JTAG test port.

●支持用于诊断的内环回通道测试。 ● support channel loopback test for diagnosis.

●提供一个8位通用I/O(GPIO)寄存器。 ● providing an 8-bit general-purpose I / O (GPIO) register.

下面是本发明接口装置的接收和发送处理的详细说明。 The following is a detailed description of the receive and transmit processing of the interface apparatus of the present invention. 在随后的说明中,相关功能或操作以及功能块或单元能以可执行程序或硬件形式实现。 In the following description, the operations and related functions, or functional blocks or units can be implemented in hardware or in the form of an executable program. 它们将被省略,以避免对本发明主要方面的不必要的混淆。 They will be omitted to avoid unnecessarily obscuring the main aspect of the present invention.

接收SDH/SONET处理RX帧解析器9的功能相当一个SDH/SONET接收处理器。 Receiving SDH / SONET frame parser 9 RX processing function equivalent to a SDH / SONET receive processor. SDH/SONET接收处理器用于实现STS信号的成帧、解扰、包括B1和B2监控在内的TOH/SOH监控、AIS检测、指针处理、以及POH监控。 Framed SDH / SONET STS implement a processor for receiving a signal, descrambling, comprising B1 and B2 monitor including TOH / SOH monitor, the AIS detecting, pointer processing, and POH monitor. 接收SDH/SONET处理器执行以下功能: Receiving SDH / SONET processor to perform the following functions:

●SDH/SONET成帧,检测[A1 A1 A2 A2]字节,这些字节将用于成帧,提供OOF和LOF指示符(单事件和第二事件,single event and second event)。 ● SDH / SONET framing detection [A1 A1 A2 A2] bytes, which will be used for framing, to provide an indicator LOF and OOF (single event and a second event, single event and second event).

●用SDH/SONET帧同步扰码器对净荷进行扰码,扰码多项式为(X7+X6+1)。 ● using SDH / SONET frame synchronous scrambler scrambling the payload scrambler polynomial (X7 + X6 + 1).

●监控输入的B1字节,将其与重计算出的BIP-8值相比较。 ● monitoring byte B1 input, which is compared with the BIP-8 value recomputed. 提供错误事件信息,包括单个位错误、错误帧和错误时间(Errored Second)的计数。 Providing an error event information includes a count of single-bit errors, frame errors, and time error (Errored Second) of.

●监控输入的B2字节,将其与重计算出的BIP-86/24值相比较。 ● monitoring B2 bytes of the input, which is compared with / 24 weight value computed BIP-86. 提供错误事件信息,包括单个位错误、错误帧和错误时间的计数。 Providing an error event information includes a count of single-bit errors, frame errors, and error time.

●监控K1和K2字节,K1和K2用于发送线路/MS AIS或RDI,以及用于APS发信。 ● monitoring K1 and K2 bytes, K1 and K2 line for transmitting / MS AIS or RDI, and for APS signaling.

●监控接收到的S1字节的4个LSB,以找出后续帧的一致值。 ● monitoring S1 byte received four LSB, to find the same value for subsequent frames.

●监控M1字节,用于确定由远程终端在其接收到的信号中探测到的B2错误数。 ● monitoring M1 byte, B2 for determining the number of errors detected in the signals it receives from the remote terminal.

●TOH/SOH分离(drop)块输出接收到的E1、F1和E2字节以及2个串行DCC信道、SDCC(D1-D3)和LDCC(D4-D12)。 ● TOH / SOH separation (drop) block outputs the received E1, F1 and E2, and two serial bytes DCC channels, SDCC (D1-D3) and LDCC (D4-D12).

●指针状态确定包括检查H1-H2字节,以建立接收指针的状态(正常、LOP、AIS)。 ● state determination comprises checking the pointer H1-H2 bytes, the pointer to establish the status of the received (normal, LOP, AIS). 如果指针状态正常,则读取第一个H1H2字节以确定SPE/VC的开始。 If the pointer is normal, then reads the first byte to determine the start H1H2 SPE / VC's.

●POH监控模块由J1、B3、C2和G1监控组成,这些POH字节用来监控状态的错误或变化。 ● monitoring module by the POH J1, B3, C2 and G1 monitoring composition, the POH bytes for error or status change monitor.

●监控/捕获J1字节,在SONET应用中,捕获64个连续的J1字节,在SDH应用中,EOS装置查找重复的16个连续的J1字节模式。 ● monitoring / capture J1 byte in the SONET applications, the capture of consecutive 64 byte J1 in the SDH applications, the EOS device 16 find duplicate consecutive J1 byte pattern.

●监控C2字节,以校验周期的分机类型。 ● monitoring the C2 byte to verify cycle extension type. 检查分支以找出具有相同C2字节的5个连续帧。 Check branch to find five consecutive C2 frames have the same byte.

●监控REI-P和RDI-P的G1。 ● monitoring REI-P and RDI-P of G1.

●监控输入的B3字节,将其与再计算出的BIP-8值进行比较。 ● B3 byte input monitoring, which is compared with the BIP-8 value is recalculated. 提供错误事件信息,包括单个位错误、错误帧和错误时间的计数。 Providing an error event information includes a count of single-bit errors, frame errors, and error time.

●为了确定接收信号的误码率是在两个不同预设阈值之上或其之下,EOS装置设置两个B2错误率阈值块。 ● In order to determine the error rate of the received signal is above a predetermined threshold, or two different below, EOS device B2 is provided two block error rate threshold. 当超过阈值时,通过中断来报告信号失效(SF)以及信号退化(SD)状态。 When the threshold is exceeded, an interrupt signal for reporting the failure (SF) and signal degradation (SD) state.

发送SDH/SONET处理TX成帧器3实现发送SDH/SONET处理器的功能。 Transmitting SDH / SONET framer 3 realize the function processing TX transmitting SDH / SONET processor. 发送SDH/SONET处理器的功能是将LAPS帧封装到SPE/VC中。 A function of transmitting SDH / SONET processor LAPS frame is encapsulated into the SPE / VC of. 然后,它插入适当的POH和TOH/SOH,将最终STS信号输出到后接光纤收发器的并行串行转换器。 Then, it is inserted into the appropriate POH and TOH / SOH, the parallel-serial converter connected to the fiber optic transceiver to the final output signal STS.

●同步净荷包络/虚容器(SPE/VC)生成块将来自系统接口的LAPS帧与通道开销(POH)字节复用,生成SONET的SPE或SDH的VC。 ● synchronous payload envelope / virtual container (SPE / the VC) LAPS frame generation block the passage from the system interface overhead (POH) bytes multiplexing the generated SONET or SDH SPE of VC.

●支持下列POH字节:通道跟踪(J1)、通道BIP-8(B3),信号标签(C2)、通道状态(G1)。 ● POH bytes supports the following: Path Trace (J1), path BIP-8 (B3), the tag signal (C2), channel status (G1). 其他POH字节全部设置为零进行传输。 Other POH bytes set to zero for all transmissions.

●执行AIS和无准备的信号插入。 ● implementation of AIS signals and unprepared inserted.

●TOH/SOH生成,包括:帧字节A1A2-为了测试通过微处理器接口的固定的F628或强制错误(Forced Error),供测试用。 ● TOH / SOH generation, comprising: a frame byte A1A2- To test F628 or fixed force error (Forced Error) through microprocessor interface, for testing purposes.

段跟踪(J0)-可通过微处理器接口编程。 Section trace (J0) - may be programmed via the microprocessor interface.

段增长(Section Growth J0)-固定模式2~12。 Growth section (Section Growth J0) - 2 ~ 12 fixed mode.

段BIP-8(B1)-通过微处理器接口的计算的或强制的错误,供测试用。 Section BIP-8 (B1) - calculated by a microprocessor interface error or mandatory, for testing purposes.

指令线(Orderwire,E1E2)-外部串行接口。 Command line (Orderwire, E1E2) - external serial interfaces.

段用户信道(F1)-外部串行接口。 Section user channel (F1) - the external serial port.

数据通信信道(D1-D12)-外部串行接口。 Data communication channels (D1-D12) - external serial interfaces.

指针字节(H1H2H3)-固定为522,禁止NDF,SS可编程。 Pointer byte (H1H2H3) - 522 fixed to prohibit NDF, SS programmable.

线路BIP-96/24(B2)-通过微处理器接口计算的或强制的错误,供测试用。 Line BIP-96/24 (B2) - calculated by a microprocessor interface or forced errors for testing purposes.

APS/MS AIS(K1K2)-可通过微处理器接口编程。 APS / MS AIS (K1K2) - may be programmed via the microprocessor interface.

同步状态(S1)-可通过微处理器接口编程。 Synchronization state (S1) - may be programmed via the microprocessor interface.

线路/MS REI(M1)-通过微处理器接口计算的或强制的错误,供测试用。 Line / MS REI (M1) - or forced error calculated by the microprocessor interface, for testing purposes.

●没有定义的TOH/SOH,全部设置为零进行传输。 ● not defined TOH / SOH, all zeros are transmitted. 用SONET/SDH帧同步扰码器对净荷扰码,多项式为X7+X6+1。 A SONET / SDH frame synchronous scrambler scrambling the payload, the polynomial X7 + X6 + 1.

下面详细说明LAPS处理过程LAPS处理 The following detailed description LAPS LAPS treatment process

EOS装置1通过LAPS处理器从SONET净荷包络(SpE)中提取帧/包。 EOS device 1 is extracted from the SONET payload envelope (SpE) by the processor LAPS frame / packet. EOS装置1也支持流通过模式(Flow-thru mode),该模式允许SPE直接通过系统接口。 EOS apparatus 1 also supports flow-through mode (Flow-thru mode), the direct mode allows SPE through the system interface. LAPS处理器为LLC和其他基于分组的数据进行LAPS类成帧。 LAPS LAPS processor based framing and other data based on the LLC packet. LAPS处理器是一个单信道引擎,用于按照ITU-T建议X.86将数据包封装到LAPS帧中。 LAPS is a single channel processor engine, according to ITU-T Recommendation X.86 packets encapsulated into LAPS frame. LAPS处理器只对字节对准的数据操作(例如消息的长度是整数字节)。 LAPS processor byte-aligned data only operation (e.g., the byte length of the message is an integer). 在EOS模式,LAPS处理器分成接收LAPS处理器和发送LAPS处理器。 The EOS model, the processor into LAPS LAPS processor receiving and transmitting LAPS processor.

封装LAPS链路实体通过协调子层和等效的MII(介质独立接口)接收来自MAC层的帧。 LAPS encapsulation link entity (media independent interface) receives a frame from the MAC layer through the Reconciliation sublayer and equivalent MII. 这里没有使用地址过滤功能。 There is no use address filtering.

图10所示为IEEE 802.3以太网MAC帧格式的示意图,图中阴影部分定义了LAPS信息字段格式。 FIG 10 is a schematic illustration IEEE 802.3 Ethernet MAC frame format, the shaded part of the definition of the LAPS information field format. 图11所示为封装MAC字段后的LAPS帧格式。 Figure 11 is a LAPS frame format of the encapsulated MAC field. LAPS和MAC的FCS计算分别参考ITU-T建议X.85/Y.1321和IEEE 802.3标准。 LAPS and MAC FCS is calculated separately with reference to ITU-T Recommendation X.85 / Y.1321 and IEEE 802.3 standards. Ethernet over LAPS的功能单元将所有输入LAPS信息字段转发除了源链路端口外的对等连接链路,在转发前,允许缓冲一个或多个输入帧。 Ethernet over LAPS functional units all input information fields LAPS forward link in addition to the peer to peer connection source link port before forwarding the buffer allows one or more input frames. 图4所表示的是协调子层/MII和LAPS/SDH的关系。 Figure 4 represents the relationship between the Reconciliation sublayer / MII and LAPS / SDH is.

接收LAPS处理器接收LAPS处理器12的功能是提取LAPS帧、透明消除(TransparencyRemoval)、FCS错误校验、SPE/VC净荷的解扰、控制和地址字段选项删除以及性能监控。 LAPS LAPS function of receiving processor receives processor 12 is to extract the LAPS frame, transparent elimination (TransparencyRemoval), FCS error checking, SPE / VC payload descrambling, control and address fields and performance monitoring option to remove.

在移去字段标志和字节填充的开始/结束后,剩下的净荷包括数据和FCS字段,更详细的细节请看附图。 After the removal of the filling and byte flag field start / end, and the rest of the data payload includes the FCS field, greater detail at Figures. 注意,在两个包间只需一个标志字节,包之间的所有标志都将丢弃。 Note that, between the two packages simply a flag byte, all flags between packets are discarded.

接收LAPS处理器执行以下功能:●可选地对接收净荷自同步解扰(多项式X43+1)。 LAPS receiving processor to perform the following functions: ● alternatively received from the synchronous descrambling the payload (polynomial X43 + 1).

●检测和终止LAPS帧,如帧定界标志检测。 ● detection and termination LAPS frame, such as frame delimiting flag detection.

●移去控制转义码(Control Escape)填充。 ● Control Escape removed (Control Escape) filled.

●计算任选FCS代码(32位),并与接收的FCS值进行比较。 ● optionally FCS calculation codes (32), and compared with the received FCS value. 性能监控寄存器对错误进行累积。 Performance monitoring register for errors accumulated. 如果检测到FCS错误,输出的数据标记为错误数据。 If a FCS error is detected, the data output of the data marked as an error.

●在字节流中(0x7D、0x7E)检测异常中止序列。 ● the byte stream (0x7D, 0x7E) abort sequence is detected.

●任选地删除地址和控制字段。 ● optionally delete the address and control fields.

●提供任选的最小和最大包长度检测(SW配置),确定数据的RX_ERR信号,以标记错误状态。 ● optionally providing the minimum and maximum packet length detector (SW configuration), it is determined RX_ERR signal data to the error state flag.

●生成对八位组的性能监控:FCS错误、终止包、短包(Short Packet)、长包、由于RXFIFO错误丢弃的包。 ● generating performance monitoring octet: FCS error, packet termination, short packets (Short Packet), long packets, error packets discarded due RXFIFO.

●任选地删除用于处理远端FIFO下溢情况的包填充。 ● optionally remove the distal end for processing packet filled FIFO underflow condition.

●在错误情况下生成中断。 ● generating an interrupt in case of error.

●自动删除生成包间隙标志。 ● automatically delete generated packet gap flag.

●为了速率匹配,如果可能,移去可编程帧间间隙填充字节(0x7E)。 ● For rate matching, if possible, stuffing bytes removed programmable interframe space (0x7E).

●通过转换器19,使来自SDH/SONET块的LAPS信息字段(MAC/GMAC帧)与MII/GMII接口的接收时钟(RX_CLK)同步。 ● converter 19 by the LAPS information field from the SDH / SONET block (MAC / GMAC frame) synchronized with the MII / GMII receive clock (RX_CLK) interface.

LAPS帧同步标志序列(0x7E)确定LAPS帧的开始和结束。 LAPS frame synchronization flag sequence (0x7E) determining the beginning and end LAPS frame. 对接收到的SPE净荷数据逐个八位组搜索查找标志序列,以便给LAPS帧边界定位。 SPE payload data received by one flag sequence octet lookup searches so frame boundary positioned to LAPS. 用于确定标志序列的八位组值是可编程的,缺省值为0x7E。 Octet values ​​for determining the flag sequences are programmable, the default value is 0x7E.

两个连续标志序列构成一个空帧,对于空帧忽略不计。 Two consecutive flag sequences constitute an empty frame, a null frame for negligible. 因此,N个连续标志序列构成N-1个空帧。 Thus, N consecutive flag sequences constitute an empty frame N-1. 对于太短的帧、无效的帧默默地予以丢弃。 For frame is too short, invalid frames to be silently discarded. 如果一个LAPS帧属于以下几类,把该帧看作无效帧:a)不能由两个标志完全定界;b)在帧标志间少于6个八位组;c)含有一个帧校验序列错误;d)含有一个与“4”(基于IPv4的业务)、“6”(基于IPv6的业务)、“255”(基于PPP的业务)不匹配的或者接收器不支持的业务接入点标识符;e)含有一个不能识别的控制字段值;f)以一个多于6个“1”位的序列结束;LAPS八位组去填充处理LAPS八位组去填充过程(有时称作转义变换,Escaping Transform)在FCS计算之前、LAPS帧同步后应用于接收的LAPS帧。 If a LAPS frame belongs to the following categories, the frame is considered invalid frame to: a) not completely bounded by two flags; b) less than 6 between the frame flag octets; c) contains a frame check sequence error; D) and comprising a "4" (based on the IPv4 traffic), "6" (IPv6-based services), "255" (PPP-based service) or does not match the receiver does not support service access point identifier break; E) comprises a control field value unrecognizable; F) ends with a sequence of more than six "1" bits; LAPS LAPS octet to octet filling process to fill process (sometimes referred to escape transform , Escaping Transform) before the FCS calculation, LAPS LAPS applied to the received frame after frame synchronization. 通过检测控制转义八位组(Control Escape Octet)标志序列的开始和结束间的整个LAPS帧,来实现八位组的去填充。 By escaping detection control octets (Control Escape Octet) flag LAPS entire frame between the beginning and end of the sequence, to fill to achieve octet. 一旦发现,从八位组流中移去控制转义八位组,其后的八位组用一个八位组去填充掩蔽八位组(Octet De-Stuffing Masking Octet)执行或异操作。 Once removed from the control escape octets in the octet stream, with a subsequent octets to fill octet masked octet (Octet De-Stuffing Masking Octet) or perform different operations. 不应把终止序列看作是转义序列(Escape Sequence)。 Termination sequences should not be seen as an escape sequence (Escape Sequence).

控制转义八位组的值是可编程的,其缺省值为0x7D。 Control Escape octet value is programmable, the default value 0x7D. 八位组去填充掩蔽八位组也是可编程的,其缺省值为0x20。 Octet to octet fill masking also programmable, the default value is 0x20. 作为一个实例,0x7E被编码成0x7D、0x5E,0x7D被编码成0x7D、0x5D。 As an example, 0x7E is encoded as 0x7D, 0x5E, 0x7D is encoded as 0x7D, 0x5D.

LAPS终止序列在输入LAPS帧中,终止序列(后跟标志序列的控制转义码)的检测是可选的。 LAPS LAPS frame input termination sequence, the termination detection sequence (sequence followed by flags Control Escape) is optional. 终止序列标志着一个终止LAPS帧的结束。 Termination sequence marks the end of a termination LAPS frame.

发送LAPS处理器发送LAPS处理器7将基于包的信息插入到STS SPE中,它提供包封装、FCS字段生成、包间填充、TXFIFO错误恢复和扰码。 LAPS LAPS processor sends transmission processor 7 is inserted into the packet-based STS SPE, which provides packet is encapsulated, the FCS field is generated between the package is filled, the TXFIFO error recovery and scrambling code. 发送LAPS处理器完成以下功能:●将包封装到LAPS帧中,每个包以开始标志(0x7E)、任选FCS字段、任选地址和控制字段、结束标志(0x7E)封装。 LAPS transmission processor performs the following functions: ● LAPS frame encapsulates packets, each packet to the start flag (0x7E), optionally, the FCS field, the address and control fields, optionally, end flag (0x7E) package.

●可选的自同步发送净荷扰码器(多项式为X43+1)。 ● transmitting payload optional self-synchronizing scrambler (polynomial X43 + 1).

●按ITU-T X.85要求进行透明处理(对标志和控制转义码进行八位组填充)。 ● according to ITU-T X.85 transparency processing requirements (a flag and a control escape octet fill code). 在开始和结束字段标志间需进行字节填充。 In between the start and end byte field flags need to be filled. 填充用后跟与0x20(十六进制)异或的原始字节、由控制转义组成的两个字节长的序列替换任何匹配标志或控制转义字节的字节。 Followed by filling with 0x20 (hex) XOR raw bytes, two bytes long sequence composed by the control escape replace any match flag byte or control byte escape.

●生成开始和结束字段标志(0x7E)。 ● generate the start and end field flag (0x7E). 注意,在两个包间可以共享单个标志。 Note that, in the two rooms may share a single flag.

●任选地为帧校验序列(FCS)生成32位CRC。 ● optionally generated 32-bit CRC of a frame check sequence (FCS).

●提供FCS错误插入能力,以便在软件控制下进行测试。 ● provide FCS error insertion capability for testing under software control.

●TX_PRTY错误产生中断。 ● TX_PRTY error interrupt is generated.

●提供FIFO下溢的可选择处理。 ● providing selectable processing underflow FIFO. 当TXFIFO清空时间早于包结束时,会产生FIFO下溢情况。 When TXFIFO emptied earlier than the end of the package, it will generate FIFO underflow condition. 发生了这种情况时,会造成中断。 When this happens, it will cause an interrupt. 此时,包可通过以下几种方式结束:生成FCS错误、生成终止序列,或可通过SW配置转义码在包间隙期间插入“填充”字节。 In this case, the packet may end in the following ways: generating a FCS error, generating a termination sequence, or can be configured through SW escape code into the "fill" during the byte packet gap.

●生成性能监控计数,包括:FIFO错误事件数、异常终止分组数、违反最小和最大包长参数的包数量(可配置SW)。 ● generating a performance monitoring count, comprising: FIFO number of error events, the number of packets terminates abnormally, the number of packet violates the minimum and maximum packet size parameter (configurable SW).

●通过转换器19,使从MII/GMII接收的MAC/GMAC帧与SDH/SONET块时钟同步。 ● converter 19 through the MAC / GMAC SDH frame received from the MII / GMII / SONET clock synchronization block.

●如果必要,为了速率匹配,增加可编程速率包间间隙填充字节(0x7E)。 ● If necessary, for rate matching, the rate of increase programmable inter packet gap stuffing bytes (0x7E).

FCS多项式EOS装置1支持CRC-32帧校验序列(FCS)生成和校验。 EOS FCS polynomial CRC-32 supports an apparatus frame check sequence (FCS) generation and checking.

FCS首先传送最低有效八位组(LSB),最低有效八位组包含有最高项的系数。 FCS is transmitted first least significant octet (LSB), the least significant octet contains the coefficient of the highest term. EOS装置有两种FCS计算方式:按照LAPS的低有效位次序(Littleendian bit order)或高有效位次序(Big endian bit order)。 EOS FCS calculation means two ways: according to the order of LAPS significant bit (Littleendian bit order) or higher order significant bits (Big endian bit order).

下列多项式用来生成和校验FCS值CRC-32:1+x+x2+x4+x5+x7+x8+x10+x11+x12+x16+x22+x23+x26+x32。 The following check polynomial used to generate FCS values ​​and CRC-32: 1 + x + x2 + x4 + x5 + x7 + x8 + x10 + x11 + x12 + x16 + x22 + x23 + x26 + x32. FCS字段由地址(SAPI值)、控制和信息字段的所有比特计算出来,但不包括为了透明而插入的任何八位组。 FCS field by the address (SAPI value), and all the bits of the control information field is calculated, excluding any octets for transparent and inserted. 这既不包括标志序列,也不包括FCS字段本身。 This includes neither flag sequence, nor the FCS field itself. 对于两种FCS方法,CRC生成器和校验器均初始化成全部为逻辑“1”。 For both methods FCS, CRC checker and generator are all initialized to a logic "1." FCS计算完成后,FCS值为1的补码,这就将这个新值插入FCS字段中。 After completion of the calculation FCS, FCS is a complement, which is inserted into this new value in the FCS field.

下面,详细说明根据本发明数据在发送方向上的处理过程。 Next, the process is described in detail in the data transmission direction according to the present invention.

发送方向数据处理在发送方向,EOS装置1将基于分组的数据插入STS/STM SPE中。 Directional data transmission processing in the transmission direction, EOS device 1 is inserted into the STS / STM SPE in packet-based data. 设备操作模式可通过管理控制接口来提供。 The device operating mode may be provided by a management and control interface. 寄存器值TX_EOS=1使设备处于EOS模式。 Register value TX_EOS = 1 so that the device is in EOS mode.

发送FIFO接口在EOS模式中,发送系统接口作为兼容MII接口运行。 EOS transmit FIFO interface mode, a transmission system compatible with the interface MII interface operation.

1.发送FIFOTX FIFO 13,通过插入一个0x7E标志或通过同步TX FIFO的接收和发送端,将从转换器19接收到的MII突发帧(如100M)通过并行处理转换成周期性的LAPS帧(如155M)。 1. Send FIFOTX FIFO 13, by inserting a marker 0x7E synchronization by receiving and transmitting side TX FIFO, the burst frames from converter MII (e.g., 100M) 19 converts the received frame into a periodic or LAPS through parallel processing ( such as 155M).

发送系统接口由在发送通道的发送方向上位于EOS装置之前的链路层设备控制。 The transmission system is controlled by the interface link layer devices in the transmission direction of the transmission path located before EOS device. 链路层设备提供一个用于同步所有接口传输的时钟到EOS装置接口。 A link layer devices to provide clock synchronization for transmission to all interfaces EOS device interface. 该约定要求EOS装置有一个速率匹配缓冲器(如FIFO)。 This convention requires EOS rate matching means has a buffer (e.g. FIFO). FIFO大小的最小值为512字节。 Minimum FIFO size is 512 bytes. EOS装置也通过FIFO传输包的状态(分组/信元的开始/结束、分组的最后一个字是否由一个或两个八位组组成、包错误)。 EOS device status packet is also transmitted via the FIFO (packet / cell start / end, if the last word of the packet by one or two octets, packet error).

2.发送FIFO错误在EOS模式中,FIFO态由EOS装置来监控,每当出现以下情况时,宣布出现FIFO错误状态:1)在包结束(TX_EOP指示)前接收到MII_TX_SOP,2)在跟随TX_CLAV信号的不确定的“发送窗口”之外激活MII_TX_ENB。 2. The error in the transmit FIFO mode EOS, EOS FIFO state monitored by means whenever the following occurs, error status FIFO declared: 1) before the end of packet (TX_EOP instruction) received MII_TX_SOP, 2) following the TX_CLAV outside the uncertain signals "sending window" activate MII_TX_ENB. 通过设置MII_TX_FIFOERR_E=1向管理接口报告FIFO错误事件。 By setting MII_TX_FIFOERR_E = 1 report to the management interface FIFO error events. EOS装置有一个8位FIFO错误计数器,记录受FIFO错误事件影响的每个包。 EOS means has an 8-bit FIFO error counters, each recorded packet error event affected by the FIFO.

当性能监控计数器被锁存时,该计数器值由MII_TX_FIFOERR_CNT[7:0]寄存器锁存,并且清空FIFO错误计数器。 When the performance monitor counter is latched by the value of the counter MII_TX_FIFOERR_CNT [7: 0] register latch, and empty FIFO error counters. 如果自LATCH_EVENT的最后上升沿以来至少出现一次FIFO错误事件,则设置FIFO错误事件位-MII_TX_FIFOERR_SECE。 If a FIFO error events since the last rising LATCH_EVENT at least, set the event FIFO error bit -MII_TX_FIFOERR_SECE. 在EOS模式中(MII_TX_EOS=1),EOS装置终止错误的包。 The EOS mode (MII_TX_EOS = 1), EOS device terminates the error packet.

3.EOS错误包处理在EOS运行模式(MII_TX_EOS=1)中,提供错误包处理过程。 Error handling in a packet 3.EOS EOS operation mode (MII_TX_EOS = 1), there is provided an error packet processing.

4.TX_ERR链路层指示当一个特殊的分组内含有错误并且应当终止或丢弃时(见MII_TX_ERR定义),发送系统接口提供了一种链路层设备能够用来指示给EOS装置的方法。 4.TX_ERR link layer containing an error indication when a particular packet or discard and should be terminated (see MII_TX_ERR defined), there is provided a transmission system interface link layer devices to a method of indicating means can be used to EOS.

EOS装置1包含一个8位链路层错误计数器,它对从链路层接收到的有错误标志的每个包计数。 EOS device 1 comprises an 8-bit error counter link layer, it receives from the link layer to count each packet has an error flag. 当性能监控计数器被锁存时(LATCH_EVENT发送处于高位),该计数器的值由MII_TX_EOS_LLPKT_ERRCNT[7:0]寄存器锁存,清空链路层包错误计数器。 When the performance monitor counter is latched (LATCHEVENT at a high transmission), the value of the counter by MII_TX_EOS_LLPKT_ERRCNT [7: 0] register latch, link layer packet error counter is cleared. 如果自LATCH_EVENT的最后上升沿以来至少出现一次链路层包错误事件,则设置链路层错误包错误事件位,MII_TX_EOS_LLPKT_ERR_SECE。 If a link layer packet error events since the last rising LATCH_EVENT at least, set the link layer packet error event error bit, MII_TX_EOS_LLPKT_ERR_SECE.

5.最小/最大包大小EOS有一个选项,如果一个包超过了最小或最大包大小,则EOS装置认为该包出现了错误,并且不发送或终止该包。 The minimum / maximum packet size EOS has an option, if a packet exceeds the minimum or maximum packet size, the EOS means that the packet error occurred and the packet is not transmitted or terminated. 包大小仅仅指LAPS包的大小,不包括EOS装置插入的字节(标志序列、地址、控制、FIFO下溢、透明或FCS字节)。 Only refers to the size LAPS packet size packet, the EOS device is inserted does not include bytes (flag sequence, address, control, the FIFO underflow, transparent or FCS bytes). 这些最小和最大值可通过管理控制接口编程。 These minimum and maximum values ​​can be programmed by the management control interface. 寄存器MII_TX_EOS_PMIN[3:0]包含最小包大小,其缺省值为6。 Register MII_TX_EOS_PMIN [3: 0] contains the minimum packet size, it defaults to 6. 寄存器MII_TX_EOS_PMAX[15:0]包含最大包大小,其缺省值为0x05E0。 Register MII_TX_EOS_PMAX [15: 0] contains the maximum packet size, the default value 0x05E0.

EOS装置1通过管理接口的指令来禁止/允许最小和最大包大小校验。 EOS instruction device 1 via the management interface to disable / enable checking the minimum and maximum packet size. 如果MII_TX_EOS_PMIN_ENB或MII_TX_EOS_PMAX_ENB=1,允许由于违反包大小限制的包终止。 If MII_TX_EOS_PMIN_ENB or MII_TX_EOS_PMAX_ENB = 1, allows the packet size limitations due to violation of the packet is terminated. 如果=0(缺省设置),则忽略包大小限制功能。 If = 0 (the default), the packet size is ignored limiting function.

EOS装置1包含两个8位计数器,对每次的违反最小和最大包大小限制条件进行计数。 EOS device 1 comprises two 8-bit counter, the maximum and minimum packet size constraint violation counts each. 当性能监控计数器被锁存时,这些计数器的值由MII_TX_EOS_PMIN_ERRCNT[7:0]和MIITX_EOS_PMAX_ERRCNT[7:0]寄存器锁存,清空包大小违例计数器。 When the performance monitoring counters are latched by the values ​​of these counters MII_TX_EOS_PMIN_ERRCNT [7: 0] and MIITX_EOS_PMAX_ERRCNT [7: 0] register latch, empty packet size violation counter. 如果自LATCH_EVENT的最后上升沿以来至少出现一次包大小违例错误,则设置适当的包大小违例二次事件位,MII_TX_EOS_PMIN_ERR_SECE或MII_TX_EOS_PMAX_ERR_SECE。 If a packet size violation error since the last rising LATCH_EVENT at least, set the appropriate packet size violations secondary event bit, MII_TX_EOS_PMIN_ERR_SECE or MII_TX_EOS_PMAX_ERR_SECE.

6.错误包终止包开始传输后,如果接收或检测到错误情况,EOS装置1不能删除包,因此这些包将会被终止。 6. Error packet terminates the packet transmission begins, or if the receiver detects an error condition, the EOS device package 1 can not be deleted, so these packets will be terminated. EOS装置支持两种终止错误包的选择方法。 EOS device supports two options to choose to terminate the error packets.

缺省选项是通过插入终止序列0x7d7e来终止一个包。 The default option is to terminate a packet by inserting a termination sequence 0x7d7e. 远端接收器接收到该代码后丢弃该包。 After the distal end of the tag receiver receives the packet is discarded. 另外一种方案是通过简单地反转FCS字节来终止错误包。 Another solution is to terminate the packet error by simply reversing the FCS bytes. 终止模式由管理控制接口来控制。 Termination mode is controlled by the management and control interface. MII_TX_EOS_FCSABRT_ENB=1为FCS反转方法,MII_TX_EOS_FCSABRT_ENB=0(缺省设置)禁止FCS反转方法。 MII_TX_EOS_FCSABRT_ENB = 1 to FCS inversion method, MII_TX_EOS_FCSABRT_ENB = 0 (default) is prohibited FCS inversion method.

线路端包环回为了进行测试,EOS装置1提供了用户环回包功能,它将从SONET/SDH信号中提取的包置入发送方向的FIFO中,在这里,替换从系统接口接收到的数据。 For loopback packet end line test, the EOS device 1 provides a user function loopback packet, the packet into the FIFO transmission direction it is extracted from the SONET / SDH signals in, where replacement data received from the interface to the system . 然后这些数据进入发送端LAPS处理,最后送回到SONET/SDH线路。 The data is then transmitted into the end LAPS, and finally returned to the SONET / SDH line. 当MII_R_TO_T_LOOP设置为1时,环回功能激活。 When MII_R_TO_T_LOOP set to 1, the loopback function is activated. 当MII_R_TO_T_LOOP设置为0时,禁止环回,进行正常的处理过程。 When MII_R_TO_T_LOOP set to 0, loopback, normal process. 这种环回功能主要是用于设备测试。 This loopback is mainly used for device testing. 在实际运行中,如果接收时钟快于发送时钟,而SONET/SDH净荷填充了数据包,则由于发送端不能容纳接收端的全部速率,将产生周期性错误。 In actual operation, if the receive clock is faster than the transmit clock, the SONET / SDH payload filling the data packet, since the rate of the transmitting end can not accommodate all of the receiving end, will generate cyclical error.

发送LAPS过程在发送系统接口后,在EOS模式(MII_TX_EOS=1)时,EOS装置1执行以下处理:1.在LAPS帧中封装包用于EOS的LAPS帧定义如图4所示。 When the transmission process after transmitting LAPS system interface, the EOS model (MII_TX_EOS = 1), EOS processing apparatus 1 performs the following: 1. In the capsule LAPS LAPS frame for frame EOS defined as shown in FIG. 在EOS模式中(MII_TX_EOS=1),每个从链路层接收的LAPS包用在ITU-T X.85中定义的标志序列描绘,标志序列用来指示LAPS帧的开始和结束,其值为01111110(十六进制为0x7e)。 The EOS mode (MII_TX_EOS = 1), each received from the link layer LAPS coated with a flag sequence defined in ITU-T X.85 drawing, the flag sequence is used to indicate the beginning and end LAPS frame, a value of 01111110 (hexadecimal 0x7e).

作为选项之一,EOS装置可插入单个标志来指示一个帧的结束和下一个帧的开始,该项功能由管理接口来控制。 As one option, the EOS device may be inserted into a single flag to indicate the end and beginning of the next frame, this function is controlled by a management interface frame. 如果MII_TX_EOS_EOP_FLAG=1,则EOS装置插入分离标志,以指示帧的开始和结束。 If MII_TX_EOS_EOP_FLAG = 1, the separation device is inserted EOS flag to indicate the beginning and end of the frame. 如果MII_TX_EOS_EOP_FLAG=0(缺省设置),则只可插入单一的标志序列。 If MII_TX_EOS_EOP_FLAG = 0 (the default setting), only a single flag sequence may be inserted.

在禁止生成FCS字段的特殊情况下,EOS装置忽略MII_TX_EOS_EOP_FLAG,始终插入帧开始和结束标志序列。 In special cases inhibit generation FCS field, EOS device ignores MII_TX_EOS_EOP_FLAG, always inserted frame start and end flag sequences. 这是一种非标准运行模式,因为根据ITU-T X.85,FCS字段是必须遵循的。 This is a non-standard mode of operation, because, according to ITU-T X.85, FCS field is mandatory. 这种特性要求确保接收端在测试过程中能够正确运行。 This feature requires the receiving end can ensure that during the test run correctly. 在该期间,禁止使用FCS,有可能是单字节的数据包。 During this period, prohibit the use of FCS, there may be a single-byte packets.

2.地址和控制字段X.86标准定义了紧跟在帧开始标志序列后的两个字段:一个地址字段,该字段设置为0x0c;和一个控制字节,该字节定义为00000011。 2. The address and control fields X.86 standard defines two fields immediately after the frame start flag sequence: an address field, the field is set to 0x0C; and a control byte which is defined as 00000011. 在EOS模式(MII_TX_EOS=1)中,EOS装置可选择插入这些字段,如果MII_TX_EOS_ADRCTL_INS=1。 The EOS model (MII_TX_EOS = 1) in, EOS device selectively inserted into these fields, if MII_TX_EOS_ADRCTL_INS = 1. 如果MII_TX_EOS_ADRCTL_INS=0(缺省设置),则不插入这些字段。 If MII_TX_EOS_ADRCTL_INS = 0 (the default), the field is not inserted.

3.透明性处理在EOS模式(MII_TX_EOS=1),八位组填充过程在一个被称作透明处理(Transparency Processing)的点上进行。 3. Transparency processing mode EOS (MII_TX_EOS = 1), octet at a filling process is referred to as the processing performed on the clearing point (Transparency Processing) a. 一个特殊的八位组—控制转义码(01111101或十六进制0x7d)用作标志符以指示在接收端需要特殊处理的字节。 A special octet - Control Escape (or 01111101 hex 0x7D) used as a flag to indicate that the byte at the receiving end requires special handling. 控制转义码用来标志帧数据中任何特殊代码的出现。 Control Escape frame data used to mark the occurrence of any special code.

进行FCS计算后,EOS装置检查任意两个标志序列间的整个帧。 After FCS calculation, the entire frame between the two sequences EOS device checks any flags. 每次出现的标志为0x7e或0x7d的任何代码被后跟由与十六进制0x20码进行异或运算的原始八位组的控制转义八位组组成的两个八位组序列替换。 Each occurrence of any signs of code 0x7d 0x7e or two octets are replaced with escape sequences followed by a control octet XOR 0x20 in hexadecimal code consisting of the original octet. EOS装置对下列字节序列进行透明处理,一个例外是EOS装置插入的用于描述帧的标志序列。 It means the following byte sequence EOS transparent processing, an exception flag sequence is used to describe the EOS device into the frame. 净荷(在标志序列间)中的0x7e描述如下:0x7e被编码为0x7d、0x5e;0x7d被编码为0x7d/0x5d。 Payload (between flag sequences) 0x7E described as follows: 0x7e is encoded as 0x7d, 0x5e; 0x7d is encoded as 0x7d / 0x5d.

SPE生成1.EOS操作(MII_TX_EOS=1)随后EOS流映射到SONET/SDH同步净荷包络(SPE)的净荷中。 SPE generates 1.EOS operation (MII_TX_EOS = 1) then EOS stream is mapped to SONET / SDH synchronous payload envelope (SPE) payload. EOS八位组边界与SPE八位组边界对齐。 EOS octet boundaries aligned with the SPE octet boundaries. 由于EOS帧长度可变,因此,它们被允许跨越SPE边界。 EOS frame length due to the variable, therefore, they are allowed to cross the border SPE. 在运行过程中当没有立即可插入SPE的LAPS帧时,发送标志序列来填充LAPS帧间的时间。 When no SPE is inserted immediately LAPS frame during operation, transmission flag LAPS fill time sequence frames. 这只是在两个完整的帧间才进行。 This is only carried out only two complete frames. 对STS-3c/STM-1的Ethernet over SONET/SDH的可用信息速率是149.760Mbps。 Available information rate Ethernet over SONET STS-3c / STM-1 is / SDH is 149.760Mbps.

2.FIFO下溢在EOS模式(MII_TX_EOS=1)中,理所当然在两个包间是空的,但在包发送时不应该是空的,即接收到MII_TX_SOP指示后不能是空的,但在接收到MII_TX_SOP指示之前可以是空的。 2.FIFO underflow EOS mode (MII_TX_EOS = 1), the course between the two packages is empty, but should not be transmitted when the packet is empty, i.e. after receiving the indication MII_TX_SOP not be empty, but is received before MII_TX_SOP indication may be empty. 如果发生了这种情况,EOS装置为处理FIFO下溢提供了两种选择方案:可用终止模式,终止包;或可发送一个特殊代码,MII_TX_EOS_FIFOUNDR_BYTE[7:0],填充SPE,直到FIFO中再次出现有效数据。 If this happens, the EOS device to process the overflow FIFO provides two options: Available termination mode, packet termination; or may send a special code, MII_TX_EOS_FIFOUNDR_BYTE [7: 0], the SPE filled, until the FIFO again valid data. 寄存器MII_TX_EOS_FIFOUNDR_MODE控制响应;MII_TX_EOS_FIFOUNDR_MODE=0表示包将会被终止,这是缺省值。 MII_TX_EOS_FIFOUNDR_MODE register control response; MII_TX_EOS_FIFOUNDR_MODE = 0 indicates the packet is terminated, which is the default. MII_TX_EOS_FIFOUNDR_MODE=1表示在下溢情况发生时,将会发送特殊FIFO下溢代码MII_TX_EOS_FIFOUNDR_BYTE[7:0]。 MII_TX_EOS_FIFOUNDR_MODE = 1 indicates when underflow occurs, the code will be sent special overflow FIFO MII_TX_EOS_FIFOUNDR_BYTE [7: 0]. MII_TX_EOS_FIFOUNDR_BYTE[7:0]缺省值为0x? MII_TX_EOS_FIFOUNDR_BYTE [7: 0] The default value is 0x? ? .

SPE/VC生成STS-3c SPE或VC-4的结构如图12A-C所示。 SPE / VC generating structured STS-3c SPE or VC-4 shown in FIG. 12A-C. SPE/VC的第一列是POH(通道开销)。 SPE / VC POH column is first (path overhead). 通道开销有9个字节。 Nine path overhead bytes. 这9个字节的顺序对SONET为J1、B3、C2、G1、F2、H4、Z3、Z4和Z5,对SDH为J1、B3、C2、G1、F2、H4、F3、K3和N1。 The order of 9 bytes of the SONET-J1, B3, C2, G1, F2, H4, Z3, Z4 and Z5, as for SDH J1, B3, C2, G1, F2, H4, F3, K3 and N1. 通道开销的第一个字节是通道跟踪字节J1,通过相关的STS/AU指针指示其相对SONET/SDH TOH/SOH的位置。 The first byte is a path trace of a path overhead byte J1, through the associated STS AU pointer / their position relative to SONET / SDH TOH / SOH of. 下面定义POH字节的发送值。 The following transmission values ​​defined POH bytes. 这里SONET和SDH的字节名称不同,首先列出SONET的名称。 Here different SONET and SDH byte name, the name of SONET listed first.

1.通道跟踪(J1)在J1字节中,EOS可以发送一个16字节或64字节的通道跟踪消息,消息存储在MII_TX_J1_[63:0]_[7:0]中。 1. The path trace (J1) in the J1 byte, the EOS can send a 16-byte or 64-byte path trace message, the message is stored in MII_TX_J1_ [63: 0] _ [7: 0] in. 如果MII_TX_J1_SEL=0,则J1字节以从MII_TX_J1_[15]_[7:0]到MII_TX_J1[0]_[7:0]的16字节序列重复发送,否则以从MII_TX_J1_[63]_[7:0]到MII_TX_J1_[0]_[7:0]的64字节序列重复发送(通常16字节序列用于SDH模式,64字节用于SONET模式)。 If MII_TX_J1_SEL = 0, to the J1 byte [15] _ [7: 0] from MII_TX_J1_ to MII_TX_J1 [0] _ [7: 0] of the 16-byte transmission sequence is repeated, otherwise the MII_TX_J1_ [63] _ [7 : 0] to MII_TX_J1_ [0] _ [7: 0] of the 64-byte transmission sequence repeats (typically 16 bytes for SDH mode sequence, 64 bytes for SONET mode).

2.通道BIP-8(B3)如果B3_INV=0,则比特交错奇偶校验位8(BIP-8)作为偶数奇偶校验位(正常)发送,否则生成奇数奇偶校验位(不正确)。 2. Channel BIP-8 (B3) if B3_INV = 0, then the bit interleaved parity 8 (BIP-8) as even parity bit (normal) transmission, or generates an odd parity bit (incorrect). BIP-8对前一个SPE/VC(包括POH)的所有位进行计算,其值置入当前的SPE/VC的B3字节中。 BIP-8 is calculated for all the bits of the previous SPE / VC (including POH), which is placed in the current value of SPE / VC of the B3 byte.

通过定义BIP-8,B3的第一位提供前一个SPE/VC所有字节的第一位的奇偶校验,B3的第二位提供前一个SPE/VC所有字节的第二位的奇偶校验,等等。 BIP-8, the first to provide a pre SPE / VC of all bytes in the first parity bit by defining the B3, B3 of a second before providing SPE / VC of all bytes of the second parity bits experience, and so on.

3.信号标签(C2)信号标签字节指示SPE/VC的组成。 3. Signal Label (C2) consisting of a signal label byte indicative of SPE / VC's. 预设值TX_C2[7:0]插入到生成的C2字节中。 Default TX_C2 [7: 0] is inserted into the C2 byte generated.

4.通道状态(G1)通道REI接收端监控接收的SPE/VC中的B3位错误。 4. Channel Status (G1) to monitor the channel received by the receiving end REI SPE / VC of the B3 bit errors. 每个帧(0到8)检测到的B3错误数从接收端传输到发送端,插入到发送通道状态字节G1中,用作远程错误指示(Remote Error Indication)。 Each frame (0-8) B3 errors detected transmission from the reception side to the transmission side, into the transmit path status byte G1 and used as a remote error indication (Remote Error Indication). 如果FORCE_G1ERR=1,则G1的4个MSB(最高有效位)作为1000连续发送(作测试用)。 If FORCE_G1ERR = 1, then G1 is 4 MSB (Most Significant Bit) of 1000 as a discontinuous transmission (for testing). 否则如果PERI_INH=0,则它们设置为等于接收端POH监控模块最近检测到的B3错误数的二进制值(0000到1000,指示0到8)。 Else if PERI_INH = 0, they are set equal to the monitoring module receiving POH recent binary value of the detected number of errors terminal B3 (0000-1000, indicating 0-8). 否则,将它们全部设置为零。 Otherwise, they are all set to zero.

通道RDIG1的第5位可用作通道/管理单元远程故障指示(RDI-P),或者G1的第5、6和7位用作增强的RDI-P指示符。 RDIG1 channel 5 may be used as the channel bit / management unit of the remote fault indication (RDI-P), 5, 6 and 7 or G1 is enhanced RDI-P is used as an indicator. G1的第5、6和7位中的发送值或者从TX_G1[2:0]寄存器产生(如果PRDI_AUTO=0),或者EOS装置自动生成一个增强的RDI信号(如果PRDI_AUTO=1,PRDI_ENH=1),或者是一位RDI信号(如果PRDI_AUTO=1,PRDI_ENH=0)。 5, 6 and 7 of the transmission values ​​or the G1 [2: 0] generated from TX_G1 register (if PRDI_AUTO = 0), or EOS means automatically generates an enhanced RDI signal (if PRDI_AUTO = 1, PRDI_ENH = 1) or an RDI signal (if PRDI_AUTO = 1, PRDI_ENH = 0). G1的第5、6和7位中发送的值如表4所示。 5, 6 and transmitted values ​​G1 and 7 shown in Table 4.

表4通道RDI位值 Table 4 Channel bit value RDI

如果PRDI_AUTO=1,则上面所述的值最少发送20帧。 , If the value of the above minimum transmission PRDI_AUTO = 1 20. 一旦以相同值发送了20帧,则发送对应表4列出的当前态的故障指示值。 Once the transmission 20 to the same value, then a corresponding state value of the current fault indication listed in Table 4. G1的第8位(最低有效位)没有使用,设置为0。 G1 8 bit (least significant bit) is not used, it is set to 0.

5.其他POH字节EOS装置1不支持剩下的POH字节,这些字节以固定的全部零字节发送。 5. Other POH bytes EOS device 1 does not support the rest of the POH bytes, these bytes are transmitted to all fixed zero bytes. 这些字节包括通道用户信道(F2)、位置指示符(H4)、通道增长/用户信道(Z3/F3)、通道增长/通道APS信道(Z4/K3)以及前后连接监控字节(Z5/N1)。 These bytes include a channel user channel (F2), a position indicator (H4), channel increase / user channel (Z3 / F3), the channel increase / channel APS channel (Z4 / K3) and the front and rear connection monitoring bytes (Z5 / N1 ).

SONET/SDH帧生成SONET/SDH帧生成模块通过生成传送(段)开销(TOH/SOH)字节、以来自SPE/VC的字节填充净荷、对除第一行的TOH/SOH字节外的所有字节扰码,来创建STS-3c/STM-1。 SONET / SDH frame generation SONET / SDH frame generation module overhead (TOH / SOH) byte transfer by generating (segments) that from the SPE / VC payload padding bytes, except for the first row TOH / SOH bytes All byte scrambling code to create STS-3c / STM-1.

1.帧对准相对于输入的TX_FRAME_IN,生成帧的位置是固定的。 1. TX_FRAME_IN frame alignment relative to the input, generates a frame position is fixed. 帧开始指示输出TX_FRAME_OUT与TX_FRAME_IN输入有一个固定的但非特指的关系。 TX_FRAME_OUT frame start indication output and input TX_FRAME_IN has a fixed but unspecified relationships. TX_FRAME_OUT上一个时钟周期宽脉冲与发送线路输出TX_DATA[7:0]数据字节的关系由MII_TX_FOUT_BYTE_TYPE[1:0]和TX_FOUT_BYTE_NUMBER[3:0]寄存器控制。 TX_FRAME_OUT on a clock cycle wide pulse output transmission line TX_DATA [7: 0] data byte relation [1: 0] and the MII_TX_FOUT_BYTE_TYPE TX_FOUT_BYTE_NUMBER [3: 0] register.

2.净荷生成SONET或SDH净荷在正常情况下由SPE/VC字节填充而成。 2. payload generation SONET or SDH payload normally filled by SPE / VC bytes together. 在STS-3c/STM-1模式(MII_TX_SIG_MODE=0)中,SPE/VC的J1字节放置在第10列第1行中。 In the STS-3c / STM-1 mode (MII_TX_SIG_MODE = 0) in, SPE / VC of the J1 byte is placed in a column in the first row 10.

在线路(复用段,MS)告警指示信号(AIS)LAIS,或通道(管理单元,AU)告警指示信号(PAIS)发送期间,悬挂起SONET/SDH净荷的正常生成。 During the line (Multiplex Section, the MS) Alarm Indication Signal (AIS) LAIS, or channel (management unit, AU) Alarm Indication Signal (PAIS) transmitting, hanging from the normal generation SONET / SDH payload. MII_TX_LAIS和MII_TX_PAIS寄存器控制AIS的生成。 MII_TX_LAIS and control the generation of AIS MII_TX_PAIS register. 如果MII_TX_LAIS或MII_TX PAIS=1,则整个净荷(9396或2349字节)全部以1字节填充。 If MII_TX_LAIS or MII_TX PAIS = 1, then the entire payload (9396 or 2349 bytes) are all filled with 1 byte.

除非激活了AIS,否则,如果TX_UNEQ=1,则生成没有准备的SPE/VC(所有SPE/VC字节全部用零填充)。 Unless activated the AIS, otherwise, if TX_UNEQ = 1, is generated SPE / VC not ready (all SPE / VC all bytes are filled with zeros).

3.TOH/SOH生成 3.TOH / SOH generation

SONET TOH字节与SDH TOH字节基本上是一样的。 SONET TOH byte SDH TOH bytes are substantially the same. 下文中定义生成的所有TOH/SOH字节值。 Defined below all generated TOH / SOH byte value. 当SONET和SDH的字节名称不同时,首先列出SONET所用名称。 As SONET and SDH byte names are different, the first SONET are listed by name. 标准中的空白之处是SONET中没有定义的或者是SDH非标准化保留字节。 Gaps in the SONET standard is not defined or non-standardized SDH reserved bytes. EOS装置1将这些字节全部用零填充。 EOS device 1 all of these bytes are filled with zeros.

在发送LAIS或PAIS过程中,悬挂起TOH/SOH字节的正常生成。 In the transmission process LAIS or PAIS, hanging from the normal generation TOH / SOH bytes. 如果MII_TX_LAIS=1,则正常生成TOH/SOH最开始的3行,但TOH/SOH剩余部分(以及所有SPE/VC字节)全部为设置1再进行发送。 If MII_TX_LAIS = 1, then the normal production of TOH / SOH beginning of the 3 rows, but TOH / SOH remaining portion (and all SPE / VC bytes) are all disposed a further transmission. 如果MII_TX_PAIS=1,则除第4行中所指针字节外,TOH/SOH所有行字节均正常生成。 If MII_TX_PAIS = 1, in addition to the fourth row of the pointer byte, TOH / SOH bytes are generated for all normal rows. H1、H2和H3字节(以及所有SPE/VC字节)全部设置为1传送。 H1, H2 and H3 bytes (and all the SPE / VC byte) are all configured to transmit one.

以下面固定模式正常生成帧字节:A1:1111_0110=F6;A2:0010_1000=28。 The following byte fixed pattern generated normally frame: A1: 1111_0110 = F6; A2: 0010_1000 = 28.

为了测试之目的,A1和A2生成时可以包含错误。 For testing purposes, when A1 and A2 may contain an error generated. 如果A1A2_ERR=0,不插入错误。 If A1A2_ERR = 0, no insertion error. 当A1A2_ERR=1时,通过A1A2_ERR_PAT[15:0]的值与A1和A2进行异或运算生成8个帧的每个群中的m个连续帧(这里m相当于A1A2_ERR_NUM[2:0]的二进制数),A1的最高有效位与A1A2_ERR_PAT[15]进行异或运算,A2的最低有效位是A1A2_ERR_PAT[0]进行异或运算。 When A1A2_ERR = 1, by A1A2_ERR_PAT [15: 0] and the value of A1 and A2 performs an exclusive OR operation for each group of 8 frames to generate the m successive frames (where m corresponds A1A2_ERR_NUM [2: 0] Binary number), and the most significant bit A1 A1A2_ERR_PAT [15] XOR operation, the least significant bit A2 is A1A2_ERR_PAT [0] XOR.

在16个连续帧的期间内,EOS装置连续发送包含在MII_TX_J0_[15:0]_[7:0]的16字节模式,从MII_TX_J0[15]_[7:0]字节开始按递减顺序发送。 Over a period of 16 consecutive frames, included in the EOS device continuously transmits MII_TX_J0_ [15: 0] _ [7: 0] of the 16-byte mode, from MII_TX_J0 [15] _ [7: 0] byte in descending order send.

ITU-T G.707标准规定含第3条/G.831定义的段接入点标识符(SAPI)的16位段跟踪帧以连续J0字节连续发送。 16-bit segment ITU-T G.707 standard containing article defined in paragraph 3 /G.831 access point identifier (the SAPI) continuously transmitting frames in a continuous trace byte J0. 注意,只有帧开始标志符字节在其最高有效位应为1。 Note that only the frame start flag byte in which the most significant bit should be 1.

目前,没有对SONET定义段跟踪功能。 Currently, there is no tracking of SONET defined segment. 除非给SONET定义一个相似的段跟踪字段,否则所有的MII_TX_J0字节应采用0000_0001填充,因此,在J0中连续发送一个十进制的1。 Unless otherwise defined a segment tracking field similar to SONET, otherwise, all the bytes should be 0000_0001 MII_TX_J0 filled, therefore, the continuous transmission of a decimal 1 in the J0. Z0字节在STS-12c/STM-4(MII_TX_SIG_MODE=1)模式中以2到12的二进制次序发送,在STS-3c/STM-1(MII_TX_SIG_MODE=0)模式中为2到3(这在GR-253中已作规定)。 Z0 bytes transmitted binary sequence 2 to 12 in the STS-12c / STM-4 (MII_TX_SIG_MODE = 1) mode, the STS-3c / STM-1 (MII_TX_SIG_MODE = 0) mode is 2-3 (which GR -253 already specified).

如果MII_B1_INV=0,则B1 8位比特交错奇偶校验(BIP-8)以偶数奇偶校验位(正确态)发送,否则生成奇数奇偶校验位(不正确)。 If MII_B1_INV = 0, B1 8 bits of the interleaved parity (BIP-8) with an even parity bit (proper state) transmission, or generates an odd parity bit (incorrect). BIP-8对前一个扰码后STS-3c/STM-1帧的所有位进行计算,在扰码前置入当前帧的B1字节中。 BIP-8 is calculated for the STS-3c / STM-1 frame before all bits of a scrambling code after implantation B1 byte of the current frame before scrambling. 通过定义BIP-8,B1的第一位提供前一帧所有字节的第一位的奇偶校验,B1的第二位提供前一帧所有字节的第二位的奇偶校验,等等。 By defining the BIP-8, B1 to provide a first one of a former parity of all bytes, the second B1 provides all bytes before a second parity bits, etc. .

定义指令线字节用来携带两个64kb/s的数字语音信号。 Definition instruction used to carry the two-byte line 64kb / s digital voice signal. F1字节给网络提供者使用。 F1 byte to the network provider used. 发送块接收3个串行输入:MII_TX_E1_DATA、MII_TX_E2_DATA和TX_F1_DATA,用来插入到发送的E1、E2和F1字节中。 Transmission block received three serial inputs: MII_TX_E1_DATA, MII_TX_E2_DATA and TX_F1_DATA, for insertion into the transmission of E1, E2 and F1 bytes. 从EOS装置1输出一个单一的带缺口的64kHz时钟(MII_TX_E1E2F1_CLK),以便为这三个串行输入提供时钟参考。 EOS device 1 from the output of a single notched 64kHz clock (MII_TX_E1E2F1_CLK), in order to provide a reference clock for these three serial input.

这些字节的第一位(最高有效位)应与输入帧开始脉中MII_TX_FRAME_IN对齐。 The first byte (MSB) of the input frame start should veins MII_TX_FRAME_IN aligned. 在接收到E1、E2和F1字节的最后一位后,接收到的E1、E2和F1字节插入到输出的SONET/SDH帧中。 After receiving the last bit E1, E2 and F1 bytes received E1, E2 and F1 byte into the output of the SONET / SDH frame.

TOH/SOH定义了两种DCC(数据通信通道),段/再生段DCC用D1、D2和D3字节来产生一个带缺口的192kb/s信道。 TOH / SOH defines two DCC (data communication channel), section / regenerator section DCC using D1, D2 and D3 bytes to generate 192kb / s channel with a gap. 线路/复用段DCC用D4到D12的字节来产生一个带缺口的576kb/s信道。 Line / Multiplex Section DCC to generate 576kb / s channel with a band gap of bytes D4 to D12. 发送端在两个串行输入:MII_TX_SDCC_DATA和MII_TX_LDCC_DATA,接收DCC数据。 The sending end, two serial inputs: MII_TX_SDCC_DATA and MII_TX_LDCC_DATA, DCC receiving data. 为了保证位同步,发送端输出两个时钟:MII_TX_SDCC_CLK,192kHz(带缺口);以及MII_TX_LDCC_CLK,576kHz(带缺口)。 In order to ensure bit synchronization, the transmitting side outputs two clocks: MII_TX_SDCC_CLK, 192kHz (with notch); and MII_TX_LDCC_CLK, 576kHz (with notch). 时钟信号能够使MII_TX_SDCC_DATA和MII_TX_LDCC_DATA位再定位到寄存器,以插入到TOH/SOH。 MII_TX_SDCC_DATA clock signal and enables the repositioning MII_TX_LDCC_DATA bit register, to be inserted into TOH / SOH. MII_TX_SDCC_DATA和MII_TX_LDCC_DATA输入应根据MII_TX_SDCC_CLK和MII_TX_LDCC_CLK下降沿变化,因为重定时是在上升沿做出的。 MII_TX_SDCC_DATA MII_TX_LDCC_DATA and should be based on input and changes falling MII_TX_LDCC_CLK MII_TX_SDCC_CLK, since the retiming is made on the rising edge.

H1和H2字节包含3个字段。 H1 and H2 byte contains three fields. 由于SPE/VC与TOH同步生成,所以无需生成可变指针。 Since the SPE / VC generated in synchronization with the TOH, it is not necessary to generate a variable pointer. 与此相反,有效的H1和H2字节以固定指针值522(十进制)=10_0000_1010(二进制)生成,H3字节全部固定为0。 In contrast, efficient H1 and H2 bytes to a fixed pointer value 522 (decimal) = 10_0000_1010 (binary) generating, H3 byte 0 is all fixed. 这样,SPE/VC中J1字节在STS-3c/STM-1模式(MII_TX_SIG_MODE=0)中被放置在第1行第10列。 Thus, SPE / VC of the J1 byte in STS-3c / STM-1 mode (MII_TX_SIG_MODE = 0) are placed in a column 10, line 1.

如果MII_TX_LAIS或TX_PAIS处于激活态,则H1、H2和H3字节在发送时全部设置为1。 If MII_TX_LAIS TX_PAIS or in the active state, the H1, H2 and H3 bytes are all set to 1 when the transmission. 当MII_TX_LAIS或TX_PAIS转换为0时,EOS装置1在下一个帧中用一个有效的新数据标志(NDF)发送第一个H1字节。 When MII_TX_LAIS TX_PAIS or converted to 0, EOS device 1 with the next frame a new valid data flag (NDF) sends the first byte H1. 在第一个H1字节中以被禁止的NDF字段生成随后的帧。 In the first byte H1 it is prohibited to subsequent frames generated NDF field. 第一个H1-H2字节对以正常指针发送,此时: The first H1-H2 pointer bytes in a normal transmission, then:

●NDF=0110;●SS=TX_SDG_PG,0;●指针值=10_0000_1010;所有其他H1-H2字节对以级联指示字节发送,此时:●NDF=1001;●SS=TX_SDG_PG,0;●指针值=11_1111_1111;在下面B2字节的描述中,根据设备模式(STS-12c模式和STS-3c)的不同其值略有变化。 ● NDF = 0110; ● SS = TX_SDG_PG, 0; ● = 10_0000_1010 pointer value; all other bytes H1-H2 bytes indicating a transmission cascade, this time: ● NDF = 1001; ● SS = TX_SDG_PG, 0; ● pointer value = 11_1111_1111; B2 byte in the following description, the apparatus according to a slight change mode (STS-12c mode and the STS-3c) different value. 为了描述两种模式的操作,采用下面的约定来区分每种模式的要求:STS-3c。 For both modes of operation described, using the following conventions to distinguish each mode requires: STS-3c. TOH/SOH有12[3]个B2字节,它们一同提供BIP-96[BIP-24]检错能力。 TOH / SOH of 12 [3] of bytes B2, which together provide a BIP-96 [BIP-24] error detection capability.

每个B2字节为前一个帧中的12[3]组字节中的1组字节中的字节提供BIP-8奇偶校验。 Each byte provides BIP-8 B2 parity for the previous frame 12 [3] in the group of bytes in byte 1 byte group. 第j列中的B2字节为前一个帧(TOH/SOH开始3行除外)中位于第j+12k(j+3k)的字节提供BIP-8奇偶校验,这里k=0到89。 B2 byte column j for the previous frame (TOH / SOH row 3 except for start) located on j + 12k (j + 3k) providing BIP-8 byte parity, where k = 0 to 89 如果B2_INV=0,则BIP-8以偶数奇偶校验位(正常态)发送,否则,生成奇数奇偶校验位(错误态)。 If B2_INV = 0, then transmitted to the even BIP-8 parity bit (normal state), otherwise, to generate odd parity (error state). BIP-8值在扰码前对前一个STS-3c/STM-1帧中的字节计算出来,在扰码前置入当前帧的B2字节中。 BIP-8 value in the scrambling code before the previous STS-3c / STM-1 frame bytes out into B2 byte of the current frame before scrambling.

K1和K2的5位最高有效位用作自动保护交换(APS)信号。 K1 and K2 five most significant bits as automatic protection switching (APS) signal. K2的3个最低有效位在线路/MS层用作AIS或远程故障指示(RDI),在SONET中,它们也用作APS信令。 K2 three least significant bits of the line / MS AIS layer or as a remote fault indication (the RDI), in SONET, they are also used as APS signal. EOS装置1在发送的K1字节中插入MII_TX_K1[7:0],在发送的K2的5个MSB字节中插入MII_TX_K2[7:3]。 EOS MII_TX_K1 apparatus 1 is inserted in the transmitted K1 byte [7: 0], is inserted in the K2 MII_TX_K2 5 MSB byte transmitted [7: 3].

K2的3个LSB位由3个源控制,按照优先级,它们是:●如果TX_LAPS=1,发送时,将它们全部设置为1(同所有的线路/MS开销字节一样)。 K2 three LSB bits of three source control, according to priority, they are: ● If TX_LAPS = 1, when transmitting, they are set to all 1 (/ MS overhead bytes, like all the lines).

●如果LRDI_INH=0,以及如果(MII_RX_LOS AND NOTRX_LOS_INH)、MII_RX_LOF、MII_RX_LOC或MII_RX_LAIS中任何一个等于1,则它们以110码发送。 ● If LRDI_INH = 0, and if any one is equal to 1 (MII_RX_LOS AND NOTRX_LOS_INH), MII_RX_LOF, MII_RX_LOC or MII_RX_LAIS, then send them to 110 yards. 无论何时激活该特殊事件,最少20帧的K2设置为110。 Whenever you activate the special event, K2 is set to a minimum of 20 110.

●否则发送MII_TX_K2[2:0]码。 ● Otherwise transmitting MII_TX_K2 [2: 0] codes.

RX_LOS可激活到高位(MII_RX_LOS_LEVEL=0,缺省值)或激活到低位(MII_RX_LOS_LEVEL=1)。 RX_LOS may be activated to a high level (MII_RX_LOS_LEVEL = 0, default) or activated to a low (MII_RX_LOS_LEVEL = 1). 在内部,如果MII_RX_LOS_LEVEL=1,则插入MII_RX_LOS以产生MII_RX_LOS。 Internally, if MII_RX_LOS_LEVEL = 1, to generate insert MII_RX_LOS MII_RX_LOS. GR-253 R6-180到R-182要求规定了应在125μs的接收到的LOS、LOF或LAIS期间插入和移去RDI检测。 GR-253 R6-180 R-182 to the requirements to be received in LOS 125μs, during, or LOF LAIS RDI insertion and removal detection.

该字节的4个LSB传送同步状态消息。 4 LSB of the byte synchronization status message transmission. 设置发送的S1字节等于MII_TX_S1_[7:0]。 Set equal to the S1 byte transmitted MII_TX_S1_ [7: 0].

接收端监控接收信号中的B2位错误,在STS-12c/STM-4模式中每帧检测到的B2错误数范围为每帧0到96个B2位,在STS-3c/STM-1模式中为每帧0到24个B2位。 The receiving terminal to monitor the received signal B2 in bit errors in the STS-12c / STM-4 mode of each frame detected B2 errors in the range of 0-96 per frame position B2, the STS-3c / STM-1 mode per frame B2 bits 0-24. 通常,线路/MS远程错误指示(REI)字节、M1字节传送在接收信号中检测到的B2错误计数。 Typically, line / MS remote error indication (REI) bytes, the byte transfer Ml detected in the received signal B2 error count.

通过设置TX_M1_ERR=1,用户可强制发送REI错误指示。 By setting TX_M1_ERR = 1, the user can send REI to force an error indication. 这时M1字节中发送24个数值中的任何一个(STS-3c/STM-1模式)。 M1 any time send a byte (STS-3c / STM-1 mode) of 24 values. 如果LREI_INH=0,则M1字节被设置成等于最近的B2错误计数。 If LREI_INH = 0, then the M1 byte is set equal to the most recent error counts B2. 否则的话,M1字节全部设置为0。 Otherwise, M1 byte set to all zeros.

由于Z1和Z2字节没有标准化,因此,EOS装置1将这些字节全部填充为0。 Since the Z1 and Z2 bytes are not standardized, therefore, the EOS device 1 all of these bytes are filled with zeros.

扰码用一个同步扰码序列对输入数据进行扰码,扰码多项式为x7+x6+1。 With a scrambling code synchronization scrambling sequence scrambling the input data, the scrambler polynomial x7 + x6 + 1. 在SPE/VC第一个字节开始处(在STS-3c/STM-1模式中位于1行10列的字节i)的扰码器初始化为1111111,对除第一行TOH/SOH字节外的整个SONET/SDH信号进行扰码。 At the beginning of the first byte of SPE / VC (i 10 is located in a column octet in STS-3c / STM-1 mode) of the scrambler is initialized to 1111111, the first row TOH / SOH bytes in addition the whole SONET / SDH signals outside scrambled. 为了测试之目的,可通过设置SCRINH为1禁止扰码器。 For testing purposes, by setting 1 to prohibit SCRINH scrambler.

从扰码单元6输出的已扰码的LAPS帧(如155M)被连接扰码单元6和SPE/BC生成单元5之间的FIFO单元(未示出)转换成SDH帧(如155M),该FIFO单元与PLL(锁相环路)协同工作。 LAPS frame has a scrambling code (e.g., 155M) outputted from the scrambler unit 6 is connected between 6 and SPE / BC scrambling code generating unit 5 units FIFO unit (not shown) into the SDH frame (e.g., 155M), the FIFO unit and PLL (phase locked loop) work together.

下面描述数据在接收方向的处理过程。 The following process description data in the receive direction.

1.发送到接收环回和LOC如果R_LOOP=1,EOS装置1接收部能被配置到环回生成发送信号。 1. transmitted to the receiving loop and LOC if R_LOOP = 1, EOS device receiving unit can be configured to generate a transmission signal loopback. 否则,选择从SONET/SDH接口接收到的信号。 Otherwise, the selection signal received from the SONET / SDH interfaces. 在环回中,TX_SONETCLK输入用于确定接收器成帧器和其他接收电路的时钟。 In loopback, TX_SONETCLK input framer for determining receiver receiving circuit and the other clock. 如果没有选择环回,则RX_SONETCLK输入用于确定该电路的时钟。 If loopback is not selected, then the circuit for determining RX_SONETCLK input clock.

RX_SONETCLK输入用TX_CLK输入监控时钟丢失。 RX_SONETCLK monitor input clock is lost with TX_CLK input. 如果RX_SONETCLK上在16个TX_CLK周期没有检测到转换,则设置RX_LOC位。 If the conversion is not detected in RX_SONETCLK 16 TX_CLK cycle, RX_LOC bit is set. 检测到转换时,清除它。 When the conversion is detected, it is cleared. 如果RX_LOC从0转换到1或从1转换到0,设置RX_LOC_D delta位。 If RX_LOC transition from 0 to 1 or from 1 to 0, provided RX_LOC_D delta position.

2.传送开销监控TOH/SOH监控块由J0、B2、K1K2、S1和M1监控字节组成。 2. Monitoring transport overhead TOH / SOH monitoring block consists J0, B2, K1K2, S1 and M1 bytes monitor. 这些TOH/SOH字节监控状态的错误或变化。 The TOH / SOH byte errors or monitor changes state.

2.1.J0监控J0监控有两种操作模式,一种用于SONET应用,一种用于SDH应用。 2.1.J0 monitor J0 monitor has two operating modes, for SONET applications, for SDH applications. 在MII_RX_J0=0模式(SONET)中,J0监控包括检查其值与3个连续帧一致的接收到的J0字节值。 In MII_RX_J0 = 0 mode (SONET) in, J0 monitoring comprises checking a value consistent with three consecutive frames of the received J0 byte values. 当接收到一个一致的J0值时,把它写到MII_RX_J0_[15]_[7:0]。 When receiving a consistent value J0, writes it MII_RX_J0_ [15] _ [7: 0].

在MII_RX_J0=1情况(SDH),J0字节可望包含一个重复的16字节段跟踪帧,该帧包括段接入点标志(SAPI)。 MII_RX_J0 = 1 in the case of (SDH), J0 byte is expected to contain a repeating 16-byte segment track frame, the frame comprising a flag section access point (SAPI). J0监控包括跟踪16字节段跟踪帧开始、检查其值与3个连续段跟踪帧匹配一致的接收的段跟踪帧值。 Monitoring includes 16 bytes J0 section trace tracing frame starts checking the value of the received segment of three successive segments follow the same track frame matching frame value. 当接收到一个一致的帧值时,把它写到MII_RX_J0_[15:0]_[7:0]。 When receiving a frame consistent value, it writes MII_RX_J0_ [15: 0] _ [7: 0]. 段跟踪帧的第一个字节(它包括帧起始标志)写到MII_RX_J0_[15]_[7:0]。 A first track frame byte segment (that includes a frame start flag) is written MII_RX_J0_ [15] _ [7: 0].

2.1.1.成帧除帧起始标志字节的最高有效位外,所有段跟踪帧字节的最高有效位均为0。 2.1.1. Framing except the most significant bit of the frame start flag byte, the most significant bit section trace all frames are zero bytes. J0监控器成帧器搜索15个连续J0字节,该字节最高有效位有一个0,后接的J0字节的最高有效位为1。 J0 monitor framer search 15 consecutive J0 bytes, the byte has a most significant bit 0, followed by the most significant bit is 1 byte J0. 当发现这种模式时,成帧器进入帧内,此时J0_OOF=0。 When this pattern is found, the framer enters the frame, this time J0_OOF = 0. 一旦J0监控器成帧器为内帧,一直留在帧内直到接收到3个连续段跟踪帧中至少有1个最高有效位(MSB)位错误。 Once J0 framer within the monitor frame, the frame remained until receiving three consecutive frames to track segment has at least one most significant bit (MSB) bit errors. 如果MII_RX_J0=0,则J0帧指示节被约束在内帧状态,MII_J0_OOF=0。 If MII_RX_J0 = 0, then J0 Section frame indicates the inner frame is constrained state, MII_J0_OOF = 0. 当MII_J0_OOF改变状态时,设置MII_J0_OOF_D delta位。 When MII_J0_OOF changes state, setting MII_J0_OOF_D delta position.

2.1.2模式接收和比较一旦在帧内,J0监控模块就查找3个连续的16字节(MII_RX_J0=1)或1个字节的段跟踪帧(MII_RX_J0=0)。 2.1.2 Comparison of once and receiving mode frame, J0 PCU Find 3 consecutive 16 bytes (MII_RX_J0 = 1) or a section trace byte frames (MII_RX_J0 = 0). 当接收到3个连续相同的帧时,接收的帧就存入MII_RX_J0_[15:0]_[7:0](或在SONET模式下,存入MII_RX_J0[15][7:0])。 Upon receiving the same three consecutive frames, it stores the received frame MII_RX_J0_ [15: 0] _ [7: 0] (or SONET mode, stored MII_RX_J0 [15] [7: 0]). 接收的帧与这些寄存器的先期内容进行比较。 The received frame is compared with the contents of these registers in advance. 当存储了一个新值时,就设置MII_RX_J0_D delta(变化)位。 When storing a new value is set MII_RX_J0_D delta (change) position.

2.2BIP-96(B2)校验在下面B2的说明中,根据设备模式的不同(STS-3c),B2值略有变化。 2.2BIP-96 (B2) B2 is check in the following description, the devices according to the different modes (STS-3c), B2 values ​​are slightly changed. 为了说明两种情况的运行,将利用以下约定来确定模式STS-3c的要求。 To illustrate the operation of two cases, the pattern will be determined in claim STS-3c using the following convention. EOS装置1校验接收的B2字节中正确的BIP-8值。 EOS device B2 bytes received in the correct parity BIP-8 value 1. (12[3]个B2字节组合在一起形成1个BIP-96[BIP-24])。 (12 [3] of byte B2 together form a BIP-96 [BIP-24]). 除去TOH的最前3列(SONET中为SOH,SDH中为RSOH),对每帧的所有12[3]字节组计算BIP-96[BIP-24]偶数校验位。 3 before the removal of most TOH (SONET as SOH, SDH for RSOH), calculated BIP-96 [BIP-24] of the even parity bit of each frame for all 12 [3] tuples. 解扰之后对接收的数据进行计算,解扰之后将该值与下一帧的B2值进行比较。 The received data is calculated after descrambling, the value B2 is compared with the next frame after descrambling. 通过比较可以得到0到96[0到24]的不匹配(B2位错误)。 It can be obtained by comparing the 0-96 [0-24] mismatch (B2 bit errors). 每帧检测到的B2位错误数可以插入发送的M1字节。 B2 bit errors detected per frame may be inserted M1 bytes sent.

2.2.1B2错误计数ROS装置1包括一个20位的B2错误计数器,它对每个B2错误进行计数(当BIT_BLKCNT=0时)或对至少有一个B2错误的帧进行计数(当BIT_BLKCNT=1时)。 2.2.1B2 error count ROS apparatus 1 comprises a 20-bit error counter B2, it counts each error B2 (when BIT_BLKCNT = 0) or at least to a B2 frame error counts (as when BIT_BLKCNT = 1) . 当性能监控计数器被锁存时(LATCH_EVENT变成高电平),此计数器的值就由B2_ERRCNT[19:0]寄存器锁存,并清除B2错误计数器。 When the performance monitor counter is latched (LATCHEVENT the high level), the value of this counter is B2_ERRCNT [19: 0] register latch, B2 and clear error counter. 如果从LATCH_EVENT的最后上升沿开始导致至少一个B2错误时,则设置B2错误第二事件位B2ERR_SECE,采用B2错误率门限模块。 If you start led to at least a B2 error from the last rising LATCH_EVENT, setting B2 error second event bit B2ERR_SECE, the use of B2 error rate threshold module.

为了判定接收信号的误码率是否高于或低于两个规定的不同预定门限值(信号故障和信号衰减情况),EOS装置1提供了两个B2错误率门限模块。 To determine a bit error rate of the received signal is above or below a predetermined two different predetermined threshold value (signal attenuation and signal failure), EOS device 1 provides two error rate threshold module B2. 如果SF模块或SD模块判定错误率高于门限的话,就设置B2_ERR_SF或B2_ERR_SD。 If the SF or SD module determines module error rate threshold, then it is provided B2_ERR_SF or B2_ERR_SD. 如果对应的错误率位改变了值的话,也设置delta位B2_ERR_SF_D或B2_ERR_SD_D。 If the bit error rate is changed corresponding to the value, the delta bit is also set or B2_ERR_SF_D B2_ERR_SD_D. 对于每种错误率门限模块,用户可以规定一个BLOCK寄存器和2对THRESH和GROUP寄存器。 For each block error rate threshold, the user can specify a register and 2. BLOCK GROUP and THRESH register. 为了允许设置和清除状态位的滞后,每个错误率门限模块有1对THRESH和GROUP寄存器来设置状态,和1对THRESH和GROUP寄存器来清除状态。 In order to allow the hysteresis setting and clearing the status bits, each error rate threshold module has one and GROUP THRESH register set state, and a pair of THRESH and GROUP register to clear the condition. 因此用于错误率门限模块的寄存器是·当B2_ERR_SF=0,判定其是否应设置,使用:B2_BLOCK_SF[7:0],B2_THRESH_SET_SF[7:0],和B2_GROUP_SET_SF[5:0]·当B2_ERR_SF=1,判定其是否应清除,使用:B2_BLOCK_SF[7:0],B2_THRESH_CLR_SF[7:0],和B2_GROUP_CLR_SF[5:0]·当B2_ERR_SD=0,判定其是否应设置,使用:B2_BLOCK_SD[15:0],B2_THRESH_SET_SD[5:0],和B2_GROUP_SET_SD[5:0]·当B2_ERR_SD=1,判定其是否应清除,使用:B2_BLOCK_SD[15:0],B2_THRESH_CLR_SD[5:0],和B2_GROUP_CLR_SD[5:0]3.K1K2监控K1和K2字节是用于发送Line(线路)/MS AIS或RDI、及用于APS信令,通过监控该字节确定状态的改变。 Thus register error rate threshold module is • When B2_ERR_SF = 0, it is determined whether it should be set, using: B2_BLOCK_SF [7: 0], B2_THRESH_SET_SF [7: 0], and B2_GROUP_SET_SF [5: 0] · When B2_ERR_SF = 1 , determine whether it should be clear, use: B2_BLOCK_SF [7: 0], B2_THRESH_CLR_SF [7: 0], and B2_GROUP_CLR_SF [5: 0] · when B2_ERR_SD = 0, it is determined whether it should be set, using: B2_BLOCK_SD [15: 0] , B2_THRESH_SET_SD [5: 0], and B2_GROUP_SET_SD [5: 0] · when B2_ERR_SD = 1, it is determined whether it should be clear, use: B2_BLOCK_SD [15: 0], B2_THRESH_CLR_SD [5: 0], and B2_GROUP_CLR_SD [5: 0] 3.K1K2 monitoring K1 and K2 bytes are used to transmit line (line) / MS AIS or the RDI, and for APS signaling is determined by monitoring the change of state byte.

3.1 Line/MS AIS监控和LRDI的生成K2字节的3个LSB在线路/MS层上能够用作AIS或远端缺陷指示(RDI)。 3.1 Line / MS AIS monitoring and K2 bytes generated three LSB LRDI on line / MS can be used as a layer or AIS Remote Defect Indication (RDI). 如果以“111”接收到K2_CONSEC[3:0]连续帧,就设置RX_LAIS,同时RX_LAIS_OUT输出为高位;如果K2_CONSEC[3:0]连续帧以“111”接收到,就清除RX_LAIS和RX_LAIS_OUT。 If "111" is received K2_CONSEC [3: 0] consecutive frames RX_LAIS is set, the output is high while RX_LAIS_OUT; if K2_CONSEC [3: 0] in successive frames "111" is received, and cleared RX_LAIS RX_LAIS_OUT. 当RX_LAIS状态改变时,就设置RX_LAIS_D delta位。 When the state changes RX_LAIS, RX_LAIS_D delta bit is set.

3.2 Line/MS RDI监控K2字节的3个LSB也可以用于监控K2_CONSEC[3:0]是以“110”连续接收还是连续不接收,发生这种情况时,就设置或清除RX_LRDI,当RX_LRDI改变状态时就设置RX_LRDI_D。 3.2 Line / MS RDI monitoring K2 byte 3 may also be used to monitor the LSB K2_CONSEC [3: 0] is "110" does not receive a continuous or discontinuous reception, when this occurs, it is set or cleared RX_LRDI, when RX_LRDI is set RX_LRDI_D changes state.

3.3APS监控K1字节和K2字节的4个MSB是用于发送APS请求和信道数的,当在3个连续帧接收到同样的数值时,就将其写到RX_K1_[7:0]和RX_K2_[7:4]。 3.3APS monitor the K1 byte and K2 byte is used to transmit four MSB APS channel request and channel number, when receiving three consecutive frames of the same value, which will be written RX_K1_ [7: 0] and RX_K2_ [7: 4]. 然后将接收的值与寄存器原先的值进行比较,当出现一个新的12位值时,就设置RX_K1_D delta位。 Then the received value of the previous register value, when there is a new 12-bit value, the bit is set RX_K1_D delta.

检查K1字节的稳定性。 Stability check byte K1. 如果在12个连续帧中,没有3个连续帧以同样的K1字节接收到,就设置K1_UNSTAB位。 If 12 consecutive frames, there is no three consecutive frames with the same K1 byte received, the bit is set K1_UNSTAB. 当接收到连续3个相同的K1字节时就清除。 Upon receiving three consecutive identical K1 byte is cleared. 如果K1_UNSTAB改变状态,就设置K1_UNSTAB_D delta位。 If K1_UNSTAB change state is set K1_UNSTAB_D delta position. K2的3位到0位包括APS模式信息。 K2 is 3-0 comprises APS mode information. 监控K2_CONSEC[3:0]的这些位以找出连续的同样值,出现上述情况时就写到RX_K2[3:0],除非K2字节的2位和1位为“11”(表示Line/MS AIS或RDI)。 When it is written: [03] to identify those bits of the same value continuously, the above-described situation RX_K2 [3: 0] to monitor K2_CONSEC, unless the K2 byte and the two 1-bit "11" (represented by Line / MS AIS or RDI). 当写到RX_K2_[3:0]的为新值时,设置RX_K2_D delta位。 When written RX_K2_ [3: 0] to a new value, provided RX_K2_D delta position.

3个delta位MII_RX_K1_D、RX_K2_D以及MII_K1_UNSTAB_D均与APS监控有关,都能提供一个APS中断信号APS_INTB。 3 delta bit MII_RX_K1_D, RX_K2_D and MII_K1_UNSTAB_D are related to monitoring and APS, APS can provide an interrupt signal APS_INTB. 此外,这些delta位还能提供标准的累加中断信号INTB。 In addition, the delta bits also provide a standard cumulative interrupt signal INTB.

3.4S1监控监控接收到S1字节的4个LSB,在SONET模式下,MII_RX_SDH_S1=0,找出8个连续帧中的一致值,在SDH模式下,MII_RX_SDH_S1=1,找出3个连续帧中的一致值。 3.4S1 monitor monitoring the received S1 byte 4 the LSB, in SONET mode, MII_RX_SDH_S1 = 0, find the same value of 8 consecutive frames in SDH mode, MII_RX_SDH_S1 = 1, 3 consecutive frames to identify consistent value. 当这些位包括相同的同步状态消息时,就将接收的值写到RX_S1[3:0],并将接收的值与该寄存器先前的值进行比较,当存储了一个新值时,就设置MII_RX_S1_D delta位。 When these bits comprise the same synchronization status message received will writes the value RX_S1 [3: 0], and the received value is compared with the previous value of the register, when a new value is stored, is set MII_RX_S1_D delta position. S1字节也用于消息故障检测。 The S1 byte is also used for fault detection message. 如果从LATCH_EVENT的最后一个上升沿开始没有消息能够满足上述有效准则(它是否与最后接收的值相同还是不同),就设置S1第二事件位S1_FAIL_SECE。 If not started from a rising edge of the last message LATCH_EVENT effectively satisfy these criteria (if it the value of the last received the same or different), a second event bit S1 is set S1_FAIL_SECE.

3.5 M1监控M1字节说明由远程终端在接收信号中检测的B2错误数。 3.5 of M1 M1 monitoring B2 bytes to specify the number of errors detected by the remote terminal in the received signal. EOS装置1包含1个20位的M1错误计数器,当BIT_BLKCNT=0时,就计数由M1指示的每个错误;当BIT_BLKCNT=1时,就计数以M1接收的不等于0的每一帧。 EOS device M1. 1 comprises an error counter 20, and when BIT_BLKCNT = 0, the count on each error indicated by the M1; when BIT_BLKCNT = 1, it is counted to M1 is not equal to the received 0 of each frame. 当MII_RX_SIG_MODE=1时,BIT_BLKCNT=0的M1的有效值范围是0到96;其他任何值都解释为0错误。 When MII_RX_SIG_MODE = 1, BIT_BLKCNT = M1 valid range of 0 is 0 to 96; any other value 0 is interpreted as an error. 当RX_SIG_MODE=0和BIT_BLKCNT=0时,M1的有效值范围是0到24;任何其他值都解释为0错误。 When RX_SIG_MODE = 0 and BIT_BLKCNT = 0, the range of valid values ​​M1 is from 0 to 24; any other value 0 is interpreted as an error. 当性能监控计数器被锁存时,该计数器的值是由M1_ERRCNT[19:0]寄存器锁存,并且清除M1错误计数器。 When the performance monitor counter is latched by the value of the counter is M1_ERRCNT [19: 0] register latch, and clears the error counter M1.

如果从LATCH_EVENT最后的上升沿开始已经有至少1个接收M1错误指示的话,就设置M1错误第二事件位M1 ERR SECE。 If you already have at least one reception error indication M1 from the last start rising LATCH_EVENT, then it is wrong to set a second event digit M1 M1 ERR SECE.

4.传送开销分离(drop)TOH/SOH分离模块输出接收的E1、F1和E2字节,以及2个串行DCC信道。 4. The transport overhead separator (drop) TOH / SOH separation module receives the output of E1, F1 and E2 bytes, DCC and two serial channels.

4.1指令线(E1和E2)和段用户信道(F1)3个串行输出MII_RX_E1_DATA、MII_RX_E2_DATA和MII_RX_F1_DATA包含接收的E1、E2和F1字节的值,同时提供单个带缺口的64kHz时钟参考输出(MII_RX_E1E2F1_CLK),在RX_FRAME_OUT上升沿之后,E1、E2和F1字节的MSB出现在第一个64kHz时钟周期(带缺口)。 4.1 instruction line (E1 and E2) and User Channel section (F1). 3 serial output MII_RX_E1_DATA, MII_RX_E2_DATA received and MII_RX_F1_DATA comprising E1, E2 and F1 byte value, while providing a single notched 64kHz clock reference output (MII_RX_E1E2F1_CLK ), after the rising edge RX_FRAME_OUT, E1, E2 and F1 bytes MSB appear in the first clock cycle 64kHz (with notch).

4.2数据通信信道,DCC,(D1-D12)TOH/SOH中定义了两个DCC。 4.2 Data communication channel, DCC, (D1-D12) TOH / SOH defines two DCC. 段/再生段DCC采用D1、D2和D3字节建立1个带缺口的192kb/s的信道,线路/复接段DCC采用D4到D12字节建立1个带缺口的576kb/s的信道。 Section / regenerator section DCC using D1, D2 and D3 bytes establishing a notched 192kb / s channel, the line / multiplexing section DCC using D4-D12 bytes to establish a 576kb / s notched channel. TOH/SOH分离模块通过2个串行信道输出DCC数据RX_SDCC_DATA和RX_LDCC_DATA。 TOH / SOH separation module and outputs DCC data RX_SDCC_DATA RX_LDCC_DATA by two serial channels. 这些信道与输出MII_RX_SDCC_CLK和MII_RX_LDCC_CLK同步,DCC数据输出在RX_SDCC_CLK和RX_LDCC_CLK的下降沿改变。 These channels are aligned with the output and MII_RX_SDCC_CLK MII_RX_LDCC_CLK, DCC output data changes on the falling edge of RX_SDCC_CLK and RX_LDCC_CLK.

5.指针状态判定通过检查H1-H2字节来判定指针状态,建立STS-3c/AU-4接收指针态。 The pointer state determination determined by checking the status of the pointer bytes H1-H2 established STS-3c / AU-4 pointer receiving state.

5.1状态变化规则在下列指针状态判定说明中,依据设备的模式(STS-3c),数目略有变化。 5.1 the transition rule is determined in the following description pointer state, the device according to the mode (STS-3c), a slight change in the number. 为了说明两种情况的运行,将利用以下约定来确定模式(STS-3c)的要求:第一对H1-H2字节包含STS-3c/AU-4指针,监控该字节对,它们可认为是下列3种状态中1种:·正常(NORM=00)·告警指示信号(AIS=01)·指针丢失((LOP=10)剩余的11[2]对H1-H2字节用于监控正确级联指示。它们可认为是下列3种状态中1种: To illustrate the operation of the two cases, the following conventions will be used to determine the mode (STS-3c) requirements: a first pair of bytes H1-H2 comprising STS-3c / AU-4 pointer bytes monitor this, they may be considered the following is one kind of three states: · normal (NORM = 00) · alarm indication signal (AIS = 01) · loss of pointer ((LOP = 10) the remaining 11 [2] H1-H2 bytes for monitoring correct cascade indicating that they can be considered the following three states one kind of:

·级联(CONC=11)·告警指示信号(AISC=01)·指针丢失(LOPC=10)各自的状态存储于MII_PTR_STATE_[1:12]_[1:0][MII_PTR_STATE_[1:3]_[1:0]],这里MII_PTR_STATE_[i]_[1:0]表示第i对H1-H2字节的状态。 · Cascade (CONC = 11) · Alarm Indication Signal (AISC = 01) · loss of pointer (LOPC = 10) stored in the respective states MII_PTR_STATE_ [1:12] _ [1: 0] [MII_PTR_STATE_ [1: 3] _ [1: 0]], where MII_PTR_STATE_ [i] _ [1: 0] indicates the i-th state H1-H2 bytes. 然后,合并各对单独的H1-H2字节,确定STS-3c/AU-4指针状态。 Then, for each separate combined H1-H2 bytes, and determine STS-3c / AU-4 pointer state.

5.2 STS-3c/AU-4指针状态EOS装置1提供寄存器状态位MII_RX_PAIS和MII_RX_LOP,用于指示接收的STS-3c/AU-4指针的指针状态,它们可能为3种状态之一:·正常(MII_RX_PAIS=0和RX_LOP=0)-MII_PTR_STATE_[1]_[1:0]为NORM(00),所有其他PTR_STATE_[i]_[1:0]为CONC(11)。 5.2 STS-3c / AU-4 pointer state EOS device 1 and provides the status is MII_RX_PAIS MII_RX_LOP, a pointer for indicating the state of the received STS-3c / AU-4 pointer, which may be one of three states: • Normal ( MII_RX_PAIS = 0 and RX_LOP = 0) -MII_PTR_STATE_ [1] _ [1: 0] as NORM (00), all other PTR_STATE_ [i] _ [1: 0] is CONC (11).

·通道/AU AIS(MII_RX_PAIS=1和RX_LOP=0)-所有PTR_STATE_[i]_[1:0]为AIS或AISC(01)。 • Channel / AU AIS (MII_RX_PAIS = 1 and RX_LOP = 0) - All PTR_STATE_ [i] _ [1: 0] for the AIS or AISC (01).

·指针丢失(MII_RX_PAIS=0和MII_RX_LOP=1)-所有其他情况(PTR_STATE_[i]_[1:0]值不能满足正常或通道/AU AIS标准)。 · Loss Of Pointer (MII_RX_PAIS = 0 and MII_RX_LOP = 1) - all other cases (PTR_STATE_ [i] _ [1: 0] value fails to meet the normal or channel / AU AIS standard).

MII_RX_PAIS和MII_RX_LOP信号提供通道远程故障指示(PRDI)。 MII_RX_PAIS and MII_RX_LOP remote fault indication signal path (PRDI). 通过MII_RX_PAIS_D和MII_RX_LOP_D delta位指示状态位的改变。 It indicates a change status bit by bit MII_RX_PAIS_D and MII_RX_LOP_D delta.

6.指针解释第一H1-H2字节对被解释为应用对SPE/VC的开始定位。 6. explaining the first pointer bytes H1-H2 starts the application be construed as positioning of SPE / VC's. 指针解释规则如下:1.在正常运行期间,指针定位SPE/VC的开始。 Pointer interpretation rules are as follows: 1. During normal operation, the pointer positioning start SPE / VC's.

2.忽略当前接收到的指针的任何变化,除非连续3次接收到一个一致的新指针值,或者它先于规则3、4或5中的任何一条。 2. ignores any change in the currently received pointers, any one of the received three times in succession unless a consistent new pointer value, or it prior to the rule 3, 4 or 5. 任何连续3次接收到一致的新指针值优先于规则3或4。 Any received three times in succession to a consistent new pointer value precedence rules 3 or 4.

3.当MII_RX_SDH_PI=0,如果4位NDF位中至少3位匹配禁止指示(0110)以及10位指针值位中至少8位匹配当前接收到的其I位反转的指针,则指示一个正调整。 3. When MII_RX_SDH_PI = 0, if four NDF bits match disable indication at least three (0110), and 10-bit pointer value of at least 8 bits match pointer I which is currently received inverted, a positive justification is indicated . 认为跟在H3字节后的字节是正填充字节,当前接收到的指针值加1(模783)。 With pointer value that the byte after byte H3 is a positive stuff byte, the currently received plus 1 (modulo 783).

当MII_RX_SDH_PI=1,如果4位NDF位中至少3位匹配禁止指示(0110),指针值I-位中3位或更多位以及指针值D-位中2位或更少的位匹配当前接收到的其所有位反转的指针,并且接收到的SS-位是10或MII_RX_SS_EN=0,则指示一个正调整。 When MII_RX_SDH_PI = 1, if the four NDF bits match disable indication at least three (0110), I- pointer value bits and 3 bits or more bits in the pointer value D- two or fewer bits match the current received to all pointer bit inversion, and the received bits are 10 or SS- MII_RX_SS_EN = 0, it indicates a positive justification. 认为跟在H3字节后的字节是正填充字节,当前接收到的指针值加1(模783)。 With pointer value that the byte after byte H3 is a positive stuff byte, the currently received plus 1 (modulo 783).

4.当MII_RX_SDH_PI=0,如果4位NDF位中至少3位匹配禁止指示(0110)以及10位指针值位中至少8位匹配当前接收到的其D位反转的指针,则指示一个负调整。 4. When MII_RX_SDH_PI = 0, if four NDF bits match disable indication at least three (0110), and 10-bit pointer value of at least 8 which matches the currently received D bit inversion pointer, a negative justification is indicated . H3字节被认为是负填充字节(它是SPE的一部分),当前接收到的指针值减1(模783)。 H3 byte is considered to be negative stuff byte (which is part of SPE), the currently received pointer value is decremented by 1 (modulo 783).

当MII_RX_SDH_PI=1,如果4位NDF位中至少3位匹配禁止指示(0110),指针值D-位中3位或更多位以及指针值I-位中2位或更少的位匹配当前接收到的其所有位反转的指针,并且接收到的SS-位是10或MII_RX_SS_EN=0,则指示一个负调整。 When MII_RX_SDH_PI = 1, if the four NDF bits match disable indication at least three (0110), D- pointer value bits and 3 bits or more bits in the pointer value I- two or fewer bits match the current received All bit-reversed to its pointer, and the received bits are 10 or SS- MII_RX_SS_EN = 0, a negative justification is indicated. H3字节被认为是负填充字节(它是VC的一部分),当前接收到的指针值减1(模783)。 H3 byte is considered to be negative stuff byte (which is part of the VC), the currently received pointer value is decremented by 1 (modulo 783).

5.当MII_RX_SDH_PI=0,如果4位NDF位中至少3位匹配禁止指示(1001),并且指针值在0到782之间,则接收到的指针替换当前接收到的指针值。 5. When MII_RX_SDH_PI = 0, if four NDF bits match disable indication at least three (1001), and replaces the currently received pointer value pointer value between 0 to 782, the received pointer.

当MII_RX_SDH_PI=1,如果4位NDF位中至少3位匹配禁止指示(1001),指针值在0到782之间,并且接收到的SS-位是10或MII_RX_SS_EN=0,则接收到的指针替换当前接收到的指针值。 When MII_RX_SDH_PI = 1, if the four NDF bits match disable indication at least three (1001), the pointer value between 0 to 782, and the received bits are 10 or SS- MII_RX_SS_EN = 0, then the received pointers are replaced current received pointer value.

利用这些指针解释规则,指针解释器模块确定SPE/VC净荷和POH字节的位置。 Using these rules pointer interpreter pointer interpreter module determines SPE / VC payload and POH byte location.

6.1指针处理关于在EOS装置1中实现指针跟踪算法,请参考[G.783]和[GR-253]中的转换定义。 About 6.1 pointer processing pointer tracking algorithm implemented in an EOS device, please refer to [G.783] and [GR-253] in the transform definition. 指针跟踪状态机是基于ITU-T建议确定的指针跟踪状态机,它对Bellcore和ANSI标准一样有效。 Pointer tracking state machine is determined based on ITU-T Recommendation pointer tracking state machine, as it effectively Bellcore and ANSI standards. 在Bellcore模式中,不出现从AIS到LOP的状态机转换(即通过设置BELLCORE位设置成逻辑1)。 In the Bellcore mode, it does not appear from AIS to LOP state machine transitions (i.e., by setting the bit to a logical 1 provided BELLCORE).

EOS装置1使用了四个指针跟踪状态机,每个AU-4/STS-3c用一个。 EOS device 1 uses four pointer tracking state machine, each AU-4 / STS-3c with a. 指针跟踪采用H11和H21字节,该指针从H1n和H2n字节的级联中提取,解释如下: Pointer tracking using H11 and H21 bytes, the pointer is extracted from the cascade and H1n H2n bytes, it is explained as follows:

N=新数据标志位,在有效时=1001或0001/1101/1011/1000,在正常或失效时,它等于0110或1110/0010/0100/0111(即,可容忍单比特错误)。 N = new data flag, or when a valid 1001 = 0001/1101/1011/1000, normal or failure, it 1110/0010/0100/0111 or equal to 0110 (i.e., single-bit errors can be tolerated).

SS=指针跟踪状态机解释中的大小位,如果有效,通过将BELLCORE控制位设置为0。 SS = size in bits of the pointer interpretation machine tracking state, if effective, BELLCORE by the control bit is set to 0. 当BELLCORE设置为1时忽略这些位,但当它设置为0时,这些位为10。 When BELLCORE ignore these bits set to 1, but it is set to 0, which is 10 bits.

I=增加位,定义为H1n的位7以及H2n的位1、3、5和7。 I = increased bits, defined as bit 7 and H1n H2n bits 3, 5 and 7.

D=降低位,定义为H1n的位8以及H2n的位2、4、6和8。 D = reducing the bit, the bit is defined as H1n H2n 8 and 4, 6 and 8 bits.

负调整:反转的5个D-位,接收多数规则。 Negative justification: D- inverted five bits received majority rule. 通过将OR#Conf3中的正ITU位(Just ITU bit)设置为0,可启动[GR-253]的O3-92中10个对象中的8个。 8 O3-92 OR # Conf3 by the ITU n bits (Just ITU bit) is set to 0, the start [GR-253] of 10 objects.

正调整:反转的5个I-位,接收多数规则。 Positive justification: I- inverted five bits received majority rule. 通过将OR#Conf3中的正ITU位(Just ITU bit)设置为0,可启动[GR-253]的O3-92中10个对象中的8个。 8 O3-92 OR # Conf3 by the ITU n bits (Just ITU bit) is set to 0, the start [GR-253] of 10 objects.

对STM-1/STS-3c运行模式,指针为一个二进制值,范围为0到782(十进制)。 For STM-1 / STS-3c operation mode, a pointer to a binary value, in the range of 0 to 782 (decimal). 它是一个源自H1字节的两个最低有效位的10-位值,与级联的H2字节一同,形成一个偏离H3字节位置3个字节的偏置字段。 The least significant two bits of the 10-bit value which is derived from a H1 byte and H2 byte cascaded together, forming a three byte position offset from H3 byte offset field. 例如,对STM-1信号,指针值为0表示VC-4在H3字节后3个字节位置处开始,而偏置87表示VC-4从K2字节后3个字节开始。 For example, for STM-1 signals, the pointer value 0 indicates the start of the VC-4 bytes after the H3 byte positions 3, 87 represents a biased VC-4 starts from the K2 bytes 3 bytes.

在STM-4/STS-12模式有4个字节-交错AU-4,因此有4个H1/H2字节对用于确定它们各自VC-4的开始(即,J1字节位置)。 In the STM-4 / STS-12 mode 4 bytes - interleaved AU-4, so there are four H1 / H2 bytes are used for determining the start of each VC-4 (i.e., J1 byte position). 在这种情况下,4个指针跟踪状态机的运行等同于运行4×STM-1/STS-3c。 In this case, four runs pointer tracking state machine equivalent to running the 4 × STM-1 / STS-3c.

在处理STS-12c/STM-4c时,宏1的指针跟踪状态机用于定位VC-4-4c的开始。 When processing STS-12c / STM-4c, the pointer tracking state machine for positioning a macro start of VC-4-4c. 使用H11和H21字节进行指针跟踪,指针从H11和H21字节级联中提取出来,指针解释如上面所述。 Using H11 and H21 track pointer bytes pointer bytes extracted from the H11 and H21 cascade out of the pointers as explained above. 但形成的偏置是一个12字节的计数值,其值从H3字节位置开始算起。 However, the bias is formed by a 12-byte count value which value H3 byte position from the start date. 例如,对STM-12c信号,指针值为0表示VC-4在H3字节后12个字节位置处开始,而偏置87表示VC-4从K2字节后12个字节开始。 For example, a signal STM-12c, the pointer value of 0 indicates VC-4 starts at the byte after the H3 byte positions 12, 87 represents a biased VC-4 starts from byte 12 byte K2. 在相应宏(宏2-4)中也检查级联指示字节,根据[G.783]附件C中的每个状态机对应于LOP和HPAIS进行监控。 Also check byte concatenation indication in the respective macro (macro 2-4), corresponding to the LOP and monitored according HPAIS [G.783] Annex C of each state machine. 下面的状态图说明了级联指示符的状态转换。 The state diagram below illustrates the state transition indicator cascade. 转换定义请参考[G.783]。 Refer to transform definition [G.783].

此外,8位计数器用来记录正和负调整事件,以及NDF事件。 Further, the 8-bit counter is used to record the positive and negative justification event, and NDF events. 提供状态位用来指示负调整、正调整、NDF、无效指针、新指针和级联指示的检测。 It provides status bit indicates negative justification, positive justification, NDF, detecting invalid pointer, the new pointer and the concatenation indication. 当进入上图中的LOP或LOPC态时,将在相关OR#IRQ2寄存器中设置LOP中断请求位。 When entering the image above or LOPC state LOP, LOP interrupt request bit set in the associated register OR # IRQ2. 同样,如果进入了AIS或AISC态,将设置相关的HPAIS中断请求。 Similarly, if the AIS or into AISC state, to set the relevant HPAIS interrupt request.

处理完指针后,连接指针处理单元10和解扰单元11的FIFO单元(未示出)将SDH/SONET帧(如155.520Mb/s)转换成LAPS帧(如155.520Mb/s),用PLL来完成该动作。 After processing the pointer, the pointer 10 and the descrambling unit connected to the processing unit 11 of the FIFO unit (not shown) SDH / SONET frame (e.g. 155.520Mb / s) converted to a LAPS frame (e.g. 155.520Mb / s), to complete the PLL the action.

7.通道开销监控POH(通道开销)监控模块由J1、B3、C2和G1监控组成。 7. POH path overhead monitoring (POH) from the monitoring module J1, B3, C2 and G1 monitoring composition. 这些通道开销字节用于监控状态中的错误或变化。 These overhead byte used for error monitoring or change state.

7.1通道跟踪(J1)捕获/监控通过插入J1字节,EOS装置1支持两种通道跟踪(J1)捕获方法。 7.1 Tracking channel (J1) capture / monitor by insertion of the J1 byte, EOS apparatus 1 supports two channel trace (J1) capture method. 第一种主要用于SONET,在STS-3c/AU-4中捕获64个连续的J1字节。 Mainly used for a first SONET, capturing 64 consecutive J1 byte in STS-3c / AU-4 in. 第二种用于SDH,查找重复的16个连续的J1字节模式。 A second SDH, find duplicate 16 consecutive J1 byte pattern. 当在3个连续事件中检测到一致的16字节模式时,J1模式存储在指定的寄存器中。 When detecting the same byte pattern 16 in three successive events, J1 pattern stored in the specified register.

7.1.1SONETJ1捕获当MII_RX_SDH_J1=0(SONET模式),EOS装置1能提供捕获通道跟踪消息样本。 When capturing 7.1.1SONETJ1 MII_RX_SDH_J1 = 0 (SONET mode), EOS capture apparatus 1 can provide a path trace message type. 当J1_CAP从0转换成1,EOS装置1从特定分机连续捕获64个J1字节,将它们写到MII_RX_J1_[63:0]_[7:0]。 When J1_CAP transition from 0 to 1, the EOS from a particular apparatus 1 continuously captures extension 64 the J1 byte, write them MII_RX_J1_ [63: 0] _ [7: 0].

SONET中没有定义通道跟踪帧结构,但GR-253确实建议一个64字节的序列,该序列由一串ASCII字符组成,空字符(00)填充了62字节,结束为<CR>(0D)和<LF>(0A)字节。 SONET is not defined in the channel tracking frame structure, the GR-253 do suggest a sequence of 64 bytes, the sequence is a string of ASCII characters, the null character (00) is filled with 62 bytes, the end of & lt; CR & gt; (0D ) and & lt; LF & gt; (0A) bytes. 如果设置了J1_CRLF位,则EOS装置1捕获在J1字节位置中所接收的以{0A,0D}结束的第一个64字节字符串。 If J1_CRLF bit set, the EOS device 1 to capture {0A, 0D} 64 a first end of the string in the byte J1 byte positions received. 如果J1_CRLF=0,EOS装置1捕获接下来的64字节的J1字节,不考虑它们的内容。 If J1_CRLF = 0, EOS device captures the next 64 bytes J1 Byte 1, without regard to their contents. 一旦完成捕获,EOS装置1设置J1_CAP_E事件位。 Once captured, EOS event bit J1_CAP_E apparatus 1 is provided.

7.1.216字节J1监控如果MII_RX_SDH_J1=1(一般用于SDH模式),J1字节可望包含一个重复的16字节包括PAPI的通道跟踪帧。 If the J1 byte monitor 7.1.216 MII_RX_SDH_J1 = 1 (mode is generally used for SDH), J1 byte is expected to contain a repeating 16-byte frame includes a channel tracking PAPI. 在这种模式中,不使用J1_CAP、J1_CRLF和J1_CAP_E位。 In this mode, not used J1_CAP, J1_CRLF and J1_CAP_E bits. J1监控包括自动跟踪16字节通道跟踪帧开始、检查接收通道跟踪帧值以找出与3个连续帧匹配一致的值。 Monitoring includes the automatic tracking J1 Path Trace bytes 16 beginning frame, checks the received path trace value of the frame to find the values ​​match with three consecutive frames match. 当接收到一个一致的帧值时,把它写到MII_RX_J1_[15:0]_[7:0]。 When receiving a frame consistent value, it writes MII_RX_J1_ [15: 0] _ [7: 0]. 通道跟踪帧的第一个字节(它包括帧起始标志)写到MII_RX_J1_[15]_[7:0]。 A path trace byte of the first frame (which includes a frame start flag) is written MII_RX_J1_ [15] _ [7: 0].

成帧.除帧起始标志字节的MSB外,所有通道跟踪帧字节的最高有效位均为0。 Framing. In addition to the frame start flag byte MSB, all path trace byte frames the most significant bit are zero. J1监控器成帧器搜索15个连续J1字节,该字节最高有效位中具有0,后接最高有效位中具有1的J1字节。 J1 framer monitor 15 consecutive search J1 byte, the most significant bit having 0, followed by the most significant bit of byte 1 having J1. 一旦搜索到这种模式,成帧器进入帧内,此时J1_OOF=0。 Once this search mode, the framer enters the frame, this time J1_OOF = 0. 一旦J1监控器成帧器为内帧,它便一直留在帧内直到接收到至少有1个最高有效位(MSB)位错误的3个连续通道跟踪帧中。 Once J1 framer within the monitor frame, it will remain at least until it receives the frame a most significant bit (MSB) bit error tracking channels 3 consecutive frames. (在SONET模式,J1帧指示保留在内帧状态,J1_OOF=0)。 (In the SONET mode, J1 frame indicates a frame reservation in state, J1_OOF = 0). 如果J1_OOF状态改变,则设置J1_OOF_D delta位。 If the state change J1_OOF, J1_OOF_D delta bit is set.

模式接收和比较.一旦在帧内,J1监控模块查找3个连续的16字节的通道跟踪帧。 Receiving and comparing pattern. Once the frame, J1 monitoring module searches for 3 consecutive 16 byte path trace frames. 当接收到3个连续相同的帧时,接收的帧就存入MII_RX_J1_[15:0]_[7:0]。 Upon receiving the same three consecutive frames, it stores the received frame MII_RX_J1_ [15: 0] _ [7: 0].

接收的帧与这些寄存器的先期内容进行比较,当存储了一个新值时,就设置RX_J1_D的delta位。 The received frame is compared with the contents of these registers in advance, when a new value is stored, the bit is set RX_J1_D the delta.

7.2.BIP-8(B3)校验EOS装置1检查接收到的B3字节中正确的BIP-8值。 7.2.BIP-8 (B3) EOS calibration apparatus 1 check the correct BIP-8 value received B3 bytes. 通过对每帧SPE/VC(包括POH)中所有位计算BIP-8的偶数奇偶校验位。 By the even parity BIP-8 is calculated for all bits in each frame of the SPE / VC (including POH). 然后这些值与下一帧中接收到的B3值进行比较。 These values ​​are then compared with the value of the received B3 in the next frame. 比较的结果可能会是0到8不匹配(B3位错误),将该值插入到发送端G1字节中。 The result of the comparison may be 0-8 mismatch (B3 bit error), the value into the transmit terminals G1 byte.

EOS装置1包含一个16位B3错误计数器,该计数器对每个B3位错误(如果BIT_BLKCNT=0)或者至少有一个B3位错误(如果BIT_BLKCNT=1)的每个帧进行计数。 EOS device 1 comprises a 16-bit error counter B3, B3 of the counter for each of the bit error (if BIT_BLKCNT = 0) or there is at least one bit error B3 (if BIT_BLKCNT = 1) for each frame count. 当性能监控计数器被锁定时(LATCH_EVENT向高位转换),该计数器的值锁定到B3ERRCNT_[15:0]寄存器,清除B3错误计数器。 When the performance monitor counter is locked (LATCHEVENT conversion to high), the value of the counter is locked to B3ERRCNT_ [15: 0] register, clears the error counter B3. 如果自LATCH_EVENT最后上升沿开始已至少有一个B3错误,则设置B3错误二次事件位B3ERR_SECE。 If you start from the last rising LATCH_EVENT already have at least a B3 error, the error set B3 secondary event bit B3ERR_SECE.

7.3.信号标签(C2)监控对接收到的C2字节进行监控,从而可确认接收到正确的净荷类型。 7.3 Signal Label (C2) monitoring the received byte C2 monitoring, thereby acknowledging receipt of the correct type payload. 在5个连续帧上接收到一致的C2值时,将接收到的值写到MII_RX_C2[7:0]中。 Upon receiving the same value C2 in five consecutive frames, the received value is written MII_RX_C2 [7: 0] in. 当接收到一个新的C2值,设置MII_RX_C2D的delta位。 When receiving a new value of C2, delta bit is set to MII_RX_C2D.

接收到的C2的预期值留在EXP_C2[7:0]中。 Expected value C2 received remain in EXP_C2 [7: 0] in. 如果当前接收到的值与预期值不匹配,接收到的值也不符合以下条件则将净荷标签不匹配寄存器位MII_RX_PLM设置为高位:●全部为0,没准备的标签;●01(十六进制),准备的非特定标签;●FC(十六进制),有净荷缺陷标签;●FF(十六进制),保留标签。 If the currently received does not match the expected values, the received value does not meet the following conditions will not match the payload tag register bit set high MII_RX_PLM: ● all 0, unprepared label; ● 01 (sixteen hex), prepared in a non-specific label; ● FC (hex), the label has a defect payload; ● FF (hex), reservation label.

如果当前接收到的值是无标签、全部为零,EXP_C2! If the current value received is untagged, all zeros, EXP_C2! =00(十六进制),则未准备的寄存器位(Unequipped registerbit)MII_RX_UNEQ设置为高位。 = 00 (hex) is not ready bit register (Unequipped registerbit) MII_RX_UNEQ set to high.

MII_RX_PLM和MII_RX_UNEQ信号供通道RDI在发送端插入。 MII_RX_PLM signal supply path and MII_RX_UNEQ RDI inserted at the transmitting end. 当MII_RX_PLM或MII_RX_UNEQ改变其状态时,设置MII_RX_PLM或MII_RX_UNEQ delta位。 When MII_RX_PLM MII_RX_UNEQ or change its state, or provided MII_RX_PLM MII_RX_UNEQ delta position.

7.4.通道状态(G1)监控G1监控包括通道REI监控和通道RDI监控。 7.4 Channel Status (G1) includes a channel monitor to monitor G1 REI monitoring and monitoring channel RDI.

7.4.1.通道REI监控通道状态字节的位1到位4(4个最高有效位)指示远程终端在其接收到的信号中检测到的B3错误数。 7.4.1. REI channel monitoring channel status byte 4 bit 1 bit (most significant 4 bits) indicates the remote terminal detects that its received signal B3 errors. 只有在0到8间的二进制值是合法的。 Only binary values ​​0-8 are legitimate. 如果接收到的值大于8,将其解释为0错误(正如GR-253和ITU-T建议G.707所规定的一样)。 If the received value is greater than 8, an error will be interpreted as 0 (as GR-253 and ITU-T Recommendation as defined in G.707). EOS装置1包含一个16位的G1错误计数器,它计算G1指示的每个错误(如果BIT_BLKCNT=0)、或者接收到的头4个G1位不等于0的每个帧(如果BIT_BLKCNT=1)。 EOS device 1 comprises a 16-bit error counter G1, each error (if BIT_BLKCNT = 0), or received in the first four bits G1 of each frame is not equal to 0 (if BIT_BLKCNT = 1) which indicates the calculated G1. 当性能监控计数器被锁定时(LATCH_EVENT转换成高位),该计数器的值赋给G1_ERRCNT[15:0]寄存器,清空G1错误计数器。 When the performance monitor counter is locked (LATCHEVENT converted to high), the counter value assigned G1_ERRCNT [15: 0] register, G1 clear error counter.

如果自LATCH_EVENT的最后上升沿以来已至少有一个接收到的G1错误指示,则设置G1错误第二次事件位G1ERR_SECE。 If there is at least a G1 error indication received since the last rising LATCH_EVENT, setting G1 error second event bit G1ERR_SECE.

7.4.2通道RDT监控如果MII_RX_PRDI5=1,则EOS装置1可监控G1的第5位(RDI-P指示符);如果MII_RX_PRDI5=0,则可监控G1的第5、6和7位(增强RDI-P指示符)。 7.4.2 If the monitoring channel RDT MII_RX_PRDI5 = 1, the apparatus 1 can monitor G1 EOS bit 5 (RDI-P indicator); if MII_RX_PRDI5 = 0, 5, 6, 7 can be monitored and G1 (enhanced RDI -P indicator). 监控过程包括检查G1_CONSEC[3:0]监控位的连续接收值中完全相同的值。 Supervisory process comprising checking G1_CONSEC: continuously received values ​​[30] to monitor the position of the same value. 当接收到完全相同的值,G1个5、6和7位写到MII_RX_G1[2:0]。 Upon receiving the same value, G1 5,6 and 7 written MII_RX_G1 [2: 0]. 接收值与该寄存器前面的值进行比较(所有3位都被写到,但如果MII_RX_PRDI5=1,只将G1的第5位和MUU_RX_G1[2]进行比较)。 Received value is compared with the value of the preceding register (all three bits are written, but if MII_RX_PRDI5 = 1, only the bit 5 of G1 and MUU_RX_G1 [2] are compared). 当存储一个新值时,设置MII_RX_G1_D delta位。 When storing a new value, provided MII_RX_G1_D delta position.

7.5.其他POH字节EOS装置1对POH剩下的其他字节不予监控。 7.5. Other EOS POH bytes of POH monitor apparatus 1 not the other remaining bytes. 这些字节包括通道用户信道(F2)、位置指示符(H4)、通道增长/用户信道(Z3/F3)、通道增长/通道APS信道(Z4/K3)以及前后连接监控(Z5/N1)字节。 These bytes include a channel user channel (F2), a position indicator (H4), channel increase / user channel (Z3 / F3), the channel increase / channel APS channel (Z4 / K3) and the front and rear connection monitoring (Z5 / N1) word section.

8.接收净荷解扰从SONET/SDH信号中提取净荷后,净荷数据用自同步X43+1解扰器进行解扰。 8. After receiving a payload from the payload extracted descrambling SONET / SDH signals, the payload data X43 + 1 self-synchronous descrambler for descrambling. 在所有模式中,寄存器MII_RX_DSCR_INH控制解扰器的运行。 In all modes, the operation of the control register MII_RX_DSCR_INH descrambler. 当MII_RX_DSCR_INH=0(缺省),解扰器正常工作。 When MII_RX_DSCR_INH = 0 (default), the descrambler work. 当MII_RX_DSCR_INH=1,解扰器禁止工作。 When MII_RX_DSCR_INH = 1, the descrambler prohibition of work.

EOS装置1提供一个基于如下生成多项式X43+1的自同步解扰器。 EOS generating apparatus 1 provides the following based on a self-synchronizing descrambler polynomial X43 + 1 is.

9.接收LAPS处理在此处SPE已从SONET/SDH帧中提取,然后进入LAPS处理器做进一步的处理。 The receiving process LAPS herein SPE extraction from SONET / SDH frame, and then enter the LAPS processor for further processing. 在EOS模式下(MII_RX_EOS=1),LAPS处理过程为从SPE中提取LAPS包/帧。 In the EOS mode (MII_RX_EOS = 1), LAPS LAPS processing to extract the packets / frames from the SPE.

9.1 LAPS成帧器在EOS模式下(MII_RX_EOS=1),通过识别帧起始/结束的标志序列(0x7e),从SPE净荷中提取LAPS帧。 9.1 LAPS EOS framer in mode (MII_RX_EOS = 1), by identifying a frame start / marker sequence (0x7E) end extracted from the SPE payload LAPS frame.

EOS装置1检查净荷中的每个八位组,当位模式为0x7e的八位组被检查到时,EOS装置1就认为这是1个包的起始/结束,然后检查标志序列后的八位组。 EOS inspection apparatus 1 for each octet in the payload, after the bit pattern is to be inspected octet 0x7e, the EOS device 1 which is considered the start / end of a packet, and then checks the sequence flag octets. 如果仍为0x7e,则认为它们是用于填充包间间隙的标志序列,并将其丢弃。 If still 0x7E, they are considered a marker sequence gap between the padding packet, and discards it. 跟随起始标志序列、且不等于0x7e的第一个八位组被认为是LAPS帧的第一个八位组。 Following the start flag sequence octet 0x7e not equal to the first group is considered to be the first octet LAPS frame. 在帧起始标志之后,EOS装置1继续检查净荷的每个八位组,查找标志序列。 After the frame start flag, the EOS device 1 continue to check each octet of the payload, the sequence for the logo. 如果找到了位模式0x7e位置,且其前面的八位组为控制转义码(0x7d),则此帧中止;否则,就认为是当前帧的正常结尾。 If the bit pattern 0x7e find the location, and the front of Control Escape octet (0x7D), the frame is aborted; otherwise, it is normal that the end of the current frame. 在FCS字段的终止被禁止的特殊情况下,必须在帧信号之间检测最小量为2个标志序列。 In special cases the FCS field termination is prohibited, the signal must be detected between frames, a minimum of two flag sequences.

9.2透明字节填充的删除9.3.1 EOS模式在EOS模式(MII_RX_EOS=1),在LAPS帧之后,EOS装置1将透明字节填充过程反过来,以恢复原始包信息流。 9.2 9.3.1 deletion transparent byte stuffing mode in EOS EOS mode (MII_RX_EOS = 1), after LAPS frame, transparent EOS device 1 byte stuffing process, in turn, to restore the original packet stream. FIFO下溢字节序列是由发送端在FIFO下溢过程中插入的,如果MII_RX_EOS_FIFOUNDR_MODE=1,则在透明处理过程中需要检测出,并删除。 FIFO underflow byte sequence is inserted by the sender during the underflow of the FIFO, if MII_RX_EOS_FIFOUNDR_MODE = 1, then the transparent processing necessary to detect and remove. 该缺省值被禁止:MII_RX_EOS_FIFOUNDR_MODE=0。 The default value is disabled: MII_RX_EOS_FIFOUNDR_MODE = 0. 特殊的FIFO下溢字节码可以利用寄存器MII_RX_EOS_FIFOUNDR_BYTE[7:0]编程。 Overflow FIFO bytecodes can use the special register MII_RX_EOS_FIFOUNDR_BYTE [7: 0] programming.

9.3.2下溢字节删除在EOS模式下,如果MII_RX_EOS_FIFOUNDR_MODE=1,匹配FIFO下溢字节(MII_RX_EOS_FIFOUNDR_BYTE[7:0])的字节如果其后没有紧跟控制转义码(0x7d)则被丢弃。 9.3.2 Remove the underflow byte mode in EOS, if MII_RX_EOS_FIFOUNDR_MODE = 1, match underflow byte (MII_RX_EOS_FIFOUNDR_BYTE [7: 0]) if the subsequent byte FIFO control is not immediately escape code (0x7D) were throw away.

9.4错误帧在EOS模式下(MII_RX_EOS=1),利用1个特殊的字节编码(0x7d7e)来指明该帧已被中止。 9.4 Error Frame mode in EOS (MII_RX_EOS = 1), using a special byte code (0x7d7e) to indicate that the frame has been aborted. 如果接收到此字节码,含此字节码的帧就被中止。 If receiving this bytecode, the bytecode frame containing this was aborted. 不将更多的八位组送入FIFO;如果该包是发送到链路层设备的,则标记为错误。 The octet is not more into the FIFO; if the packet is transmitted to the link layer device, is marked as an error.

EOS装置1包括1个8位错误计数器,对其中检测到中止序列的每个包进行计数。 EOS device 1 comprises an 8-bit error counter, which for each detected packet abort sequence is counted. 当性能监控的计数器被锁存时(LATCH_EVENT变成高电平),该计数器的值由寄存器MII_RX_EOS_PABORT_ERRCNT[7:0]锁存,并清除包中止错误计数器。 When the performance monitor counter is latched (LATCHEVENT the high level), the value of the counter by the register MII_RX_EOS_PABORT_ERRCNT [7: 0] latched, and clear the abort packet error counter.

如果从LATCH_EVENT的最后1个上升沿已导致至少1个包中止错误,则需设置包中止错误第二事件位MII_RX EOS_PABORT ERR_SECE。 If the package has led to at least one abort error, you need to set the packet abort error second event digit MII_RX EOS_PABORT ERR_SECE from the last one of the rising LATCH_EVENT.

作为一种替换方案,也可以通过反转FCS字节来中止1个包。 As an alternative, also possible to suspend a packet by reversing the FCS bytes. 这对于EOS装置1接收LAPS处理器来说仅是1种FCS错误。 This LAPS processor EOS receiving apparatus 1 is only one kind of FCS error. 其处理过程,如下段说明。 Its processing, described below in section.

作为一种选项,EOS装置1也可以将包视为错误包,并因此根据其是否违反最小或最大包规定,而进行标记。 As an option, EOS device 1 package can be treated as an error packet, and therefore minimum or maximum, depending on whether it violates the provisions of the package, and labeled. 包的大小只是指从EOS装置1出来的包大小,不包括去掉的标志序列、地址字节、控制字节、透明字节、FIFO下溢字节和FCS字节。 Refers only to the packet size from packet size out of the EOS device 1, does not include the flag sequence, address of the removed byte, control byte, byte transparency, and the FIFO underflow byte FCS bytes. 通过管理接口可以对这些最小和最大长度编程。 Via the management interface can be the minimum and maximum length programming pair. 寄存器MII_RX_EOS_PMIN[3:0]包含最小包长,该寄存器的缺省值是0;寄存器MII_ RX_EOS_PMAX[15:0]含有最大长度,该寄存器的缺省值是0x05E0。 Register MII_RX_EOS_PMIN [3: 0] contains the minimum packet length, the default value of this register is 0; register MII_ RX_EOS_PMAX [15: 0] contains the maximum length, the default value of this register is 0x05E0.

当通过管理接口发指令时,EOS装置1可使最小和最大长度校验功能有效/无效。 When the command sent via the management interface, EOS device 1 can be minimized and the maximum length of the check function valid / invalid. 寄存器MII_RX_EOS_PMIN_ENB和MII_RX_EOS_PMAX_ENB(两个缺省值均为0)控制如何处理对最小和最大包长的违反,当任何一个寄存器设置为1时,任何违反对应的包长规定,都会标记为错误。 And registers MII_RX_EOS_PMIN_ENB MII_RX_EOS_PMAX_ENB (two default values ​​are 0) control how the minimum and maximum packet size of the breach, when any one of the register is set to 1, the corresponding packet in violation of any predetermined length, will be flagged as an error.

EOS装置1包括两个8位错误计数器,对每个违反最小和最长包长限制的违例进行计数。 EOS device 1 comprises two 8-bit error counter, counting each violate minimum and maximum packet length limit violation. 当性能监控计数器被锁存时(LATCH_EVENT变为高电平),这些计数器值由寄存器MII_RX_EOS_PMIN_ERRCNT[7:0]和MII_RX_EOS_PMAX_ERRCNT[7:0]锁存,并清除包违例计数器。 When the performance monitor counter is latched (LATCHEVENT goes high), these counter values ​​by the register MII_RX_EOS_PMIN_ERRCNT [7: 0] and MII_RX_EOS_PMAX_ERRCNT [7: 0] latched, and clear the illegal packet counter.

如果从LATCH_EVENT的最后上升沿开始已导致至少1个包大小违例错误的话,就设置合适的包长违例第二事件位MII_RX_EOS_PMIN_ERR_SECE或MII_RX_EOS_PMAX_ERR_SECE。 If you start from the last rising LATCH_EVENT have led to at least one packet size violation error, then it is illegal to set the appropriate packet length second event digit MII_RX_EOS_PMIN_ERR_SECE or MII_RX_EOS_PMAX_ERR_SECE.

9.5帧校验序列(FCS)字段在EOS模式下(MII_RX_EOS=1),计算出FCS,并在每帧的结尾处对FCS字节进行检查。 9.5 Check Sequence (FCS) field in Mode EOS (MII_RX_EOS = 1), to calculate the FCS, and the FCS bytes to be checked at the end of each frame. 该选项由寄存器MII_RX_EOS_FCS_INH控制,值MII_RX_EOS_FCS_INH=0时FCS有效;值MII_RX_EOS_FCS_INH=1时FCS无效。 This option is controlled by the register MII_RX_EOS_FCS_INH, MII_RX_EOS_FCS_INH = 0 when the value of the FCS is valid; MII_RX_EOS_FCS_INH = 1 when the value is invalid FCS. 仅采用32位的校验序列(CRC-32)。 Only 32-bit check sequence (CRC-32). MII_RX_EOS_FCS_MODE=0使设备运行为FCS-32模式。 MII_RX_EOS_FCS_MODE = 0 for the operation of equipment FCS-32 mode.

EOS装置1提供CRC-32功能,采用生成多项式为:1+x+x2+x4+x5+x7+x8+x10+x11+x12+x16+x22+x23+x26+x32。 EOS device 1 provides CRC-32 function, the generating polynomial: 1 + x + x2 + x4 + x5 + x7 + x8 + x10 + x11 + x12 + x16 + x22 + x23 + x26 + x32. 对除标志序列和FCS字段自己本身外的所有帧码位计算FCS字段。 The FCS field is calculated for all the frames and flag sequences code bits except the FCS field itself outside.

如果MII_RX_EOS_FCS_BIT_ORDR=0(缺省值),采用高有效位(先为MSB)次序将接收的信号读进移位寄存器;如果MII_RX_EOS_FCS_BIT_ORDR=1,采用低有效位(首先为LSB)次序将接收的信号读进移位寄存器。 If MII_RX_EOS_FCS_BIT_ORDR = 0 (the default value), high significant bits (first to MSB) of the received signal sequence read into the shift register; read signal if MII_RX_EOS_FCS_BIT_ORDR = 1, low significant bits (first to LSB) the received sequence into the shift register. 无论是那种情况,FCS计算后,数据都是采用高有效位进行存储,以便处理。 In either case, after the FCS computation, data are based on significant bit is stored for processing.

得到的FCS结果值与接收到的FCS字段值进行比较,如果检测到错误,就告知管理控制接口,对应的计数器加1,FIFO中包的最后1个字标记为错误。 FCS result value obtained is compared with the received value of the FCS field, if an error is detected, to inform the management and control interface, the corresponding counter is incremented, and finally a word FIFO of packets marked as an error. EOS装置1包含一个20位的FCS错误计数器,对每个FCS CRC违例进行计数。 EOS device 1 comprises a 20-bit FCS error counter for each violation counts the CRC FCS. 当性能监控计数器被锁存时(LATCH_EVENT变为高电平),该计数器的值由寄存器MII_RX_EOS_FCS_ERRCNT[19:0]锁存,并清除FCS错误计数器。 When the performance monitor counter is latched (LATCHEVENT goes high), the value of the counter by the register MII_RX_EOS_FCS_ERRCNT [19: 0] latched FCS error and clear the counter.

如果从LATCH_EVENT的最后上升沿开始已导致至少1个FCS错误,则设置FCS错误第二事件位MII_RX_EOS_FCS_ERR_SECE。 If the start has resulted in at least one rising LATCH_EVENT FCS error from the last, then set the FCS error second event bit MII_RX_EOS_FCS_ERR_SECE.

FCS校验后,终止FCS字节(它们没有存储到FIFO)。 After FCS check, the FCS bytes to terminate (they are not stored to the FIFO). 如果通过管理接口禁止FCS校验的话,最后2或4个字节就发送到FIFO。 If the FCS check is prohibited through the management interface, the last two or four bytes is sent to the FIFO. 假定检测到一个FCS错误,当发送到链路层设备时,标记包为错误(RX_ERR)。 Assume that a FCS error is detected, when transmitted to the link layer device, labeled as an error packet (RX_ERR).

9.6LAPS帧终止在EOS模式(MII_RX_EOS=1)下,FCS计算之后,监控下列LAPS字节,并选择性地终止。 9.6LAPS frame mode terminates at EOS (MII_RX_EOS = 1), the FCS calculation then, the following monitoring LAPS bytes, and selectively terminates.

9.6.1标志序列所有用于帧描绘和内帧填充目的而出现的标志序列都被删除。 9.6.1 flag sequence for all of frame flag sequence depicted within the frame and filling purposes are deleted occurring. 帧信息的起始和结束标志仍由EOS装置1保留,通过RX_SOP和RX_EOP信号发送给链路层。 Start and end of frame information flag still retained EOS device 1, is sent to the link layer and RX_EOP RX_SOP signal.

9.6.2地址和控制字节地址和控制字节(跟随标志序列的LAPS帧中的前两个字节)是由EOS装置1监控,监控包括检查有效地址字段和控制字段(0xFF03)。 9.6.2 address and control bytes and the control byte address (LAPS frame following the first two bytes of the flag sequence) is monitored by an EOS device, the effective address monitoring comprises checking field and control field (0xFF03). 如果检测到不匹配,就认为该字段是压缩的,不发送出去。 If a mismatch is detected, the field is considered to compression, is not transmitted. 如果检测到无效值,这两个字节不被分离,通过MII接口传递到链路层。 If an invalid value is detected, these two bytes are not separated, passed through the MII interface to the link layer. 通过设置MII_RX_EOS_ADRCTL_INVALID=1告知管理控制接口检测到无效地址和控制字段。 By setting MII_RX_EOS_ADRCTL_INVALID = 1 to notify the management control interface detects an invalid address and control fields. 通过设置MII_RX_EOS_ADRCTL_INVALID_D的相应delta位为1,表示MII_RX_EOS_ADRCTL_INVALID的状态发生改变。 By setting delta MII_RX_EOS_ADRCTL_INVALID_D corresponding bit is 1, it represents MII_RX_EOS_ADRCTL_INVALID changes state.

如果检测到有效地址和控制字段,EOS装置1就终止这两个字节,不传递到RX FIFO。 If a valid address and control fields, the EOS device 1 terminates these two bytes are not transmitted to the RX FIFO. 通过设置MII_RX_EOS_ADRCTL_DROP_INH=1,可以禁止删除有效地址和控制字节。 By setting MII_RX_EOS_ADRCTL_DROP_INH = 1, it can be allowed to delete a valid address and control bytes. 该寄存器的缺省值为0(自动分离有效)。 The default value of this register 0 (effective automatic separation).

9.6.3 FCS字节如在FCS一节中提到的,EOS装置1也可以终止4个FCS字节。 9.6.3 FCS byte FCS as mentioned in section, EOS device 1 can also be terminated FCS 4 bytes. 如果通过管理控制接口(MII_RX_EOS_FCS_INH=1)禁止FCS校验,终止功能也被禁止,LAPS帧最后4个字节就发送到链路层。 If (MII_RX_EOS_FCS_INH = 1) is prohibited by the FCS check management and control interface, termination function is also disabled, the LAPS frame the last four bytes is sent to the link layer.

10接收FIFO接口10.1系统端包环回EOS装置1通过系统接口为用户提供环回接受的包功能。 10.1 FIFO interface 10 receives the loopback packet EOS System terminal apparatus 1 provides a user interface function loopback packet received by the system.

当SYS_T_TO_R_LOOP=1,从链路层设备接收的包从发送FIFO直接路由到接收FIFO,再输出回始发信元数据的链路层设备。 When SYS_T_TO_R_LOOP = 1, from the link layer device receives the packet from the receive FIFO routed directly to the transmit FIFO, and then back to the output link layer devices origination metadata. 当SYS_T_TO_R_LOOP设置为0时,在SONET/SDH链路信号内接收的包,发送到接收FIFO,然后输出到系统接口。 When SYS_T_TO_R_LOOP set to 0, the received SONET / SDH link signal packet transmitted to the receiving the FIFO, and then output to the system interface.

10.2FIFO处理过程EOS装置1将包写到FIFO,准备通过接收系统接口输出到链路层设备。 10.2FIFO EOS processing apparatus 1 writes the packet FIFO, ready for output to the link layer device by receiving the system interface. FIFO最小值为512个八位组。 FIFO minimum of 512 octets. 连同包,下列可应用的标识符必须伴随FIFO的每个字:包的开始、包的结束、包是否结束,字中(1或2)有几个八位组、以及包是否出错。 Together with the package, may be applied following each word must be accompanied by an identifier of the FIFO: The start packet, end of packet, the packet is finished, word (1 or 2) has several octets, and a packet for errors. 一旦在包信号里检测到错误,包不再有更多的字节装入FIFO中。 Upon detecting an error in the packet signal, the packages are no more bytes loaded into the FIFO.

FIFO状态由EOS装置1监控。 1 FIFO status monitored by EOS device. 通过设置MII_RX_FIFOOVER_E=1,向管理控制接口报告FIFO上溢事件,FIFO下溢的发生同时也会使对应的性能监控计数器增加。 By setting MII_RX_FIFOOVER_E = 1, the management control interface underflow event report FIFO, FIFO underflow occurs also cause a corresponding increase in performance monitoring counters.

EOS装置1包括一个8位FIFO下溢错误的计数器,对受FIFO下溢事件影响的每个包进行计数。 EOS device 1 includes the next eight FIFO overflow error counter, for receiving each packet FIFO underflow event counts affected. 当性能监控计数器被锁存时(LATCH_EVENT变为高电平),该计数器的值就由寄存器MII_RX_FIFOOVER_ERRCNT[7:0]锁存,并清除FIFO下溢错误计数器。 When the performance monitor counter is latched (LATCHEVENT goes high), the value of the counter is a register MII_RX_FIFOOVER_ERRCNT [7: 0] latched, and clear the error counter overflow FIFO.

如果从LATCH_EVENT的最后上升沿开始导致至少1个FIFO下溢事件的话,就设置FIFO下溢错误事件位MII_RX_FIFOOVER_ERR_SECE。 If you start underflow event resulting in at least one rising from the last FIFO LATCH_EVENT, then, is set overflow error event bit under FIFO MII_RX_FIFOOVER_ERR_SECE.

一旦检测到下溢错误,就不再有包的字节送入FIFO。 Once underflow error is detected, no more bytes into the packet FIFO. 在EOS模式(MII_RX_EOS=1)下,包的最后1个字标记为错误(RX_ERR)。 In the EOS mode (MII_RX_EOS = 1), the last word of the packet marked as an error (RX_ERR).

FIFO就在接收系统兼容接口之前,其目的是完成SONET时钟域和链路层时钟域之间的速率匹配功能。 Just before the reception FIFO compatible interface system, which aims to complete the SONET clock rate between the domain and the link clock domain matching layer.

10.3错误包处理RX处理单元12提供一个决定单元(determining unit)(未示出),它用来确定接收数据包类型、生成相应的预定SAPI,议及校验发生在帧中的错误。 10.3 RX error packet processing unit 12 a processing determining unit (determining unit) (not shown), which is used to determine the type of the received data packet, the SAPI generate corresponding predetermined, and verification errors occur in the proposed frame.

在EOS模式(MII_RX_EOS=1)下,对于由FIFO上溢事件破坏的包,EOS装置1用RX_ERR将其标记为错误包。 In the EOS mode (MII_RX_EOS = 1), for the destruction of a packet FIFO overflow events, the EOS device 1 with RX_ERR marked as error packets.

无效帧为:a)没有正确的以两个标志序列为界;或b)帧标志序列间的八位组少于8;或c)包含有一个帧校验序列差错;或d)包含一个接收器不匹配或不支持的服务访问点标识符(见ITU-T X.85的A.3.3);或e)包含一个不可识别的控制字段值;或f)结束标志为超过六个“1”位的序列。 Invalid frames: a) not have the correct sequence is bounded by two flags; or b) between the frame flag sequence octet less than 8; or c) contains a frame check sequence error; or d) comprises a receiver or does not match the supported service access point identifier (see ITU-T X.85 of A.3.3); or e) contains a control field value unrecognized; or f) is more than six end flag "1" bit sequence.

无效帧将被丢弃,不通知发方,也不产生任何动作。 Invalid frames are dropped without notifying the sender, nor any action.

10.4.接收数据奇偶校验作为MAC-PHY的规定,EOS装置1提供1个奇偶检验位,跟随发送到链路层的每个八位组或两个八位组的字(MII_RX_SYS_DAT[15:0])。 10.4 receiving the parity data as the predetermined MAC-PHY, the EOS device 1 provides a parity bit, following the words to each octet or two octets of the link layer (MII_RX_SYS_DAT [15: 0 ]). 在RX_PRTY管脚提供该奇偶校验位。 Providing the parity bits RX_PRTY pin. 作为缺省(MII_RX_PRTY_MODE=0),该位提供奇数奇偶校验;当MII_RX_PRTY_MODE=1时,提供偶数奇偶校验。 As a default (MII_RX_PRTY_MODE = 0), which provides odd parity bit; when MII_RX_PRTY_MODE = 1, to provide even parity.

RX_FIFO 13中执行从LAPS到MII的速率适配。 RX_FIFO 13 from the LAPS performing rate adaptation to the MII. 从RX_LAPS处理单元12输出的周期性LAPS帧(如155M),转换成突发的MII帧(如100M)。 LAPS frame periodically (e.g., 155M) from the output unit 12 RX_LAPS processing, is converted into a MII frame burst (e.g., 100M). 在TX FIFO执行相反的速率适配过程。 Instead of performing rate adaptation process in TX FIFO. 经过处理后,接收到的SDH/SONET帧转换成MII帧,通过转换器19传送到以太网层。 After treatment, the received SDH / SONET frame into MII frame, is transmitted to converter 19 through the Ethernet layer.

MII接口要求EOS装置1对MII接口的要求是基于IEEE 802.3对协调子层和介质独立接口的定义。 MII interface MII claim EOS device 1 is IEEE 802.3 interfaces requires Reconciliation sublayer and the media independent interface definition based.

图13是图9中的转换器19的详细功能模块图。 FIG 13 in FIG. 9 is a detailed functional block converter 19 of FIG. 图中所用的定义如下:TX_ER:发送编码错误;TXD:发送数据;TX_EN:发送允许;TX_CLK:发送时钟;GTX_CLK:千兆位发送时钟;COL:冲突检测;RXD:接收数据;RX_EN:接收使能;RX_CLK:接收时钟;CRS:载波侦听;RX_DV:接收数据有效;MDC:管理数据时钟;MDIO:管理数据输入/输出;TSOF:帧发送开始;TEOF:帧发送结束;TCLK:发送时钟;TENA:发送写允许;TFA:发送帧可用;TxDATA:发送数据;RSOF:帧接收开始;REOF:帧接收结束;RCLK:接收时钟;RV:接收数据有效;RFA:接收帧可用;RxDATA:接收数据。 Used in the figure are defined as follows: TX_ER: transmission coding errors; TXD: transmitting data; TX_EN: transmission permission; TX_CLK: transmitting clock; GTX_CLK: gigabit transmission clock; COL: collision detection; RXD: receiving data; RX_EN: Receive Enable energy; RX_CLK: receiving a clock; CRS: carrier sense; RX_DV: receiving data valid; MDC: management data clock; MDIO: management data input / output; TSOF: transmission start frame; TEOF: end frame transmission; TCLK: transmitting clock; TENA: transmitting write enable; TFA: transmitting frame may be used; TxDATA: transmitting data; RSOF: frame reception; REOF: frame reception; RCLK: receiving a clock; RV: receiving data valid; RFA: receiving a frame may be used; RxDATA: receiving data .

应指出的是,标记括号的信号项是变化的,这里有两种选择方法:对于Ethernet/Fast(快速)Ethernet over SDH/SONET情况,使用的是TxDATA<7:0>(8×19.44MHZ)、RxDATA<7:0>(8×19.44MHZ)、TXD<3:0>(4×25MHZ)、RXD<3:0>(4×25MHZ)以及TX_CLK(25MHZ)。 It should be noted that the signal term signs placed in parentheses is changed, there are two options: For Ethernet / Fast (fast) Ethernet over SDH / SONET case, the TxDATA & lt; 7: 0 & gt; (8 × 19.44MHZ) , RxDATA & lt; 7: 0 & gt; (8 × 19.44MHZ), TXD & lt; 3: 0 & gt; (4 × 25MHZ), RXD & lt; 3: 0 & gt; (4 × 25MHZ) and TX_CLK (25MHZ). 对于Gigabit(前兆位)Ethernetover SDH/SONET包括GTX_CLK方向在内使用的是:TxDATA<31:0>(32×78.76MHZ)/<63:0>(64×38.88MHZ)、RxDATA<31:0>(32×78.76MHZ)/<63:0>(64×38.88MHZ)、TXD<7:0>(8×125MHZ)、RXD<7:0>(8×125MHZ)以及GTX_CLK(125MHZ)。 For Gigabit (precursor bit) Ethernetover SDH / SONET comprising GTX_CLK directions from using: TxDATA & lt; 31: 0 & gt; (32 × 78.76MHZ) / & lt; 63: 0 & gt; (64 × 38.88MHZ), RxDATA & lt; 31: 0 & gt ; (32 × 78.76MHZ) / & lt; 63: 0 & gt; (64 × 38.88MHZ), TXD & lt; 7: 0 & gt; (8 × 125MHZ), RXD & lt; 7: 0 & gt; (8 × 125MHZ) and GTX_CLK (125MHZ).

如图13所示,转换器19执行MII/GMII接口和WRI接口间的转换功能。 13, converter 19 performs conversion between the MII / GMII interfaces and interfaces WRI.

1.输入和输出间转换模块的同步MII和GMII与IEEE 802.3标准兼容。 MII 1. Synchronization between input and output conversion module, and GMII compatible with the IEEE 802.3 standard. TX_CLK(发送时钟)或GTX_CLK(千兆位发送时钟)是一个为TX_EN、TXD以及TX_ER转移提供定时参考的连续时钟。 TX_CLK (Transmit Clock) or GTX_CLK (gigabit transmission clock) is to provide a timing reference for the TX_EN, TXD and TX_ER continuous clock transfer. RX_CLK(发送时钟或千兆位发送时钟)是一个为TX_DV、RXD以及RX_ER转移提供定时参考的连续时钟。 RX_CLK (gigabit transmission clock or transmit clock) is to provide a timing reference for TX_DV, RXD and RX_ER continuous clock transfer. 当自动协商处理选择全双工工作模式时,COL(冲突检测)信号和CRS(载波侦听)的工作状态没有详细说明。 When the auto-negotiation process selects full duplex mode, COL (collision detection) signal and the CRS (carrier sense) in the operating state is not described in detail.

在EOS装置的发送方向,MII/GMII和WRI接口分别为输入和输出接口,在接收方向,MII/GMII和WRI接口分别为输出和输入接口。 EOS device in the transmit direction, MII / GMII interfaces are WRI and input and output interface, in the receive direction, MII / GMII interfaces are WRI and output and input interfaces. WRI接口提供以下两种并行的发送和接收数据转移方式,这两种方式均采用独立于线速的时钟速率:在STM-1/OC-3c速率时为8bits(位)×19.44MHz;在STM-16/OC-48c速率为32bits×78.76MHz/64bits×38.88MHz。 WRI interface provides two parallel transfer mode data transmission and reception, these two methods are used in wire-speed clock rate independent: when STM-1 OC-3c rate / is 8bits (bits) × 19.44MHz; in an STM -16 / OC-48c rate 32bits × 78.76MHz / 64bits × 38.88MHz. EOS芯片支持通过转换器和LAPS处理器间的FIFO实现帧速率去耦。 EOS chip supports decoupling between the converter and the FIFO LAPS frame rate implemented by a processor.

为了简化MII/GMII层和EOS间的接口、支持多种物理层(PHY)接口,使用了转换器19和FIFO。 In order to simplify the interface between the MII / GMII layer and the EOS, to support multiple physical layer (PHY) interface using the converter 19 and the FIFO. 提供控制信号支持MII/GMII层和EOS层设备两者,以便允许EOS在WRI接口执行流控制。 It provides both a control signal support MII / GMII layer and a device layer EOS, EOS in order to allow WRI interface performs flow control. 由于总线接口是基于点到点连接,因此,EOS装置的接收接口通过FIFO和转换器19将数据推入MII/GMII层设备。 Since the bus interface is based on point to point connection, thus, EOS reception interface means via the converter 19 and the FIFO push data MII / GMII layer devices. 在发送和接收接口可用帧状态颗粒(granularity)是基于八位组。 In the transmission and reception interfaces available frame status particles (granularity &) is based on octets. 在接收方向,当EOS层设备在其接收FIFO中存储了一个帧的结束(一个小的LAPS帧或一个大的LAPS帧结束)或预定数个字节时,通过转换器19向MII/GMII层设备发送带内地址(in-band address),后跟FIFO数据。 In the receive direction, when EOS layer device stores a frame in which the end of the receive FIFO (small end of a LAPS frame or a large frame LAPS) or a predetermined number of bytes, the converter 19 to the MII / GMII layer device address transmission band (in-band address), followed by the FIFO data. 在WRI接口总线的数据贴上接收有效信号(RV)的标志。 Paste receiving a valid signal (RV) of the flag in the data WRI interface bus.

具有多个FIFO的多端口EOS装置在其FIFO中有足够的数据时,每个端口可以循环(round-bin)方式工作。 EOS multi-port device having a plurality of FIFO there is sufficient data in its FIFO, each port can cycle (round-bin) manner. WRI接口根据IEEE 802.3x和相关的转换器19通过不维持允许信号(RENB)可暂停数据流。 The IEEE 802.3x WRI interfaces and associated converter 19 is maintained by not allowing signal (for RENB) to suspend the data flow. 在发送方向,当EOS层设备有空间给发送FIFO中预定数个字节时,通过声明一个发送帧到达(transmitframe available,TFA)经转换器19通知MII/GMII层设备。 In the transmit direction, when a space is to EOS layer device transmits a predetermined number of bytes in the FIFO, by declaring a transmission frame arrives (transmitframe available, TFA) notifies MII / GMII layer devices via the converter 19. MII/GMII层设备能在WRI接口用一个允许信号(TENB)将后跟帧数据的带内地址写到EOS层设备。 MII / GMII layer in the device can interface with a WRI enable signal (TENB) followed by the band address data is written to the frame EOS layer device. 转换器19监控TFA从高到低的转变,该转变表示发送FIFO接近满了(FIFO中剩下的字节数可由用户选择,但必须预定义),悬挂数据转移以避免下溢。 TFA converter 19 to monitor the transition from high to low, this transition represents the transmission FIFO is almost full (number of bytes remaining in the FIFO selected by the user, but must be predefined), data transfer is suspended to avoid underflow. 转换器19通过不维持允许信号(TENB)可暂停数据流。 Converter 19 is maintained by not allowing signal (TENB) data stream may be suspended.

在发送方向,WRI-PHY定义帧级转移控制。 In the transmission direction, WRI-PHY frame level transition control is defined. 由于帧大小是可变的,不提供任何可用字节数保证,在发送和接收两个方向信号,在STFA上提供选择的可用EOS发送帧,在信号RV上接收数据有效。 Since the frame size is variable, the number of bytes available does not provide any guarantee in the transmit and receive signals in both directions, provided the selected EOS STFA available transmission frame, received data valid on the signal RV. STFA和RV一直反映数据正被转移到后从其转出的选择的EOS的状态。 STFA and RV always reflects the state of EOS data is being transferred to the roll-out of its choice. RV指示有效数据在接收数据总线上是否可用,并被定义为数据转移可与帧边界对齐。 RV indicating whether valid data is available on the receive data bus, and is defined as a data transfer can be aligned with frame boundaries. 用带内寻址选择物理层端口。 Select a physical layer interface with the tape addressing. 在发送方向,MII/GMII设备通过在TxDATA<7:0>或TxDATA<31:0>/TxDATA<63:0>总线上发送地址来选择EOS端口,总线上有TSX信号处于激活态、TENB信号处于非激活态标志。 In the transmit direction, MII / GMII device by TxDATA & lt; 7: 0 & gt; or TxDATA & lt; 31: 0 & gt; / TxDATA & lt; 63: 0 & gt; transmit address bus to select EOS ports on the bus TSX signal is in an active state, TENB signal in a non-active state flag. 所有标志了TENB处于激活态的后续TxDATA<7:0>或TxDATA<31:0>/TxDATA<63:0>总线操作是用于指定端口的帧数据。 All marks TENB in ​​the active state subsequent TxDATA & lt; 7: 0 & gt; or TxDATA & lt; 31: 0 & gt; / TxDATA & lt; 63: 0 & gt; bus operations are the frame data for the specified port. 在接收方向,MII/GMII设备,通过在RxDATA<7:0>或RxDATA<31:0>/RxDATA<63:0>总线上发送地址来指定选择端口,总线有RSX信号处于激活态、RV信号处于非激活态标志。 In the receive direction, MII / GMII apparatus by RxDATA & lt; 7: 0 & gt; or RxDATA & lt; 31: 0 & gt; / RxDATA & lt; 63: 0 & gt; sending the address on the bus to specify the selected port, bus has RSX signal is in an active state, RV signal in a non-active state flag. 所有标志了RV处于激活态的后续RxDATA<7:0>或RxDATA<31:0>/RxDATA<63:0>总线操作是用于指定端口的帧数据。 All flags the subsequent RxDATA RV is in an active state & lt; 7: 0 & gt; or RxDATA & lt; 31: 0 & gt; / RxDATA & lt; 63: 0 & gt; bus operations are the frame data for the specified port.

为了支持现有的少量的多端口EOS层设备以及将来高密度多端口设备,当EOS层设备的端口数量有限时,采用DFTA信号的字节级转移提供一种更简单的实现方法,同时减少所需的寻址管脚。 In order to support a small number of conventional multi-port device layer EOS and future high-density multi-port device, when a limited number of ports EOS layer device, adopted to provide a more simple implementation DFTA byte-level transfer signal, while reducing the need addressing pins. 在这种情况下,随着端口数量的增加,直接访问就变得毫无理由。 In this case, with the increase in the number of ports, direct access becomes no reason. 当端口数量多时,采用TADR总线使帧级转移所需的管脚数量少得多。 Much less when the number of ports is large, so that the frame-level bus using TADR transfer the desired number of pins. 带内寻址保证两种方法的协议保留一致。 With the addressing protocols to ensure retention of the two methods is consistent. 然而系统设计者和物理层设备制造商具体选用那种方法取决于那种方法更适合其想得到的应用。 However, equipment manufacturers and system designers specific choice of the kind of physical layer that depends on which method is more suitable for use conceivable.

2.转换器19的数据结构应采用一个定义的数据结构将帧写到发送FIFO以及从接收FIFO中读取帧。 2. The data structure of the converter 19 should be a defined data structure written to the transmit FIFO frame and reads the frame from the receive FIFO. 八位组以在SDH/SONET线路中发送或接收的相同顺序读写。 Octet read in the same order sent or received in the SDH / SONET line. 在一个八位组中最高有效位(位7)首先发送(参见图7/ITU-T建议草案X.86)。 In a most significant group of eight bit (bit 7) is first transmitted (see FIG. 7 / ITU-T draft recommendation X.86). EOS装置可用来转移1个字节的帧。 EOS means can be used to transfer one byte frame. 在这种情况下,同时声明帧信号的开始和结束。 In this case, a statement that the beginning and end of the frame signal. 对于帧长度超过EOS装置FIFO的帧,帧必须通过WRI接口转移。 EOS device for a frame length exceeds the FIFO, the frame must be transferred through the interface WRI. 在每个段每个帧数据的字节数可以固定不变,也可以是变化的,这取决于具体的应用。 Bytes in each segment of each frame of data may be fixed, or may vary, depending on the particular application. MII/GMII可通过转换器19在MII/GMII接口发送固定大小的帧段,或者当FIFO满时在WRI接口上使用TFA信号来确定。 MII / GMII can be determined by the converter 19 in the frame segment MII / GMII interface to send fixed size, or when the FIFO full signal with TFA in WRI interface. 对于多MII/GMII端口应用,用TPAS(发送端口地址选择,Transmit Port Address Selection)指示TxDATA总线上的带内端口地址选择有效。 For multi-MII / GMII port applications, with TPAS (transmit port address selection, Transmit Port Address Selection) indicating band on the port address bus TxDATA effective choice. 当TPAS处于高位、TENB也是高位时,TxDATA[7:0]或TxDATA<31:0>/TxDATA<63:0>的值是要选择的发送FIFO的地址。 When TPAS are high, TENB is high, TxDATA [7: 0] or TxDATA & lt; 31: 0 & gt; / TxDATA & lt; 63: 0 & gt; value is the address in the transmit FIFO to be selected. TxDATA总线上的随后数据转移填充到该带内地址指定的FIFO中。 Subsequent data transfer on the bus TxDATA filled in with the address specified by the FIFO. 对于单一端口的EOS装置,TPAS信号是可选项,因为当TENB处于高位时,EOS装置将忽略带内地址。 For a single port EOS device, TPAS signal is optional, because when TENB are high, with EOS will ignore the address. 只有在没有声明TENB时,TPAS才有效。 Only in the absence of a statement TENB, TPAS is valid.

在32位/64位总线接口以及8位总线接口,没有示出多端口EOS装置的带内端口地址。 In the 32-bit / 64-bit bus interface 8 and a bus interface, not shown, the multi-port device with port address EOS. 转换器19应在与数据相同的总线上发送MII/GMII端口地址,该总线标志TPAS信号处于激活态,TENB信号处于非激活态。 Converter 19 to be sent on the same data bus MII / GMII port address, the flag TPAS bus signal is in an active state, TENB signal is non-active state. WRI接口上随后的数据转移使用带内地址选择的发送FIFO。 WRI interface transferring the subsequent data transmission using the FIFO with address selection. 在接收接口,在转移帧数据前EOS装置用RPAS(接收端口地址选择,Receive Port Address Selection)信号处于激活态,RV信号处于非激活态报告带内接收FIFO地址(the receive FIFO addressin-band)。 The reception interface, before transferring frame data EOS device RPAS (receiving port address selection, Receive Port Address Selection) signal is in an active state, RV signal is received FIFO address (the receive FIFO addressin-band) the non-active state report band. 对于这两种情况,超出FIFO大小的大帧通过在每个段中加上适当的带内地址前缀,经WRI接口转移。 For both cases, a large frame size beyond the FIFO by adding an appropriate address prefix band in each segment, via the interface WRI transfer.

带内地址在以TPAS/RPAS信号标志的单个时钟周期操作中规定。 Address to a predetermined band in a single clock cycle TPAS / RPAS operation flag signal. 端口地址由TxDATA[7:0]和RxDATA[7:0]信号或TxDATA[31:0]/TxDATA[63:0]以及RxDATA[31:0]/RxDATA[63:0]信号确定。 A port address TxDATA [7: 0] and RxDATA [7: 0] signal or TxDATA [31: 0] / TxDATA [63: 0] and RxDATA [31: 0] / RxDATA [63: 0] signal determination. 在数值编码方式下,地址是TxDATA[7:0]和RxDATA[7:0]信号或TxDATA[31:0]/TxDATA[63:0]和RxDATA[31:0]/RxDATA[63:0]信号的数值,此时,位0是最低有效位,位7是最高有效位。 In the numerical coding mode, the address is TxDATA [7: 0] and RxDATA [7: 0] signal or TxDATA [31: 0] / TxDATA [63: 0] and RxDATA [31: 0] / RxDATA [63: 0] a numerical signal, in which case, bit 0 is the least significant bit, bit 7 is the most significant bit. 这样,一个单接口可支持多达256的端口。 In this way, a single interface can support up to 256 ports. 对32位接口,忽略掉上面的24位,对64位接口,忽略掉上面的56位。 32-bit interface, ignored above 24, for 64-bit interface, ignore 56 above.

根据ITU-T建议草案,在LAPS处理器中必须处理帧校验序列(FCS)。 According to ITU-T draft recommendation, it must process a frame check sequence (FCS) in LAPS processor. 如果EOS装置在传送前不以可选项方式插入FCS字节,则在包结尾应该包括这些字节。 If the device is not inserted EOS option FCS bytes before transmitting manner, the package should be included at the end of these bytes. 如果EOS装置在接收方向没有剥离FCS字段,则在包结尾应保留这些字节。 If the device does not release EOS FCS field in the receive direction, the end of the packet should be retained in these bytes.

管理控制接口下面描述对应于EOS装置的管理控制接口,定义可供外部微处理器读写的所有寄存器地址。 Management and control interface will be described below corresponds to the EOS device management and control interface, defined for all the register read and write address of the external microprocessor. 这里使用了一张表,该表了包含公共配置和总体状态映射(Summary Status Map),后者拥有整个设备公用的控制和监控参数。 Used here a table that contains the common configuration and overall state map (Summary Status Map), which has a common control and monitoring parameters of the entire apparatus. 在发送端,该表为管理控制接口寄存器映射,在接收端,每个块是管理控制接口寄存器映射。 The transmitting side, the table management and control interface register map at the receiving end, each block is mapped register management and control interface. 微处理器总线地址的最高有效位ADDR[8:0]指明映射是否与发送或接收方向有关。 The most significant bit microprocessor bus address ADDR [8: 0] indicates whether the mapping to the transmission or reception direction. ADDR[7:0]指示特殊映射,这些值采用后面详述的每个映射识别。 ADDR [7: 0] indicating the special mapping, each mapping identified using these values ​​described in detail later. 公共配置和总体映射为ADDR[8]=0。 And generally common configuration mapped to ADDR [8] = 0.

1.中断或轮询(polled)操作管理控制接口以中断驱动或轮询模式两种方式工作。 1. interrupt or polling (Polled) operation management and control interface to interrupt driven or polled mode operates in two modes. 在这两种模式中,公共配置和总体状态映射地址0x002中的EOS装置寄存器位SUM INT用于决定EOS装置中的监控寄存器状态是否已发生了变化。 In both modes, the common overall configuration and status register bit map address 0x002 EOS device is used to monitor whether the register SUM INT EOS status determining means has changed.

1.1中断源1.1.1发送端发送端寄存器映射(Transmit Side register map)几乎是确定SONET/SDH信号组成以及提供LAPS、SONET/SDH POH和SONET/SDH TOH/SOH值的全部规定参数(provisioning parameters)。 1.1 1.1.1 Interrupt Source Register Map transmitting end (Transmit Side register map) almost determines the transmission side SONET / SDH signal consisting of predetermined parameters, and to provide all the LAPS, SONET / SDH POH and SONET / SDH TOH / SOH value (provisioning parameters) . 除这些规定参数外,发送端寄存器映射包括系统接口和通用I/O监控器。 In addition to these predetermined parameters, the transmitting end includes a system interface register map and general purpose I / O monitor. 如果这些指示中的任何一个处于激活态,则寄存器0x002中的SUM_INT位为高位(逻辑1)。 If any of these instructions are in the active state, the 0x002 bits of the register SUM_INT is high (logic 1). 如果SUM_INT_MASK=0,微处理器接口中断输出(INTB)处于激活态(逻辑0)。 If SUM_INT_MASK = 0, interrupt output microprocessor interface (INTB) in the active state (logic 0).

1.1.2接收端该表也包含寄存器0x005中接收端的总体状态位。 1.1.2 When the end of the table also contains general status bit register 0x005 receiving end. 这些位提供寄存器0x002中的SUM_INT位。 These bits provide SUM_INT bit register is 0x002. 如果总体状态位中的任何一个为“1”,并且相应的掩蔽位为“0”,则设置SUM_INT位为“1”。 If the overall status bit is any one of "1", and the corresponding mask bit is "0", the bit SUM_INT set to "1." 如果表(TBD)中一个或多个相应位组为“1”,则表中寄存器0x005(TBD)中总体状态位为“1”。 If the table (TBD) one or more respective groups of bits is "1", the table registers 0x005 (TBD) in the overall status bit is "1." 可掩蔽单个TOH/SOH delta和第二次事件位(Second event bit)(表(TBD),例如地址为0x204-0x206)。 It may be a single mask TOH / SOH delta and second event bits (Second event bit) (Table (TBD), such as an address of 0x204-0x206).

1.2中断驱动在中断驱动模式中,应清除公共配置和总体状态映射的寄存器0x006的SUM_INT_MASK位(设置为0)。 1.2 interrupt driven mode, the interrupt-driven, common configuration should be cleared SUM_INT_MASK bit-mapped registers and general state of 0x006 (set to 0). 这允许INTB输出成为激活位(逻辑0)。 This allows INTB output goes active (logic 0). 该输出是INTB=! The output is INTB =! (!SUM_INT_MASK && SUM_INT)。 (! SUM_INT_MASK & amp; & amp; SUM_INT). 此外,应清空接收端的MII_RX_APS_INT_MASK位(设置为逻辑0)。 Moreover, it should clear the bit receiving end MII_RX_APS_INT_MASK (set to logical 0). 这允许APS_INTB输出成为激活位(逻辑0),该输出是APS_INTB=! This allows APS_INTB output goes active (logic 0), the output is APS_INTB =! (!MII_RX_APS_INT_MASK &&MII_RX_APS_INT)。 (! MII_RX_APS_INT_MASK & amp; & amp; MII_RX_APS_INT). 如果发生了中断,微处理器首先读取总体状态寄存器0x004-0x005以确定激活的中断源类,然后读取该类中的特殊寄存器,以确定中断的精确原因。 If the interrupt, the microprocessor first reads to determine the overall status register 0x004-0x005 activated interrupt source class, then the class read the special register, to determine the precise cause of the interrupt occurrence.

1.3轮询模式在轮询模式中,应设置SUM INT MASK和MII RX_APS_INT MASK位(为逻辑1),以抑制所有硬件中断以及运行在轮询模式中。 1.3 polling mode in the polling mode, and should be set SUM INT MASK MII RX_APS_INT MASK bit (logic 1), and to inhibit the operation of all hardware interrupts in the polling mode. 在这种模式中,EOS装置1输出INTB,APS_INTB保持在非激活状态(逻辑1)。 In this mode, EOS device output INTB, APS_INTB maintained in an inactive state (logic 1).

应指出的是,SUM_INT_MASK和MII_RX_APS_INT_MASK位不影响寄存器位SUM_INT和MII_RX_APS_INT的状态。 It should be noted that, SUM_INT_MASK and MII_RX_APS_INT_MASK bit does not affect the status register bits SUM_INT and MII_RX_APS_INT of. 可以轮询这些位以确定是否需要进一步询问寄存器。 These bits can be polled to determine if further inquiry register.

微处理器接口连接EOS装置的微处理器接口18使系统能够接入OS装置中的所有寄存器。 EOS microprocessor interface means connected to a microprocessor interface 18 enables the system to access all registers OS device. 微处理器接口可以运行在中断驱动或轮询模式。 Microprocessor interface can operate in an interrupt driven or polled mode. 在中断模式,EOS装置支持多种中断源。 In interrupt mode, EOS device supports multiple interrupt sources. 无论在那种模式,EOS装置均可掩蔽任何中断。 Whether in that mode, EOS device can mask any interruption.

由于本发明的EOS装置中的其他段是众所周知的,在此略去相关的描述。 Since the EOS device of the present invention are well known in other segments, associated description thereof is omitted herein.

上面参照SDH/SONET描述了本发明,然而,本发明也可用在简化SDH/SONET中。 Above with reference to SDH / SONET described in the present invention, however, also be used in the present invention is simplified SDH / SONET in. 简化SDH/SONET是指简化的SDH/SONET,其中终止POH、以降低处理器的负载。 Simplified SDH / SONET refers simplified SDH / SONET, wherein terminating POH, to reduce the load on the processor.

图14所示为根据本发明实施例,使SDH专用网与具有EOS装置的10BASE-T、100BASE-T和1000BASE-x的2层交换机(命名为S24-2OC-48)连接的示例图。 14 shows an embodiment of the present invention, the private network and the SDH 10BASE-T, 2-layer switch 100BASE-T and 1000BASE-x having EOS device (designated S24-2OC-48) connected in the example of FIG.

图中所用的定义如下:GMAC,千兆位介质接入控制;GMII,千兆位介质独立接口;MAC,介质接入控制;交换控制内存(Switch control Memory):用于交换过程中读和写数据;I2C接口,用于提供E2PROM接口;CPU接口单元:用于提供对外部微机主机的接口功能;帧缓冲器:用于存储高速数据;帧存储器,用于以常规方式存储数据;Gigabit Ethernet over STM-16c/OC-48C,提供两个千兆以太网映射的EOS单元。 Used in the figure are defined as follows: GMAC, Gigabit Media access control; GMII, gigabit media independent interface; MAC, Medium Access Control; exchange control memory (Switch control Memory): the process of reading and writing for exchanging transactions; the I2C interface for providing an interface E2PROM; the CPU interface unit: means for providing an interface to an external host computer; a frame buffer: means for storing speed data; a frame memory for storing data in a conventional manner; Gigabit Ethernet over STM-16c / OC-48C, two Gigabit Ethernet provides EOS mapping unit.

根据图9的框图所示的单个OC-48c/STM-16c展示单个GMII信道。 GMII show single channel from a single block diagram shown in FIG. 9 OC-48c / STM-16c. 24端口10/100 MAC用于提供二十四个MAC端口处理。 24-port 10/100 MAC MAC port for providing twenty-four process. MAC帧引擎(MACFrame Engine,MFE)是S24-2GEOC48中的主MAC帧缓冲和转发引擎。 MAC frame engine (MACFrame Engine, MFE) is a front S24-2GEOC48 the MAC frame buffer and forwarding engine. MAC搜索引擎(MSE)用于提供目的地地址搜索功能。 MAC Search Engine (MSE) for providing a destination address search function.

S24-2GEOC48的基本特征如下:● STM-16c/OC-48c上的2个千兆以太网端口;●带MII接口的24个10/100Mbps自动侦听、快速以太网端口; S24-2GEOC48 basic characteristics are as follows: ● 2 Gigabit on STM-16c / OC-48c Ethernet port; ● MII interface 24 with 10 / 100Mbps automatically listen, Fast Ethernet ports;

●支持IEEE 802.1d生成树算法;●2层交换。 ● Supports IEEE 802.1d Spanning Tree algorithm; ● Layer 2 switching.

--内部交换数据库内存支持多达2k的MAC地址、高达64k的用于SNMP网络管理CPU存储器、基于Web的网络管理控制台接口或RS-232本地控制台接口或并行接口。 - MAC address of the internal memory exchange database supports up to 2k of up to, Web-based management console interface or RS-232 local console interface or a parallel interface for SNMP network management CPU 64k of memory.

---在24+2(EOS)系统中支持多达16k的MAC地址。 --- support up to 16k in the MAC address 24 + 2 (EOS) system.

●通过IGMP探听支持IP多播;●高速MAC帧转发,转发速率大于每秒300万MAC帧(3Mpps),以及全线速过滤;●采用真正的非模块化体系结构,支持超过6Mpps(每秒600万包)吞吐量的系统。 ● by IGMP snooping support IP multicasting; ● high speed MAC frame forwarding, forwarding rate greater than 300 million times per MAC frame (3Mpps), filtered, and full wire speed; ● a true non-modular architecture supports over 6Mpps (600 per second million bales) throughput of the system.

●在进入端口单存储和转发,在目的地端口直通交换●通过单存储和转发交换技术,延时非常低;●全双工以太网IEEE 802.3x流控制使业务拥塞最小化;●对半双工端口采用背压(backpressure)流控制(IEEE802.3x);●提供端口和ID标志的虚拟局域网(VLAN)802.1Q;●VLAN ID标志插入/提取;●支持IEEE 802.1p/Q服务质量,其具有4个优先发送队列、加权公平队列、以及用户映射优先级和权重●支持以太网多播和广播;●提供源、目的和协议过滤;●严格的电可擦除只读存储器提(EEPROM)提供配置数据保护。 ● In the store and forward a single inlet port, the destination port through switching ● single store and forward switching, the delay is very low; ● full-duplex Ethernet IEEE 802.3x Flow Control minimize traffic congestion; ● half-bis workers backpressure port (the backpressure policy) flow control (IEEE802.3x); ● provide a port ID and a virtual local area network logo (VLAN) 802.1Q; ● VLAN ID flag insertion / extraction; ● support IEEE 802.1p / Q quality of service, which having four transmit queue priority, weighted fair queuing, and priority and user mapping weights ● Ethernet multicast and broadcast; ● providing source, destination and protocol filtering; ● strict electrically erasable read only memory mentioned (EEPROM) provide configuration data protection.

S24-2GEOC48是一个26端口的10/100/1000Mbps Gigabit Ethernet overover STM-16c/OC-48c带有片内地址存储空间的非模块化以太网交换芯片。 S24-2GEOC48 is a 26 10/100 / 1000Mbps Gigabit Ethernet overover STM-16c ports / OC-48c with a non-modular Ethernet switch chip address memory space. 片内地址存储器支持多达2K的MAC地址以及多达256个IEEE 802.1Q虚拟局域网(VLAN)。 Address memory chip supports up to 2K MAC addresses and up to 256 IEEE 802.1Q Virtual Local Area Network (VLAN). 在10/100Mbps端口S24-2GEOC48支持端口中继(port trunking)/负载共享。 In 10 / 100Mbps ports S24-2GEOC48 supports port trunking (port trunking) / load sharing. 端口中继/负载共享可用于内连交换机间的端口分组,以增加网络带宽效率。 The relay port / ports may be used for load sharing among the packet switch is connected to the network to increase bandwidth efficiency. 帧缓冲存储器接口采用性能价格合算的、高性能流水式同步突发SRAM,以同时在所有外部端口支持全线速。 Interface uses a frame buffer memory performance price-effective, high-performance synchronous pipelined burst SRAM, while full wire speed in order to support all the external ports. 在半双工模式,所有端口支持背压流控制,将长期激活突发的数据丢失的威胁降到最小。 In half-duplex mode, all ports support backpressure flow control, long-term activation burst threat of data loss to a minimum. 在全双工模式,提供IEEE 802.3x流控制。 In full duplex mode, provides IEEE 802.3x flow control. 在全双工情况下,端口0-11支持200Mbps聚集带宽连接,端口12支持2 Gbps到桌面计算机、服务器或其他高性能交换机。 In the case of full-duplex, ports 0-11 to support aggregate bandwidth 200Mbps connections, supports 2 Gbps port 12 to the desktop computer, server, or other high-performance switches. 对26个端口中的每个端口独立收集以太网SNMP和远程接口管理信息库(RMONMIB)的统计信息。 To 26 ports each port independently collect and remote interfaces Ethernet SNMP MIB (RMONMIB) statistics. 通过CPU接口提供对这些统计计数器/寄存器的接入。 Access to these statistics counters / registers provided through the CPU interface. 通过CPU接口接收和发送SNMP管理帧,形成一个完整的网络管理方案。 Via the CPU interface receive and transmit SNMP management frame, forming a complete network management solutions. S24-2GEOC48用0.18μm技术制造。 S24-2GEOC48 0.18μm manufacturing techniques. 容许的输入电压为3.3V,输出直接与LVTTL电平相连接。 Allowable input voltage is 3.3V, LVTTL outputs directly connected to the level.

如图所示,当在交换机和传输设备(如ADM)之间通信时,本发明的EOS装置可内装在10M/100M/1000M局域网2层交换机中。 As shown, when the switch between the transmission equipment (such as ADM) communication, the EOS device of the present invention may be incorporated in 10M / 100M / 1000M Layer 2 LAN switch.

24个10/100介质接入控制器(MAC)提供进入S24-2GEOC48的协议接口。 24 10/100 medium access controller (MAC) protocol interface provides access S24-2GEOC48. 这些MAC完成MAC帧校验的要求,以保证提供给MAC帧引擎的每个MAC帧符合所有IEEE 802.3标准。 These requirements complete MAC frame MAC check to ensure that each MAC frame to MAC frame engine meets all the IEEE 802.3 standard. 丢弃那些长度大于1518字节(带VLAN标志为1522字节)以及小于64字节的数据MAC帧,VHS 108已经设计成支持输入MAC帧间的最小帧间间隙。 Discard more than 1518 bytes (1522 bytes VLAN tag tape) and less than 64 bytes of data the MAC frame, VHS 108 it has been designed to support a minimum interframe space input MAC frames.

MAC帧引擎(MFE)是S24-2GEOC48中的主MAC帧缓冲器和转发引擎。 Engine MAC frame (the MFE) is a front S24-2GEOC48 the MAC forwarding engine and the frame buffer. 因此,MFE控制进出外部帧存储缓冲器的MAC帧的存储,留意帧缓冲器的可用性,以及安排输出MAC帧发送。 Thus, the MFE MAC control frame stored out of the external frame buffer memory, the availability of watching the frame buffer, and outputs the MAC frame transmission schedule. 当MAC帧数据被缓冲时,MFE从每个MAC帧首标中提取必须的信息,将其发送到搜索引擎中进行处理。 When the MAC frame data is buffered, the MFE to extract the necessary information from the header of each MAC frame, and sends it to the search engine for processing. 搜索结果送回MFE,从而安排MAC帧发送及其优先级。 Search results returned MFE, arranged so that the MAC frame transmitted and the priority. 当选定一个MAC帧发送时,MFE从外部缓冲存储器读取MAC帧,将其放置到输出端口的输出FIFO中。 When a MAC frame transmission is selected, the MFE MAC frame read from the external buffer memory, which is placed into the output FIFO output port.

MFE可管理S24-2GEOC48所有端口的输出发送队列。 MFE manage all output ports S24-2GEOC48 transmit queue. 一旦在MSE中完成目的地地址搜索,作出的交换决定送回到MFE,将MAC帧插入到适当的输出队列。 Once the destination address search in the MSE, switching decisions made by the MFE is returned, the MAC frames into the appropriate output queue. 帧是进入高优先级还是进入低优先级队列由VLAN优先级标志信息或IP首标中的业务类型/不网业务(TOS/DS)字段来控制。 A high priority frame or entering into the low priority queue is controlled by a priority flag VLAN IP header information or the service type / no network service (TOS / DS) field. 配置寄存器可确定QoS映射所采用的是VLAN优先级标签还是TOS/DS字段。 Configuration registers may determine QoS mapping is used VLAN priority tag or TOS / DS field. 一旦采用VLAN优先级标签进行QoS映射,用户也可通过寄存器VLAN优先级映射方法映射发送优先级,以及通过寄存器VLAN丢弃映射寄存器指定丢弃的先后次序。 Once the VLAN using tags QoS mapping priority, user priority can also register VLAN mapping method by transmission priority, and by discarding the register map register specified VLAN discard priorities. 当系统采用TOS/DS编码点字段来映射QoS时,可选用TOS字节(参考RFC 791)或TOS字节的位[3:5](参考RFC 2460以及IETF站点上的其他RFC文档)来映射发送队列的优先级以及帧丢弃的先后次序。 When the system uses the TOS / DS field codepoints map to QoS, the choice of the TOS byte (see RFC 791) or the TOS byte in bits [3: 5] (refer to RFC 2460 is on, and other IETF documents RFC site) to map and the order of transmission priority queue of frame dropping. 用户能够控制所选的TOS映射字段。 The user can control the selected TOS map field. TOS字段映射到高优先级队列或低优先级队列由寄存器TOS优先级映射和TOS丢弃映射处理。 TOS field mapped to the high priority queue or from the low priority queue register TOS TOS priority mapping and mapping processing discarded. S24-2GEOC48用加权循环(Weighted Round R0bin,WRR)以及加权随机早期检测/丢弃(WeightedRandom Early Detection/Drop,WRED)安排帧发送。 S24-2GEOC48 weighted cycle (Weighted Round R0bin, WRR) and weighted random early detection / drop (WeightedRandom Early Detection / Drop, WRED) frame transmission schedule. 为使S24-2GEOC48有QoS能力,需一个EEPROM(4k字节)来改变缺省寄存器配置,开启QoS。 For S24-2GEOC48 have QoS capabilities, a need EEPROM (4k bytes) to change the default configuration register, open QoS.

开启电源后,S24-2GEOC48能立即开始地址学习和MAC帧转发。 After the power is turned on, S24-2GEOC48 can immediately start MAC address learning and frame forwarding. MAC搜索引擎(MSE)为S24-2GEOC48输入端口上接收到的每个有效MAC帧检查其内部交换数据库存储内容。 Each MAC MAC effective search engine (MSE) of the received input port S24-2GEOC48 frame exchange checks its internal database stored contents. 当MSE在其数据库内没有发现匹配时,检测到未知的源和目的地MAC地址。 When the MSE match is not found in its database, the detected unknown source and destination MAC addresses. 通过在交换数据库存储器中生成一个新项目,同时在该位置存储必要的分辨信息,来学习这些未知源MAC地址。 By generating a new item in the database memory exchange, while in this position stores necessary resolution information, to learn the source MAC address unknown. 在搜索到一个学习过的目的地MAC地址之后,将返回该MAC地址控制表(MACAddress Control Table,MACT)项目的新内容。 After the search to a learned destination MAC addresses, it will return to the MAC address control table new content (MACAddress Control Table, MACT) program. 在每次源地址搜索后,MACT项目变化标志(aging flag)更新。 After searching each source address, MACT project change flag (aging flag) update. 那些在一个用户可配置的时间周期内(从5到7200秒)没有被接入的MACT项目将被移去。 Those (from 5 to 7200 seconds) has not been accessed MACT items will be removed within a time period of a user configurable. 变化时间周期可用存储在寄存器MAC地址变化时间的低和高的16位值配置。 Change time period available storage arranged in the low and high 16-bit MAC address value register changes over time. 在每个时间周期中,所有MACT项目变化检查1次。 In each time period, all projects change MACT check once. 如果MAC项目在下一时间周期结束前没有使用,则将其删除。 If the MAC is not used in the project before the end of the next period of time, it is deleted.

S24-2GEOC48支持隔离模式,此时端口0~23的每个端口只允许直接与基于OC-48的上行链路端口通信。 S24-2GEOC48 supports isolation mode, where each port 0 to port 23 only allows direct communication with the port on the upstream link to OC-48. 因此,该模式保证来自端口0~23中一个端口的数据不会被其他端口直接看到。 Thus, to ensure the pattern from 0 to 23, a data port one port to other port can not be seen directly. 这种特性通常是在住宅接入到ISP(因特网服务供应商)应用中希望得到的,从而提供用户传送数据的保密性。 This characteristic is usually desirable in residential access to an ISP (Internet service provider) obtained in the application, thereby providing privacy of user data transmitted.

S24-2GEOC48采用标准严格端口接口使外部主机接入内部寄存器,如图14所示的管理总线。 S24-2GEOC48 strict standard port interface external host access the internal registers, the management bus 14 as shown in FIG. 这种接口由3个管脚组成:TRANSMIT DATA、RECEIVEDATA和GROUNG。 This interface is composed of three pins: TRANSMIT DATA, RECEIVEDATA and GROUNG. TRANSMIT DATA和RECEIVE DATA管脚提供向S24-2GEOC48的地址和数据内容的输入。 RECEIVE DATA TRANSMIT DATA and provides input to the address pins and data content of S24-2GEOC48. 提供一个简单的2线串行接口,允许从EEPROM配置S24-2GEOC48。 Provide a simple 2-wire serial interface, the EEPROM configuration allows S24-2GEOC48. VHS108采用一个带一个I2C接口的4K比特EEPROM。 VHS108 using a 4K-bit EEPROM with an I2C interface.

支持EOS应用的另外一个实例是系统供应商在其设备中提供连接10/100/1000M以太网交换机的以太网接口,以及连接SDH/SONET传输系统的OC-3/STM-1或OC-48/STM-16接口。 EOS support application further example is a system vendor connection 10/100 / 1000M Ethernet interface Ethernet switch in the device, and in connection SDH / SONET transmission system according to OC-3 / STM-1 or OC-48 / STM-16 interfaces. 在另外一端,采用相反的变换形式。 At the other end, with the transformation to the contrary.

图15所示为根据本发明一实施例的SDH专用网连接带EOS装置的10BASE-T和100BASE-T2层交换机、1000BASE-x交换机的示意图。 FIG 15 is a 10BASE-T SDH network dedicated to an embodiment of the present invention is connected with EOS device and 100BASE-T2 layer switch, a schematic view of the switch shown in 1000BASE-x. 如图所示,当在以太网交换机和传输设备(如ADM)之间进行通信时,本发明的EOS装置设置在10M/100M/1000M局域网2层交换机中。 As shown, when the communication between the Ethernet switch and the transmission equipment (such as ADM), EOS device of the present invention 10M / 100M / 1000M Layer 2 LAN switch.

图16所示为根据本发明另一实施例的SDH公网连接IEEE 802.3以太网3层交换机的示例图。 As shown in FIG. 16 is a public network according to the present invention, SDH another embodiment of the IEEE 802.3 Ethernet example of Figure 3 is connected to the switch layer. 如图所示,当在以太网交换机和传输设备(如ADM)之间以全线速高速通信时,EOS装置设置在10M/100M/1000M局域网3层交换机中。 As shown, when between the Ethernet switch and the transmission equipment (such as ADM) at full line rate when the high-speed communication, the EOS device disposed 10M / 100M / 1000M LAN Layer 3 switches.

图15和16所示的示例中,根据本发明的EOS装置可另外设置在传输设备中(如ADM)。 The example shown in Figures 15 and 16, EOS device according to the invention may be additionally provided in the transmission apparatus (e.g. ADM). 通过采用这种网络体系结构,本发明的益处在于可在传输设备中提供以太网接口。 With such a network architecture, the benefits of the present invention to provide Ethernet interface in the transmission equipment. 这种网络结构能扩展以太网传送距离,拓宽传输设备的应用范围,进行接入和传输,在简化SDH/SONET情况下,可用于DWDM,使以太网和SDH/SONET结合在一起,无需ATM设备。 This network architecture Ethernet transmission distance can be extended, broaden the scope of application of the transmission device, for access and transport, in a simplified SDH / SONET, the DWDM can be used, so that Ethernet and SDH / SONET together without ATM device .

此外,将根据本发明的EOS装置连接在传输设备和局域网交换机之间,以提供点到点全双工同时双向运行,从而使以太网运行在广域网上成为一种实用方法。 Furthermore, the EOS device connector according to the invention between the transmission apparatus and the LAN switch to provide simultaneous two-way point to point full duplex operation, so that the Ethernet running over the WAN as a practical method.

另外,通过SDH/SONET的VC的级联,以太网帧可以MPEG帧以及音频帧等进行封装并传送。 Further, by concatenating the VC SDH / SONET, and Ethernet frames MPEG frames and audio frames can be packaged and transmitted the like. 同样,通过调节VC中的指针,相互隔离很远的发送端和接收端很容易达到同步。 Similarly, by adjusting the VC pointer, isolated far transmitting and receiving ends easily achieve synchronization.

工业实用性从上面参照附图的的说明可以看出,本发明揭示了一种直接将以太网适配到物理信道的新的接口装置和方法。 Industrial Applicability From the above description with reference to the accompanying drawings can be seen, the present invention discloses a new interface apparatus and method for adapting Ethernet directly to physical channel. 本发明在电信SDH/SONET传输设备上提供以太网接口,或实现远程接入数据通信设备,如核心和边缘路由器、交换机设备、基于IP的网络接入设备、线卡、高速接口单元,如直接适配MAC帧到SDH/SONET。 The present invention provides a telecommunications SDH / SONET transmission equipment Ethernet interface, or a remote access to the data communications device, such as core and edge routers, switch devices, IP based network access equipment, line cards, a high-speed interface unit such as direct adapter MAC frames to SDH / SONET. 通过简化SDH/SONET,如采用简化的SDH/SONET,以太网可用于DWDM。 By simplifying the SDH / SONET, such as a simplified SDH / SONET, Ethernet can be used for DWDM.

以上详细描述了本发明的各个方面,但是,应理解的是,本领域内的普通技术人员可依据本发明的公开对这些示例性实施例进行各种修改。 The above described various aspects of the present invention in detail, it should be understood that one of ordinary skill in the art Keyijuben disclosed invention to these exemplary embodiments and various modifications. 所作出的这些修改和变型均落入由所附权利要求限定的本发明范围和宗旨内。 Such modifications and variations are made to fall within the appended claims is defined by the scope and spirit of the present invention.

Claims (86)

  1. 1.一种从上层设备向下层设备传送数据包的数据传输装置,包括:第一接收装置,用于从上层设备接收数据包,将所述数据包转换成第一类帧;第一处理装置,用于将SAPI标识符所指示的数据包的字段和信息字段一起封装到所述第一类帧中,形成第二类帧;第二处理装置,用于将所述第二类帧封装到净荷部分,并且插入相应于所述数据包的适当开销,形成第三类帧;和第一发送装置,用于将所述第三类帧输出到下层设备。 A data transfer apparatus from the upper layer to the lower device packet transfer device, comprising: a first receiving means for receiving data packets from an upper layer, to convert the data packets into a first type of frames; first processing means for encapsulation field and information field of the packet identifier SAPI indicated by the first type of frames together to form a second type of frames; second processing means, for encapsulating the second frame type to the payload part, and inserted into appropriate overhead corresponding to the data packet, forming a third type of frames; and a first transmitting means for outputting the lower-layer frame to the third type device.
  2. 2.如权利要求1所述的数据传输装置,其中,所述第一处理装置将所述第二类帧封装成包括起始标志、含SAPI标识符的SAPI字段、控制字段、包括所述数据包的信息字段、FCS字段和结束标志的帧格式。 2. The data transmission apparatus according to claim 1, wherein the first processing means to the second type of frames includes a start flag package containing SAPI identifiers SAPI field, control field, said data comprising the packet information field, FCS, and end flag field of the frame format.
  3. 3.如权利要求2所述的数据传输装置,其中,所述第一接收装置是用于接收和缓冲输入数据包,并且适配上层设备的速率与下层设备的速率的第一FIFO。 3. The data transmission apparatus according to claim 2, wherein said first receiving means for receiving and buffering incoming data packet, and adaptation rate of the first FIFO device and the lower rate of the upper layer device.
  4. 4.如权利要求3所述的数据传输装置,还包括扰码装置,用于对所述第二类帧用从多项式g(x)=x7+1生成的帧同步扰码序列执行扰码操作。 4. The data transmission apparatus according to claim 3, further comprising scrambling means for using the second type of frames from the polynomial g (x) generates a frame sync = x7 + 1 scrambling sequence scrambling operation performed .
  5. 5.如权利要求4所述的数据传输装置,还包括指针处理装置,用于在所述第三类帧中插入指示净荷起始位置的指针。 5. The data transmission apparatus according to claim 4, further comprising a pointer processing means for inserting a pointer indicating the start position of the payload in the third class frame.
  6. 6.如权利要求5所述的数据传输装置,还包含成帧装置,用于将扰码后的第二类帧封装到所述第三类帧中。 Data transmission device according to claim 6 further comprising framing means for encapsulating the scrambled frame to the second type of the third type frame.
  7. 7.如权利要求6所述的数据传输装置,其中,所述第二类帧的起始标志和结束标志是“0x7E”。 7. The data transmission apparatus according to claim 6, wherein the second type frame start flag and the end flag is "0x7E".
  8. 8.如权利要求7所述的数据传输装置,其中,所述标志“0x7E”在帧与帧之间的时间填充期间发送。 Said data transmission apparatus as claimed in claim 7, wherein, during the transmission flag "0x7E" is filled in the time frame between the frames.
  9. 9.如权利要求8所述的数据传输装置,其中,所述成帧装置实现透明性处理(八位组填充)。 9. The data transmission apparatus according to claim 8, wherein said framing means to achieve transparency processing (octet fill).
  10. 10.如权利要求9所述的数据传输装置,其中,所述第一处理装置利用生成多项式1+x+x2+x4+x5+x7+x8+x10+x11+x12+x16+x22+x23+x26+x32对除起始标志、结束标志以及FCS字段本身之外帧的所有八位组计算32位帧校验序列字段。 10. The data transmission apparatus according to claim 9, wherein the first processing means using the generator polynomial 1 + x + x2 + x4 + x5 + x7 + x8 + x10 + x11 + x12 + x16 + x22 + x23 + x26 + x32, 32-bit frame check sequence field for all octets except start flag, end flag and the FCS field of the frame itself.
  11. 11.如权利要求5所述的数据传输装置,其中,所述净荷部分包括一个或多个用于携带所述第一类帧的净荷子部分。 11. The data transmission apparatus according to claim 5, wherein said payload portion comprises one or more payload portions carries the first sub-frame type is used.
  12. 12.如权利要求2所述的数据传输装置,其中,所述第一处理装置从所述第一接收装置获得SAPI。 12. The data transmission apparatus according to claim 2, wherein said first processing means obtains from the first receiving means SAPI.
  13. 13.如权利要求2所述的数据传输装置,其中,前一个所述第二类帧的结束标志是随后所述的第二类帧的起始标志。 13. The data transmission apparatus according to claim 2, wherein the front end of a second type of frame is a flag to mark the beginning of the subsequent second frame type.
  14. 14.如权利要求2所述的数据传输装置,里面还包括线路端包环回装置,用于将从第二类帧提取的第一类帧,环回到第一处理装置,用于测试。 14. The data transmission apparatus according to claim 2, which further comprises a loop back packet end line means, a first type of frames for a second type of frames extracted from the ring back to the first processing means, for testing.
  15. 15.如权利要求11所述的数据传输装置,其中,所述净荷部分是虚容器或虚容器的级联,虚容器是净荷子部分。 15. The data transmission device according to claim 11, wherein said payload portion is concatenated virtual container or virtual container, the virtual container is a sub-payload part.
  16. 16.根据前述权利要求中任何一个所述的数据传输装置,其中,所述开销包括以单个虚容器或级联方式的通道跟踪字节(J1)、通道BIP-8字节(B3)、信号标签字节(C2)、通道状态字节(G1)。 16. any of the preceding claims, a data transmission apparatus according to claim, wherein said overhead comprises a single or a virtual container path trace byte of the cascade (Jl), path BIP-8 byte (B3), the signal tag byte (C2), the channel status byte (G1).
  17. 17.如权利要求2到15中任何一个所述的数据传输装置,其中,所述下层为物理层,并且是SDH/SONET或简化SDH/SONET。 2 to 17. A data transmission apparatus 15 of any one of the preceding claims, wherein the lower layer is a physical layer, and is a SDH / SONET or simplified SDH / SONET.
  18. 18.如权利要求2到15中任何一个所述的数据传输装置,其中,所述上层是以太网MAC层,所述第一类帧是MAC帧,所述第二类帧是LAPS帧,所述第三类帧是SDH/SONET帧。 2 to 18. The data transmission apparatus 15 to any one of the preceding claims, wherein said upper layer is an Ethernet MAC layer, the MAC frame is the first frame type, the second type of frame is a LAPS frame, the said third type of frame is a SDH / SONET frame.
  19. 19.如权利要求2到15中任何一个所述的数据传输装置,其中,所述数据传输装置内置在SDH/SONET传输设备中。 2 to 19. The data transmission apparatus 15 to any one of the preceding claims, wherein said data transmission means built in the SDH / SONET transmission apparatus.
  20. 20.如权利要求2到15中任何一个所述的数据传输装置,其中,所述数据传输装置内置在以太网交换设备中。 2 to 20. The data transmission apparatus 15 to any one of the preceding claims, wherein said data transfer means incorporated in the Ethernet switching device.
  21. 21.如权利要求2到15中任何一个所述的数据传输装置,其中,所述数据传输装置是以太网交换设备、或以太网/快速以太网/千兆以太网2层/3层交换机或相关的路由器。 2 to 21. A data transmission apparatus 15 of any one of the preceding claims, wherein said data transmission means are Ethernet switch or Ethernet / Fast Ethernet / Gigabit Ethernet layer 2 / layer 3 switch or related to the router.
  22. 22.如权利要求20所述的数据传输装置,其中,所述以太网交换设备是以太网/快速以太网/千兆以太网2层/3层交换机或相关的路由器。 22. The data transmission apparatus according to claim 20, wherein the Ethernet switching device is an Ethernet / Fast Ethernet / Gigabit Ethernet layer 2 / layer 3 switch or router related.
  23. 23.如权利要求18所述的数据传输装置,其中,所述数据传输设备通过转换器使接收到的MAC/GMAC帧从MII/GMII同步映射到SDH/SONET模块。 23. The data transmission apparatus according to claim 18, wherein said data transmission device by converting the received allows MAC / GMAC frame synchronization map from MII / GMII to SDH / SONET module.
  24. 24.如权利要求17所述的数据传输装置,其中,为了速率适配,所述数据传输装置以{0x7d,0xdd}的形式在所述第二类帧内加入可编程速率适配填充字节(0xdd)。 24. The data transmission apparatus according to claim 17, wherein the rate adaptation for the data transfer means in the form of {0x7d, 0xdd} is added in the second type of programmable frame rate adaptation stuffing byte (0xdd).
  25. 25.一种从上层设备向下层设备传送数据包的数据传输方法,包括下列步骤:从所述上层设备接收和缓冲数据包,适配上层设备的速率和下层设备的速率,将该数据包转换成第一类帧;将SAPI标识符所指示的数据包的字段和信息字段一起封装到所述第一类帧中,形成第二类帧;将所述第二类帧封装到净荷部分,并插入所述数据包的适当开销,形成第三类帧;和将所述第三类帧输出到下层设备。 25. A method for transmitting data from the upper layer to the lower device packet transfer device, comprising the steps of: receiving from said upper device and the packet buffer, the rate of rate adaptation upper and lower equipment device, the data packet conversion a first type of frames; encapsulated packet identifier SAPI field and the information field indicated by the first type of frames together to form a second type of frames; the second type of frame is encapsulated into the payload portion, and inserts the appropriate overhead of the data packet, forming a third frame type; and the third output frame to the lower class device.
  26. 26.如权利要求25所述的数据传输方法,其中,所述第二类帧被封装成包括起始标志、含SAPI标识符的SAPI字段、控制字段、包括所述数据包的信息字段、FCS字段和结束标志的帧格式。 26. The data transmission method according to claim 25, wherein the second type comprises a frame is encapsulated as a start flag, containing SAPI identifiers SAPI field, control field, information field comprising the data packet, the FCS field and marks the end of the frame format.
  27. 27.如权利要求26所述的数据传输方法,还包含扰码步骤,用于对第二类帧用以多项式g(x)=x7+1生成的帧同步扰码序列执行扰码操作。 27. The data transmission method according to claim 26, further comprising a scrambling step for a second type of frames for the polynomial g (x) = x7 + 1 generated frame synchronous scrambling sequence scrambling operation performed.
  28. 28.如权利要求27所述的数据传输方法,还包括用于在所述第三类帧中插入指示净荷部分起始位置的指针的步骤。 The data transmission method according to claim 28. 27, further comprising the step of inserting the third type of frame pointer indicating a start position of the payload portion for.
  29. 29.如权利要求28所述的数据传输方法,还包含将扰码后的第二类帧封装到第三类帧中的步骤。 Data transfer method according to claim 29. 28, further comprising encapsulating the second type of scrambling code frame to frame type third step.
  30. 30.如权利要求28所述的数据传输方法,其中,所述第二类帧的起始标志和结束标志是“0x7E”。 30. The data transmission method according to claim 28, wherein the second type frame start flag and the end flag is "0x7E".
  31. 31.如权利要求30所述的数据传输方法,还包括透明性处理(八位组填充)的步骤。 The data transmission method according to claim 31. 30, further comprising the step of transparency processing (octet fill) of.
  32. 32.如权利要求31所述的数据传输方法,还包括计算步骤,用于利用生成多项式1+x+x2+x4+x5+x7+x8+x10+x11+x12+x16+x22+x23+x26+x32,对除起始标志、结束标志以及FCS字段本身之外帧的所有八位组计算32位帧校验序列。 32. The data transmission method according to claim 31, further comprising a calculating step of using the generator polynomial 1 + x + x2 + x4 + x5 + x7 + x8 + x10 + x11 + x12 + x16 + x22 + x23 + x26 + x32, 32-bit frame check sequence is calculated for all octets except start flag, end flag and the FCS field of the frame itself.
  33. 33.如权利要求32所述的数据传输方法,其中,所述净荷部分包括多个用于携带所述第一类帧的净荷子部分。 33. The data transmission method according to claim 32, wherein said payload portion comprises a plurality of sub-portions for carrying the payload of the first frame type.
  34. 34.如权利要求26所述的数据传输方法,其中,对于第二类帧,前一帧的结束标志是随后帧的起始标志。 The data transmission method according to claim 34. 26, wherein the second type of frames, a front end mark is followed by a frame start flag.
  35. 35.如权利要求26所述的数据传输方法,其中,所述净荷部分是虚容器或虚容器的级联,虚容器是净荷子部分。 The data transmission method according to claim 35. 26, wherein said payload portion is concatenated virtual container or virtual container, the virtual container is a sub-payload part.
  36. 36.如权利要求26到35中任何一个所述的数据传输方法,其中,所述开销包括以单个虚容器或级联方式的通道跟踪字节(J1)、通道BIP-8字节(B3)、信号标签字节(C2)、通道状态字节(G1)。 26 to 35 36. The data transmission method of any one of the preceding claims, wherein said overhead comprises a single or a virtual container path trace byte of the cascade (Jl), path BIP-8 byte (B3) , signal label byte (C2), the channel status byte (G1).
  37. 37.如权利要求26到35中任何一个所述的数据传输方法,其中,所述下层为物理层,并且是SDH/SONET或简化SDH/SONET。 26 to 35 of any one of the data transmission method, wherein the lower layer is a physical layer as claimed in claim 37, and a SDH / SONET or simplified SDH / SONET.
  38. 38.如权利要求26到35中任何一个所述的数据传输方法,其中,所述上层是以太网MAC层,所述第一类帧是MAC帧,所述第二类帧是LAPS帧,所述第三类帧是SDH/SONET帧。 As claimed in claims 26 to 38. 35. The method of any one of the data transmission, wherein the upper layer is an Ethernet MAC layer, the MAC frame is the first frame type, the second type of frame is a LAPS frame, the said third type of frame is a SDH / SONET frame.
  39. 39.如权利要求38所述的数据传输方法,其中,所述以太网层是IEEE802.3/802.3u/802.3z的以太网层。 The data transmission method as claimed in claim 39. 38, wherein said layer is an Ethernet layer Ethernet IEEE802.3 / 802.3u / 802.3z of.
  40. 40.如权利要求38所述的数据传输方法,还包括通过转换器使接收到的MAC/GMAC帧从MII/GMII同步映射到SDH/SONET模块的步骤。 40. The data transmission method according to claim 38, further comprising the step of receiving by the conversion allows the MAC / GMAC frame synchronization map from MII / GMII to SDH / SONET module.
  41. 41.如权利要求37所述的数据传输方法,为了速率适配,还包括以{0x7d,0xdd}的形式在所述第二类帧内加入可编程速率适配填充字节(0xdd)的步骤。 Step 41. The data transmission method according to claim 37, for rate adaptation, further comprising in the form of {0x7d, 0xdd} programmable rate adaptation added stuffing bytes (0xdd) in the second type frame .
  42. 42.一种从下层设备向上层设备发送由第一类帧形成的数据包的数据传输装置,包括:第二接收装置,用于从所述下层设备接收数据包;帧解析装置,用于从所述第一类帧中移去开销;第三处理装置,用于从所述第一类帧的净荷部分提取包含在信息字段中的数据和SAPI字段,形成第二类帧;确定装置,用于比较SAPI字段的值与预设值,并且当SAPI字段数据值等于所设定的值时,确定输出实际提取的数据;第四处理装置,用于将所述第二类帧转换成与数据包相应的第三类帧;和第二发送装置,用于将提取的数据包发送到所述上层设备。 42. A packet data transmission apparatus formed by a transmission device to the upper frame from the lower layer a first type apparatus, comprising: a second receiving means for receiving data from the lower-layer packets; a frame parsing means, for the removing the first type of frame overhead; third processing means for extracting the data contained in the information field and SAPI field from the payload portion of the frame of the first type, forming a second type of frames; determining means, value for comparison with a preset value of the SAPI field, and when the SAPI field data values ​​equal to a set value, determines the actual output of the extracted data; fourth processing means for converting the frame into the second category the third packet corresponding frame; and a second transmitting means for transmitting the extracted data packet to the upper layer device.
  43. 43.如权利要求42所述的数据传输装置,其中,每个所述第二类帧包括:起始标志、地址字段、控制字段、信息字段、FCS字段和结束标志,所述SAPI字段位于所述地址字段。 43. The data transmission apparatus according to claim 42, wherein each of the second type of frames comprising: a start flag, address field, control field, information field, the FCS field, and end flag, the field is located in the SAPI said address field.
  44. 44.如权利要求43所述的数据传输装置,其中,所述第二发送装置是用于接收和缓冲输入数据包,并且适配下层设备的速率与上层设备的速率的第二FIFO。 44. The data transmission apparatus according to claim 43, wherein said second transmitting means for receiving and buffering incoming data packets, and the second FIFO rate adaptation rate lower device the upper layer device.
  45. 45.如权利要求44所述的数据传输装置,还包括解扰装置,用于对所述第一类帧用以多项式为g(x)=x7+1生成的帧同步扰码序列执行解扰操作。 45. The data transmission apparatus according to claim 44, further comprising descrambling means for the first type of frames for polynomial g (x) = x7 + 1 frame synchronous scrambling sequence generated descrambling operating.
  46. 46.如权利要求45所述的数据传输装置,还包括指针处理装置,用于采用指针对封装在所述第一类帧中的净荷部分起始位置定位。 The data transmission apparatus according to claim 46. 45, further comprising a pointer processing means for using the positioning means for the starting position of the payload portion of the package in the first frame type.
  47. 47.如权利要求46所述的数据传输装置,其中,所述第二类帧的起始标志和结束标志是“0x7E”。 47. The data transmission apparatus according to claim 46, wherein the second type frame start flag and the end flag is "0x7E".
  48. 48.如权利要求47所述的数据传输装置,其中,所述帧解析装置移去帧间填充。 48. The data transmission apparatus according to claim 47, wherein said means for removing the inter-frame analysis filled.
  49. 49.如权利要求48所述的数据传输装置,其中,所述帧解析装置执行透明性处理。 48, the data transmission apparatus as claimed in claim 49., wherein the frame analysis means performs the transparency process.
  50. 50.如权利要求49所述的数据传输装置,其中,通过利用生成多项式1+x+x2+x4+x5+x7+x8+x10+x11+x12+x16+x22+x23+x26+x32对起始标志和结束标志间的所有八位组计算FCS,来校验所述接收的FCS字段。 50. The data transmission apparatus according to claim 49, wherein, by using the generator polynomial starting 1 + x + x2 + x4 + x5 + x7 + x8 + x10 + x11 + x12 + x16 + x22 + x23 + x26 + x32 of All calculated FCS octets between the start and end flags, to verify the FCS field of the received.
  51. 51.如权利要求50所述的数据传输装置,还包括开销监控装置,用于在数据接收过程中监控所述的第一类帧中开销的状态错误。 51. The data transmission apparatus according to claim 50, further comprising overhead monitoring means for monitoring said received data during a first frame type overhead status error.
  52. 52.如权利要求51所述的数据传输装置,其中,所述净荷部分包括多个用于由所述第一类帧携带的净荷子部分。 52. The data transmission apparatus according to claim 51, wherein said payload portion comprises a plurality of sub-portions for a payload carried by the first frame type.
  53. 53.如权利要求52所述的数据传输装置,其中,对于第二类帧,前一帧的结束标志是前一帧之后的紧邻随后帧的起始标志。 53. The data transmission apparatus according to claim 52, wherein the second type of frames, a front end mark is immediately before a start flag after the subsequent frame.
  54. 54.如权利要求53所述的数据传输装置,其中,所述净荷部分是虚容器或虚容器的级联,虚容器是净荷子部分。 54. The data transmission apparatus according to claim 53, wherein said payload portion is concatenated virtual container or virtual container, the virtual container is a sub-payload part.
  55. 55.如权利要求43到54中任何一个所述的数据传输装置,其中,所述开销包括以单个虚容器或级联方式的通道跟踪字节(J1)、通道BIP-8字节(B3)、信号标签字节(C2)、通道状态字节(G1)。 43 to 54. 55. The data transmission apparatus of any one of the preceding claims, wherein said overhead comprises a single or a virtual container path trace byte of the cascade (Jl), path BIP-8 byte (B3) , signal label byte (C2), the channel status byte (G1).
  56. 56.如权利要求43到54中任何一个所述的数据传输装置,其中,所述下层为物理层,并且是SDH/SONET或简化SDH/SONET。 43 to 54. 56. The data transmission apparatus of any one of the preceding claims, wherein the lower layer is a physical layer, and is a SDH / SONET or simplified SDH / SONET.
  57. 57.如权利要求43到54中任何一个所述的数据传输装置,其中,所述上层是以太网MAC层,所述第一类帧是SDH/SONET帧,所述第二类帧是LAPS帧,所述第三类帧是MAC帧。 43 to 54. 57. The data transmission apparatus of any one of the preceding claims, wherein said upper layer is an Ethernet MAC layer, the first type of frame is a SDH / SONET frame, the second frame type is frame LAPS the third type of frame is a MAC frame.
  58. 58.如权利要求43到54中任何一个所述的数据传输装置,其中,所述数据传输装置内置在SDH/SONET传输设备中。 43 to 54. 58. The data transmission apparatus of any one of the preceding claims, wherein said data transmission means built in the SDH / SONET transmission apparatus.
  59. 59.如权利要求43所述的数据传输装置,其中,所述数据传输装置内置在以太网交换设备中。 59. The data transmission apparatus according to claim 43, wherein said data transfer means incorporated in the Ethernet switching device.
  60. 60.如权利要求43所述的数据传输装置,其中,所述数据传输装置是以太网交换设备、或以太网/快速以太网/千兆以太网2层/3层交换机或相关的路由器。 60. A data transmission apparatus as claimed in claim 43 or Ethernet / Fast Ethernet / Gigabit Ethernet layer 2 / layer 3 switch or router related claim, wherein said data transmission means is an Ethernet switching device.
  61. 61.如权利要求59所述的数据传输装置,其中,所述以太网交换设备是以太网/快速以太网/千兆以太网2层/3层交换机或相关的路由器。 61. The data transmission apparatus according to claim 59, wherein the Ethernet switching device is an Ethernet / Fast Ethernet / Gigabit Ethernet layer 2 / layer 3 switch or router related.
  62. 62.如权利要求56到61中任何一个所述的数据传输装置,其中,为了速率适配,所述数据传输装置把以{0x7d,0xdd}的形式在所述第二类帧内存在的可编程速率适配填充字节去掉。 62. 56-61 claimed in any one of said data transmission means said data transmission means in the form of {0x7d, 0xdd} in the presence of the second type frame may be required, wherein, for rate adaptation, programming rate adaptation stuffing bytes removed.
  63. 63.如权利要求56到61中任何一个所述的数据传输装置,其中,所述数据传输装置在MII/GMII接口通过转换器使作为LAPS信息字段的MAC/GMAC帧从SDH/SONET模块同步映射到接收时钟。 63. 56-61 claimed in any one of the data transmission apparatus, wherein said data transfer means in MII / GMII interfaces allows the conversion of the information field as MAC LAPS / GMAC frame synchronization mapping from SDH / SONET module the receive clock.
  64. 64.一种从下层设备向上层设备发送由第一类帧形成的数据包的数据传输方法,包括下列步骤:从所述下层设备接收数据包;从所述第一类帧中移去开销;从所述第一类帧的净荷部分提取SAPI字段和包含在信息字段中的数据,形成第二类帧;将SAPI字段的值与预设值进行比较,当SAPI字段数据值等于所设定的值时,确定输出实际提取的数据;将所述第二类帧转换成与所述数据包相应的第三类帧;和将提取的数据包发送到所述上层设备。 64. A transmitting apparatus from the lower layer to the upper layer packet data transmission method of the device is formed by the first type of frames, comprising the steps of: receiving data from the lower layer packet; frame from the first class is removed overhead; extracting the payload portion from the first frame type field and the data contained in the SAPI field information, a second type of frames; the SAPI field value with a preset value are compared, when the SAPI field data values ​​equal to a set when the value of the actual output of the extracted data is determined; converting the second type of frames corresponding to the data packet with a third type of frames; and the extracted data packet to the upper layer device.
  65. 65.如权利要求64所述的数据传输方法,其中,每个所述第二类帧包括:起始标志、地址字段、控制字段、信息字段、FCS字段和结束标志,所述SAPI字段位于所述地址字段。 65. The data transmission method according to claim 64, wherein each of the second type of frames comprising: a start flag, address field, control field, information field, the FCS field, and end flag, the field is located in the SAPI said address field.
  66. 66.如权利要求65所述的数据传输方法,还包括接收和缓冲输入数据包,适配下层设备的速率与上层设备的速率的步骤。 66. The data transmission method according to claim 65, further comprising the step of receiving rate and buffer input data packet, the adaptation rate of the lower layer and the upper layer apparatus device.
  67. 67.如权利要求66所述的数据传输方法,还包括扰码步骤,用于对所述第一类帧用以多项式为g(x)=x7+1生成的帧同步扰码序列执行解扰操作。 67. The data transmission method according to claim 66, further comprising a scrambling step for the first type of frames for polynomial g (x) = x7 + 1 frame synchronous scrambling sequence generated descrambling operating.
  68. 68.如权利要求67所述的数据传输方法,还包括采用指针对封装在所述第一类帧中的净荷的起始位置定位的步骤。 The data transmission method according to claim 68. 67, further comprising the step of using means for the payload encapsulated in the starting position of the first type frame positioned.
  69. 69.如权利要求68所述的数据传输方法,其中,所述第二类帧的起始标志和结束标志是“0x7E”。 69. The data transmission method according to claim 68, wherein the second type frame start flag and the end flag is "0x7E".
  70. 70.如权利要求69所述的数据传输方法,还包括移去帧间填充的步骤。 70. The data transmission method according to claim 69, further comprising the step of removing the filled frames.
  71. 71.如权利要求70所述的数据传输方法,其中,通过利用生成多项式1+x+x2+x4+x5+x7+x8+x10+x11+x12+x16+x22+x23+x26+x32对第二类帧的起始标志和结束标志间的所有八位组计算FCS,来校验所述接收的FCS字段。 71. The data transmission method according to claim 70, wherein, by using the generator polynomial 1 + x + x2 + x4 + x5 + x7 + x8 + x10 + x11 + x12 + x16 + x22 + x23 + x26 + x32 of the first All calculated FCS octets between the two types of frame start flag and end flag, to verify the FCS field of the received.
  72. 72.如权利要求71所述的数据传输方法,还包括用于在接收过程中监控所述的第一类帧开销的状态错误的步骤。 72. The data transmission method according to claim 71, further comprising a condition monitoring process of the first type in the received frame overhead for error step.
  73. 73.如权利要求72所述的数据传输方法,其中,所述净荷部分包括多个被所述第一类帧携带的净荷子部分。 73. The data transmission method according to claim 72, wherein said payload portion comprises a plurality of sub-portion of a payload is carried by the frame of the first type.
  74. 74.如权利要求73所述的数据传输方法,其中,对于第二类帧,前一帧的结束标志是随后帧的起始标志。 74. The data transmission method according to claim 73, wherein the second type of frames, a front end mark is followed by a frame start flag.
  75. 75.如权利要求74所述的数据传输方法,其中,所述净荷部分是虚容器或虚容器的级联,虚容器是净荷子部分。 75. The data transmission method according to claim 74, wherein said payload portion is concatenated virtual container or virtual container, the virtual container is a sub-payload part.
  76. 76.如权利要求65到75中任何一个所述的数据传输方法,其中,所述开销包括以单个虚容器或级联方式的通道跟踪字节(J1)、通道BIP-8字节(B3)、信号标签字节(C2)、通道状态字节(G1)。 65-75 76. The data transmission method of any one of the preceding claims, wherein said overhead comprises a single or a virtual container path trace byte of the cascade (Jl), path BIP-8 byte (B3) , signal label byte (C2), the channel status byte (G1).
  77. 77.如权利要求65到75中任何一个所述的数据传输方法,其中,所述下层为物理层,并且是SDH/SONET或简化SDH/SONET。 77. 65-75 any one of the data transmission method, wherein the lower layer is a physical layer as claimed in claim, and a SDH / SONET or simplified SDH / SONET.
  78. 78.如权利要求65到75中任何一个所述的数据传输方法,其中,所述上层是以太网MAC层,所述第一类帧是SDH/SONET帧,所述第二类帧是LAPS帧,所述第三类帧是MAC帧。 78. The as claimed in any of claims 65-75 according to a data transmission method, wherein said upper layer is an Ethernet MAC layer, the first type of frame is a SDH / SONET frame, the second frame type is frame LAPS the third type of frame is a MAC frame.
  79. 79.如权利要求78所述的数据传输方法,其中,所述以太网层为IEEE802.3/802.3u/802.3z以太网层。 79. The data transmission method according to claim 78, wherein said layer is an Ethernet IEEE802.3 / 802.3u / 802.3z Ethernet layer.
  80. 80.如权利要求77所述的数据传输方法,为了速率适配,还包括把以{0x7d,0xdd}的形式在所述第二类帧内存在的可编程速率适配填充字节去掉的步骤。 80. The data transmission method according to claim 77, for rate adaptation, further comprising the step of removing the stuffing bytes in the form of {0x7d, 0xdd} programmable rate adaptation in the presence of the second type frame .
  81. 81.如权利要求78所述的数据传输方法,还包括在MII/GMII接口通过转换器使LAPS信息字段(MAC/GMAC帧)从SDH/SONET模块到RX_CLK同步的步骤。 81. The data transmission method according to claim 78, further comprising MII / GMII interfaces converter enables LAPS information field (MAC / GMAC frame) from the SDH / SONET synchronization module to RX_CLK step.
  82. 82.一种在上层设备和下层设备之间发送数据包的数据包接口装置,包括根据权利要求1所述的数据传输装置和根据权利要求42所述的数据传输装置。 82. A packet transmission apparatus of a packet in the interface between the upper device and the lower device, comprising a data transmission device and data transmission device according to claim 42 according to claim 1.
  83. 83.如权利要求82所述的数据包接口装置,其中所述第二类帧被封装成包括起始标志、含SAPI标识符的SAPI字段、控制字段、包括所述数据包的信息字段、FCS字段和结束标志的帧格式。 83. The packet data interface device according to claim 82, wherein the second type comprises a frame is encapsulated as a start flag, containing SAPI identifiers SAPI field, control field, information field comprising the data packet, the FCS field and marks the end of the frame format.
  84. 84.如权利要求82或83所述的数据包接口装置,还包括线路端接口装置,用于从下层设备发送/接收数据包。 84. The packet data interface apparatus of claim 82 or claim 83, further comprising a line-side interface means for transmitting from the lower device / receive data packets.
  85. 85.如权利要求84所述的数据包接口装置,还包括变换装置,用于在发送方向,使上层设备的数据包与输入到所述第一接收装置过程的数据包同步;在接收方向,使从第二发送装置提取的数据包与所述上层设备的数据包同步。 85. The packet data interface device according to claim 84, further comprising converting means for transmitting direction, so that the data packet to an upper layer device with the input means receiving the first data packet during synchronization; In the receive direction, synchronizing the second data packet data packet transmitting means extracts the upper layer device.
  86. 86.如权利要求85所述的数据包接口装置,还包括:微处理器接口装置,用于使所述数据接口装置能访问其中的所有寄存器;用于测试的JTAG端口;用于暂时缓冲输入/输出配置数据的GPIO寄存器。 86. The packet data interface device according to claim 85, further comprising: a microprocessor interface means, said data interface means for enabling access to all registers therein; a JTAG test port; an input buffer for temporarily / GPIO register data output configuration.
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