CN1373507A - Low-voltage flash memory cell erased/written via channel and its preparing process - Google Patents
Low-voltage flash memory cell erased/written via channel and its preparing process Download PDFInfo
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- CN1373507A CN1373507A CN01109117.7A CN01109117A CN1373507A CN 1373507 A CN1373507 A CN 1373507A CN 01109117 A CN01109117 A CN 01109117A CN 1373507 A CN1373507 A CN 1373507A
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- 238000000034 method Methods 0.000 title claims description 24
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 239000004744 fabric Substances 0.000 claims description 131
- 150000002500 ions Chemical class 0.000 claims description 17
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 17
- 229920005591 polysilicon Polymers 0.000 claims description 17
- 238000005530 etching Methods 0.000 claims description 13
- 239000004065 semiconductor Substances 0.000 claims description 11
- 238000004519 manufacturing process Methods 0.000 claims description 10
- 239000002184 metal Substances 0.000 claims description 9
- 238000007254 oxidation reaction Methods 0.000 claims description 9
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 7
- 230000008021 deposition Effects 0.000 claims description 6
- 239000000463 material Substances 0.000 claims description 5
- 230000003647 oxidation Effects 0.000 claims description 4
- 230000003628 erosive effect Effects 0.000 claims description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 2
- 230000012010 growth Effects 0.000 claims description 2
- 239000004576 sand Substances 0.000 claims description 2
- 229910052710 silicon Inorganic materials 0.000 claims description 2
- 239000010703 silicon Substances 0.000 claims description 2
- 238000005516 engineering process Methods 0.000 description 7
- 239000000725 suspension Substances 0.000 description 7
- 230000000694 effects Effects 0.000 description 5
- 238000002360 preparation method Methods 0.000 description 5
- 238000002955 isolation Methods 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 2
- 238000004891 communication Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000007667 floating Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 230000008635 plant growth Effects 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 230000010415 tropism Effects 0.000 description 1
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Abstract
A low-voltage flash memory cell erased via channel is prepared through generating a deep P-well on N-substrate, generating N-well on deep P-well, arranging deep P-region and shallow P-region in N-well, and arranging N-regions in deep P-region and shallow P-region. Its advantages are very low leakage, less circuit complexity and high operation efficiency.
Description
The present invention relates to a kind of low-voltage and through erasable flash memory cell of passage and preparation method thereof, mainly be by adding triple wells (Triple Well) structure so that can apply respectively with voltage to suprabasil dark p type wells of N type and N type well during operation, make its issuable leakage current reduce to minimum, end-point voltage when effectively reducing erase operation, reduce the complexity of the required charge pump line design of overall structure, and then reach the purpose that improves operating efficiency.
Flash memory (Flash Memory) is owing to having the non-volatility memorizer function of electric erasable data, so generally be used in as in the information electronic products such as portable laptop computer or communication apparatus.And general using passage richness is reined in the structure that a Nuo Dehaimu effect (Channel Fowler-Nordheim effect) is operated this flash memory cell, can be more and more intensive because of its array structure demand, and then cause each storage-to-storage operation to influence each other, so utilize the memory of this effect design, its array closeness has certain restriction, and according to the Taiwan patent No. 87116135 disclosed technology contents, " the flash memory unit structure manufacture method and its method of operation that write/erase via passage ", just can effectively improve this situation, as shown in Figure 1, be the existing flash memory cell sectional view that writes/erase via passage; As shown in the figure, it forms a N type well (N-Well) 12 in a P type substrate 10, implanting ions has a N type cloth to plant district 15 respectively in this N type well 12, be its drain region, and a P type cloth plant the district 16, and N type cloth plant the district 15 times also implanting ions have another P type cloth plant the district 17, because this P type cloth is planted district 17, cloth is planted the degree of depth and is planted district 16 much larger than this P type cloth, thus can be as a p type wells, and this another P type cloth is planted district 17 and is planted with this P type cloth and distinguish 16 mutually in succession; In addition, this N type cloth plant district's other end of 16 also the cloth value have a N type cloth to plant district 18, be its source area, this P type cloth plant district 16 above then be provided with one and pile up lock G.
But according to this prior art, the source area of this flash memory cell might not be positioned on the offside of drain region, be independently source area, and extremely corresponding well in each drain region, so when density increases, therefore the shortcoming that can cause source electrode to extend through with the drain region not can increase the closeness of manufacturing.
But, when wiping, if alleviate the burden of charge pump circuit, desire is used lower end-point voltage, be applied to word line and source electrode line one less positive voltage and negative voltage respectively and the former positive voltage that is applied to word line and source electrode line earthed voltage changed into, it is applied to the source electrode line negative voltage of N type well 12, just can produce a forward bias voltage drop on the PN interface of 10 of the P type substrates of this N type well 12 and ground connection, and causes a leakage current IL indirectly and then make this erase operation failure.
Main purpose of the present invention is to provide a kind of low-voltage and through erasable flash memory cell of passage and preparation method thereof, in substrate, form a dark P type and reach a N type well, i.e. triple wells, when operation, can apply respectively with voltage to suprabasil dark P type of N type and N type well, two voltages are offseted, avoid top, PN interface to conducting, lower leakage current.
Secondary objective of the present invention is to provide a kind of low-voltage and through erasable flash memory cell of passage and preparation method thereof, by adding triple wells (Triple Well), when operation, can apply respectively with voltage to suprabasil dark p type wells of N type and N type well, end-point voltage when effectively reducing erase operation, reduce the complexity of the required charge pump line design of overall structure, improve operating efficiency.
Another purpose of the present invention is to provide a kind of low-voltage and through erasable flash memory cell of passage and preparation method thereof, by the change of tunnel oxide structure, reduces and write the fashionable interference that produces.
The objective of the invention is to realize by the following technical solutions:
A kind of low-voltage and through the manufacture method of the erasable flash memory cell of passage, implanting ions one dark p type wells layer in a N type substrate; Implanting ions one N type well layer in this dark p type wells layer; Plant the district at this N type well laminar surface implanting ions one shallow P type cloth; Plant growth one passage oxide layer in the district at this shallow P type cloth, and deposit a polysilicon layer; This passage oxide layer of etching and this polysilicon layer; One oxide-film-silicon nitride film-oxide-film (0NO) layer is established in erosion on the passage oxide layer of this etching Hou and polysilicon layer; Deposition one polysilicon layer on this oxide-film-silicon nitride film-oxidation film layer; Each grown layer and sedimentary deposit on this passage oxide layer of etching form a rectangle stack layer, and these rectangle stack layer both sides are exposed passage oxide layer block; Carry out oxidation, between this rectangle stack layer and this N type well surface, form a smile shape oxide layer; Side implanting ions one dark P type cloth at this rectangle stack layer is planted the district, and is located in this N type well layer; Above N type cloth of implanting ions is planted the district in this N type well floor, and it is positioned at the both sides of this rectangle stack layer.
Described dark P type cloth is planted position and this shallow P type cloth and is planted and distinguish a side and join, and this dark P type cloth cloth of planting the district is planted the degree of depth and planted the district greater than this shallow P type cloth.
Described N type cloth is planted the district and is positioned at this dark P type cloth and plants the district.
The manufacture method of above-mentioned flash memory cell also comprises the following steps: to deposit a polysilicon layer, covers this rectangle stack layer and both sides thereof; Etching is positioned at many product silicon layer part of this rectangle stack layer one side, forms a passage, and making this cloth be implanted with dark P type cloth, to plant the N type well floor that district and a N type cloth plants the district partly exposed; Connect at the etched passage of this polycrystalline layer of sand and to establish a metal contact pin, itself and this cloth is implanted with dark P type cloth and plants district and N type cloth and plant a N type well floor in district and partly join.
Described P type semiconductor and N type semiconductor material can be changed each other.
A kind of low-voltage and through the erasable flash memory cell of passage, it includes: a N type substrate; One is formed on this suprabasil dark p type wells; One be formed on this dark p type wells and in this N type well appropriate location cloth be implanted with that a dark P type cloth is planted the district and a shallow P type cloth is planted the N type well in district; One be located at this N type aboveground pile up gate.
In this N type well and pile up and also include an oxide layer between the lock.
Pile up to lose between lock and oxide layer and be provided with smile type pattern.
This dark P type cloth in this N type well is planted and is gone back cloth in the district and be implanted with a N type cloth and plant the district, and it is the drain region.
The cloth that this dark P type cloth in this N type well is planted the district is planted the degree of depth and is planted the district greater than this shallow P type cloth.
This dark P type cloth in this N type well is planted the district and is provided with the part that is connected with the end that this shallow P type cloth is planted the district.
Shallow P type cloth is planted the opposite side in district in this N type well, also is provided with a N type cloth and plants the district, and it is a source area.
It is characterized in that: the N type cloth that this dark P type cloth is planted Qu Buzhi is planted the district and this dark P type cloth is planted to have between the district and is electrically connected.
This is electrically connected is one to run through N type cloth that this dark P type cloth plants Qu Buzhi and plant the district and plant the Metal Contact of distinguishing the face that connects with this dark P type cloth.
This be electrically connected the N type cloth of planting Qu Buzhi for this dark P type cloth that will expose with a Metal Contact plant the district plant being connected of district with this dark P type cloth.
Described P type semiconductor and N type semiconductor material can be changed each other.
The present invention is described in further detail below in conjunction with drawings and Examples:
Fig. 1 is existing through the erasable flash memory cell sectional view of passage.
Fig. 2 is each flow process cutaway view of flash memory cell one preferred embodiment of the present invention.
Fig. 3 is one of each flow process cutaway view of flash memory cell one preferred embodiment of the present invention.
Fig. 4 is two of each flow process cutaway view of flash memory cell one preferred embodiment of the present invention.
Fig. 5 is three of each flow process cutaway view of flash memory cell one preferred embodiment of the present invention.
Fig. 6 is four of each flow process cutaway view of flash memory cell one preferred embodiment of the present invention.
Fig. 7 is five of each flow process cutaway view of flash memory cell one preferred embodiment of the present invention.
Fig. 8 is six of each flow process cutaway view of flash memory cell one preferred embodiment of the present invention.
Fig. 9 is seven of each flow process cutaway view of flash memory cell one preferred embodiment of the present invention.
Figure 10 is eight of each flow process cutaway view of flash memory cell one preferred embodiment of the present invention.
Figure 11 is nine of each flow process cutaway view of flash memory cell one preferred embodiment of the present invention.
Figure 12 is ten of each flow process cutaway view of flash memory cell one preferred embodiment of the present invention.
Figure 13 is 11 of each flow process cutaway view of flash memory cell one preferred embodiment of the present invention.
Figure 14 is the erase operation schematic sectional view of flash memory cell one preferred embodiment of the present invention.
At first, as Fig. 2 to Figure 13, the main manufacture method of the present invention includes:
Semiconductor N type substrate (N-substrate) 20 is provided, utilizes lithography and the specific region of field oxide technology in substrate 20 to form more than one oxide isolation regions (Field oxide; FOX) 21, and between each oxide isolation regions 21, implanting ions one dark p type wellses (Deep P-Well) layers 22 in the substrate 200;
Utilize implanting ions technology cloth in the dark p type wells layer 22 of substrate 20 to plant a N type well (N-well) layer 24;
Utilize implanting ions technology cloth on these N type well floor 24 surfaces to plant a shallow P type cloth and plant district 26; In this N type well superficial growth one passage oxide layer (Tunnel oxide) 31, on passage oxide layer 31, pile up deposition one first polysilicon layer 32 again;
Utilize little shadow and etching technique to formulate passage oxide layer 31 and these first polysilicon layer, 32 patterns;
Deposition one oxide-film-silicon nitride film-oxidation film layer 33 on the passage oxide layer 31 after this etching and first polysilicon layer 32, and this layer 33 of etching;
On oxide-film-silicon nitride film-oxidation film layer 33 surfaces, pile up deposition one second polysilicon layer 35;
Utilize second polysilicon layer 35 on non-equal tropism's dry etching technology etching N type well layer 24, oxide-film-silicon nitride film-oxidation film layer 33, first polysilicon layer 32 till expose passage oxide layer 31, promptly form a rectangle stack layer 30, only keep part passage oxide layer 31 blocks that are across 21 of two oxide isolation regions, be that rectangle stack layer 30 both sides are exposed passage oxide layer 31 blocks, and utilize oxidation to form thicker tunnel oxide at rectangle stack layer 30 edges, form smile type (Smiling Effect) oxide layer part 312;
Utilize the implanting ions technology, cloth is planted a dark P type cloth and is planted district 27 in the N type well floor 24 of the left side of rectangle stack layer 30, and cloth are planted a shallow P type cloth and are planted district 26 in the below N type well floor 24 of rectangle stack layer 30, and the wherein dark P type cloth cloth of planting district 27 is planted the cloth that the degree of depth plants district 26 greater than shallow P type cloth and planted the degree of depth;
Utilize the implanting ions technology again, in the both sides of rectangle stack layer 30, cloth is planted two N type cloth and is planted district 25 and 28 in the N type well floor, and wherein the N type cloth in rectangle stack layer 30 left sides is planted district 25 and is implanted in this dark P type cloth and plants in the district 27;
Deposit one the 3rd polysilicon layer 37, cover exposed passage oxide layer 31 blocks in this rectangle stack layer 30 and both sides thereof;
Etching is positioned at insulating barrier 37 parts in rectangle stack layer 30 left sides, make it form a contact hole (Contacthole) 38, make cloth be implanted with dark P type cloth and plant district's 27 and one N type cloth to plant district 25 partly exposed, and wherein dark P type cloth plants district 27 and plant district 25 with N type cloth, make being electrically connected of a metal 29;
At last, carry out metal connection, promptly see through insulating barrier 37 etched contact holes 38 and connect and establish a metal contact pin 39 and be implanted with dark P type cloth to this cloth and plant district 27 and N type cloth and plant and distinguish 25.
As shown in figure 14, be the erase operation schematic sectional view of flash memory cell one preferred embodiment of the present invention, it includes a N type substrate 20, forms a dark p type wells 22 in this substrate 20, forms a N type well 24 and pile up on this dark p type wells 22; In this N type well 24 cloth be implanted with a dark P type cloth plant the district 27 and one shallow P type cloth plant the district 26, this dark P type cloth plant the district 27 with this shallow P type cloth plant the district 26 1 ends link to each other, and wherein this dark P type cloth is planted the district and is gone back cloth in 27 and be implanted with a N type cloth and plant district 25, planting district 27 with this dark P type cloth does and is electrically connected, be its drain region, and P type cloth plant district's side of 26 also cloth be implanted with a N type cloth and plant district 28, be its source area; The cloth that dark P type cloth is planted district 27 is planted the cloth that the degree of depth plants district 26 greater than this shallow P type cloth and is planted the degree of depth, and promptly this dark P type cloth is planted the district and also be can be used as a P type and use; Then be provided with a passage oxide layer 31 on this N type well 24, and with pile up control gate G, form a smile type (Smiling Effect) with oxidation and connect face portion, (Program Disturb) disturbed in the programming that produces in the time of so just can reducing encoding operation by the change that penetrates oxide layer 31 structures; Pile up control gate G and also include control gate (control gate) and floating grid (flow gate).
When the present invention operates under the low-voltage condition, can apply same electrical respectively and be pressed onto dark p type wells 22 and N type well 24 in the N type substrate 20, as source electrode line voltage V
SLAnd dark p type wells voltage V
Deep P-WellMake its issuable leakage current reduce to minimum; As shown in Table 1: during as if the enforcement erase operation, promptly set source electrode line voltage V
SLFor-8V, dark p type wells voltage V
Deep P-WellFor-8V, word line voltage V
WLBe 10V, so, source electrode line voltage V
SLAnd dark p type wells voltage V
Deep P-WellJust can repeal by implication, make the PN interface of 20 of dark p type wells 22 and the substrates of N type can not produce forward bias voltage drop, reach the purpose that reduces leakage current.Table one
| Word line voltage V BL | Word line voltage V WL | Source electrode line voltage V SL | Dark p type wells voltage V deep?P-Well | |||
| Choose | Do not choose | Choose | Do not choose | |||
| Coding | ??6V | ???0V | ???-10V | Suspension joint | Suspension joint | ????0V |
| Wipe | Suspension joint | Suspension joint | ???10V | Suspension joint | ????-8V | ????-8V |
| Read | ??0V | Suspension joint | ???4V | Suspension joint | ????1V | ????0V |
Above-mentioned only is a preferred embodiment of the present invention, and the interchangeable material of P type semiconductor and N type semiconductor in this structure also can be P-Well/DeepN-We/P-substrate as N-Well/Deep P-Well/N-substrate pattern.
Claims (16)
1, a kind of low-voltage and through the manufacture method of the erasable flash memory cell of passage, it is characterized in that: it comprises the steps:
A, in a N type substrate implanting ions one dark p type wells layer;
B, in this dark p type wells layer implanting ions one N type well layer;
C, plant the district at this N type well laminar surface implanting ions one shallow P type cloth;
D, plant in the district growth one passage oxide layer, and deposit a polysilicon layer at this shallow P type cloth;
E, this passage oxide layer of etching and this polysilicon layer;
F, one oxide-film-silicon nitride film-oxide-film (0NO) layer is established in erosion on the passage oxide layer of this etching Hou and polysilicon layer;
G, on this oxide-film-silicon nitride film-oxidation film layer the deposition one polysilicon layer;
Each grown layer and sedimentary deposit on h, this passage oxide layer of etching form a rectangle stack layer, and these rectangle stack layer both sides are exposed passage oxide layer block;
I, carry out oxidation, between this rectangle stack layer and this N type well surface, form a smile shape oxide layer;
J, plant the district, and be located in this N type well layer at a side implanting ions one dark P type cloth of this rectangle stack layer;
K, above N type cloth of implanting ions is planted the district in this N type well floor, and it is positioned at the both sides of this rectangle stack layer.
2, low-voltage as claimed in claim 1 and through the manufacture method of the erasable flash memory cell of passage, it is characterized in that: described dark P type cloth is planted position and this shallow P type cloth and is planted and distinguish a side and join, and this dark P type cloth cloth of planting the district is planted the degree of depth and planted the district greater than this shallow P type cloth.
3, low-voltage as claimed in claim 1 and through the manufacture method of the erasable flash memory cell of passage is characterized in that: described N type cloth is planted the district and is positioned at this dark P type cloth and plants the district.
4, low-voltage as claimed in claim 1 and through the manufacture method of the erasable flash memory cell of passage, it is characterized in that: it also comprises the following steps:
1, deposition one polysilicon layer covers this rectangle stack layer and both sides thereof;
M, etching are positioned at many product silicon layer part of this rectangle stack layer one side, form a passage, and this cloth is planted
There have dark P type cloth to plant the N type well floor that district and a N type cloth plants the district to be partly exposed;
N, connect at the etched passage of this polycrystalline layer of sand and to establish a metal contact pin, itself and this cloth is implanted with dark P type cloth
Planting the N type well floor that district and N type cloth plants the district partly joins.
5, low-voltage as claimed in claim 1 and through the manufacture method of the erasable flash memory cell of passage, it is characterized in that: described P type semiconductor and N type semiconductor material can be changed each other.
6, a kind of low-voltage and through the erasable flash memory cell of passage, it is characterized in that: it includes:
One N type substrate;
One is formed on this suprabasil dark p type wells;
One be formed on this dark p type wells and in this N type well appropriate location cloth be implanted with that a dark P type cloth is planted the district and a shallow P type cloth is planted the N type well in district;
One be located at this N type aboveground pile up gate.
7, flash memory cell as claimed in claim 6 is characterized in that: in this N type well and pile up and also include an oxide layer between the lock.
8, flash memory cell as claimed in claim 7 is characterized in that: pile up between lock and oxide layer erosion and be provided with smile type pattern.
9, flash memory cell as claimed in claim 6 is characterized in that: this dark P type cloth in this N type well is planted and is gone back cloth in the district and be implanted with a N type cloth and plant the district, and it is the drain region.
10, flash memory cell as claimed in claim 6 is characterized in that: the cloth that this dark P type cloth in this N type well is planted the district is planted the degree of depth and is planted the district greater than this shallow P type cloth.
11, flash memory cell as claimed in claim 6 is characterized in that: this dark P type cloth in this N type well is planted the district and is provided with the part that is connected with the end that this shallow P type cloth is planted the district.
12, flash memory cell as claimed in claim 6 is characterized in that: shallow P type cloth is planted the opposite side in district in this N type well, also is provided with a N type cloth and plants the district, and it is a source area.
13, flash memory cell as claimed in claim 6 is characterized in that: the N type cloth that this dark P type cloth is planted Qu Buzhi is planted the district and this dark P type cloth is planted to have between the district and is electrically connected.
14, flash memory cell as claimed in claim 13 is characterized in that: this is electrically connected is one to run through N type cloth that this dark P type cloth plants Qu Buzhi and plant the district and plant the Metal Contact of distinguishing the face that connects with this dark P type cloth.
15, flash memory cell as claimed in claim 13 is characterized in that: this be electrically connected the N type cloth of planting Qu Buzhi for this dark P type cloth that will expose with a Metal Contact plant the district plant being connected of district with this dark P type cloth.
16, flash memory cell as claimed in claim 6 is characterized in that: described P type semiconductor and N type semiconductor material can be changed each other.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB011091177A CN1185701C (en) | 2001-03-06 | 2001-03-06 | Low-voltage flash memory cell erased/written via channel and its preparing process |
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| Application Number | Priority Date | Filing Date | Title |
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| CNB011091177A CN1185701C (en) | 2001-03-06 | 2001-03-06 | Low-voltage flash memory cell erased/written via channel and its preparing process |
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| CN1373507A true CN1373507A (en) | 2002-10-09 |
| CN1185701C CN1185701C (en) | 2005-01-19 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100377335C (en) * | 2004-04-30 | 2008-03-26 | 东部亚南半导体株式会社 | Method for fabricating flash memory device |
| CN101454842B (en) * | 2006-06-01 | 2012-11-14 | 密克罗奇普技术公司 | A method for programming and erasing an array of nmos eeprom cells that minimize bit disturbances and voltage withstand requirements for the memory array and supporting circuits |
| CN108054168A (en) * | 2017-11-14 | 2018-05-18 | 上海华力微电子有限公司 | Flash memory unit structure and its manufacturing method |
-
2001
- 2001-03-06 CN CNB011091177A patent/CN1185701C/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100377335C (en) * | 2004-04-30 | 2008-03-26 | 东部亚南半导体株式会社 | Method for fabricating flash memory device |
| CN101454842B (en) * | 2006-06-01 | 2012-11-14 | 密克罗奇普技术公司 | A method for programming and erasing an array of nmos eeprom cells that minimize bit disturbances and voltage withstand requirements for the memory array and supporting circuits |
| CN108054168A (en) * | 2017-11-14 | 2018-05-18 | 上海华力微电子有限公司 | Flash memory unit structure and its manufacturing method |
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| CN1185701C (en) | 2005-01-19 |
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