CN1366732A - Voltage limiting bias circuit for reduction of hot electron degradation effects in MOS cascode circuits - Google Patents
Voltage limiting bias circuit for reduction of hot electron degradation effects in MOS cascode circuits Download PDFInfo
- Publication number
- CN1366732A CN1366732A CN01800836.4A CN01800836A CN1366732A CN 1366732 A CN1366732 A CN 1366732A CN 01800836 A CN01800836 A CN 01800836A CN 1366732 A CN1366732 A CN 1366732A
- Authority
- CN
- China
- Prior art keywords
- voltage
- transistor
- drain
- circuit
- source
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/08—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements
- H03F1/22—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements by use of cascode coupling, i.e. earthed cathode or emitter stage followed by earthed grid or base stage respectively
- H03F1/223—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements by use of cascode coupling, i.e. earthed cathode or emitter stage followed by earthed grid or base stage respectively with MOSFET's
Abstract
MOS Cascode amplifier circuits are subject to long-term or instantaneous changes (degradation) of performance characteristics by excess substrate currents. These currents can be generated in the grounded source transistor of the cascode connected output transistors during peak excursions of drain-source voltage across the grounded source transistor when the output voltage of the MOS Cascode amplifier circuit is at a maximum. An improved MOS Cascode amplifier circuit arrangement includes a voltage limiting bias circuit arrangement of additional transistors. The bias circuit arrangement acts as a series voltage-limiting device between the MOS Cascode amplifier circuit output node and the drain node of the upper-most cascode connected transistors when the MOS Cascode amplifier circuit output voltage is at its maximum value. An embodiment of the improved MOS Cascode amplifier circuit arrangement is arranged to limit the drain-source voltage excursion peak on the sensitive cascode transistor to a value below a pre-selected critical voltage, Vcrit. Vcrit is defined as the drain-source voltage value for the sensitive cascode transistor for which the instantaneous and/or cumulative substrate current caused by peak drain-source voltage excursions greater than Vcrit would instantaneously or cumulatively degrade the transistor's sensitive electrical parameters to an extent that would degrade (an) amplifier performance characteristic(s) to an appreciable degree. The additional transistors of one embodiment of the bias circuit arrangement are connected by internal adjacent source-drain nodes as a sequential chain with gates biased at respective fixed voltages. One external drain node of the chain connects to the output node of the MOS cascode amplifier and one external source node of the chain connects to drain of the uppermost cascode connected transistors.
Description
Technical field
The present invention relates generally to stablize the behavior in service of MOS circuit, particularly the restriction from the caused Performance And Reliability to the cascode amplifying circuit of the extra base current that hot electron caused of high source drain voltage is minimized.
Background technology
In MOS amplifier and current reflection circuit, the transistor of deflection saturation region may stand a undesirable base current being produced by ionization by collision effect (owing to so-called " hot electron " effect).Ionization by collision in the MOSFET raceway groove acts on and is described in the works and known by the circuit design practitioner usually.
A kind of physical model of this effect is described in the single p groove n channel transistor 300 of Fig. 3.Transistor 300 is represented as the deflection saturation region, that is, the minor face edge that gate oxide 304 following inversion layers 302 are sentenced actual electric leakage diffusion 306 at a pinch-off point 308 is an end.This pinch-off point 308 appears at the value Vdssat place of a source drain voltage (Vds).Source drain voltage Vds increases above the Vdssat value, and drain current Id relatively increases seldom.As Vds during greater than Vdssat, the position of pinch-off point 308 is represented as the actual edge of diffusion 306.
At constant power supply grid voltage Vgs place, relatively move seldom with the increase pinch-off point 308 of Vds.Therefore, drain current ID relatively changes seldom too.This is indicated in the V-I characteristic of accompanying drawing 5, and at this, ID and Vds operating characteristic represent that transistor operates in one of two zones, that is, and and the saturation region that has the triode region of low source-drain impedance and have the high source drain impedance.
Surpass Vdssat, the voltage of nearly all increase between the transistor area between inversion layer end 308 and 306 the edge of draining keeps near drain electrode and power supply.At abundant high Vds place, at inversion layer 302 with drain that the electric field in the loss district can cause that electronics flows to drain electrode 306 (that is, in the loss districts) so that the energy that obtains to add from the tail end of inversion layer 308 between 306 edges.Utilize enough additional-energies, the free carrier in the loss district causes ionization by collision, and produces additional free carrier (electron-hole pair 320).
These additional free carriers 320 are scanned out the loss district by high electric field.The free hole of some generations flows to P type base region as majority carrier, creates a base current Isub, and it has increased Vds, as shown in Figure 4.Some free electrons are swept to N type drain region as majority carrier and be added on the drain current Ids.These two kinds of carrier flow as the drain electrode and base terminal in total current an additional components Isub and occur.
The experiment expression formula of ionization by collision base current Isub is provided by following formula:
Isub＝K1(Vds?B?Vdssat)*Id*(exp[-[K2/(Vds-Vdssat)]])
At this, K1 and K2 are the relevant parameter of process and the numerical value of Vdssat is a drain characteristics when entering saturation region Vds.Under normal operating condition, MOS equipment has zero-base electrode current (leakage current that has only reverse bias base stage drain loss district) substantially, as shown in Figure 4.This effect is not too remarkable in PMOS equipment usually, because the hole than Hypomobility is effective in creating hole-duplet not as good as higher ambulant electronics in the loss district.
This expression formula is differentiated with respect to drain voltage, from the small-signal shunt conductance (g of the base stage that drains
Db) be given:
g
db＝K2[I
SUB]/(Vds-Vdssat)A^2
Expression formula with the front replaces I
SUBAnd rearranging the factor produces:
g
db＝K2?K1(Vds-Vdssat)
-1(exp[-[K2/(Vds-Vdssat)]]
Fig. 2 has shown the g of a typical N MOS transistor
DbWith its r reciprocal
DbCurve.r
DbBe the drain output resistance of main body of the base current that is equivalent to, its will with normal transistor output resistance r
0Combination in parallel.Be that a typical N MOS transistor calculates r
Db, K1=5V^-1 and K2=30V and draw it and the Vds-Vdssat curve of the drain source voltage of standard.And, drafting be the output conductance that equates, g
Db, it is r
DbInverse.The extreme nonlinear characteristic of Isub makes r
DbAnd r
0Be combined as around the Vdssat and following initial r in the parallel connection of drain voltage place
0, because r
DbR than standard
0Big many orders of magnitude.
, much higher unlike several times of numerical value Vdssat in instantaneous drain source voltage, transistorized output impedance can be fully by r
DbDecision.This is how change instantaneous or accumulation can influence device characteristics in the hot electron that causes of base current an amplitude and/or a variational example.This influence can limit and make sometimes the possibility failure that reaches or keep the executive circuit function of expectation.
Because the instantaneous drain source voltage of transistor changes during operation, the instantaneous value of base current also changes the variation that causes the small-signal output conductance.According to the working point and the output voltage drift (between maximum required output voltage and minimum possible output voltage) of cascode amplifying circuit, base current Isub can change tempestuously.Isub can represent quite most value of total drain current when a value that is substantially zero is changed to when the approaching maximum required output voltage of instantaneous Vds or surpass a critical value when Vds is low and medium value.For great Isub initial (promptly, Vds=Vcrit), the critical value of Vds (Vds=Vcrit) depends on available mains voltage and the particular electrical circuit function and the coefficient of performance in issue (group), transistor technology, transistor dimensions (mainly being channel length) and biasing and signal level.The behavior of high non-linearity circuit may occur, and this depends on the level of output voltage.If it is suitable with the drain current or the normal drain current variation of expectation substantially that base current amplitude or electric current change amplitude, then it can have a negative impact to performance, circuit behavior and the reliability of circuit function.
This critical value Vcrit depends on the details of transistor arrangement, the amplitude of the instantaneous difference between drain electrode, grid, source electrode and base voltage and drain current.The amplitude of base current is a high non-linearity function of voltage difference and electric current, and can be with the size variation of the order of magnitude when instantaneous terminal voltage minor alteration.In case Vds is near the Vcrit of specific transistor technology, geometry and circuit voltage condition, then base current is had the greatest impact by drain source voltage Vds.
The performance of a circuit may be influenced by complete non-linear Isub behavior mainly in two ways.The first, I
SUBBasic change may the restricting circuits performance one or more selectivity characteristics (postpone switching time for bias current, switching voltage threshold value, gain, distortion, noise or the like).I
SUBA moment with a high Vds voltage exceeding critical value Vcrit increase and cause that an electric device parameter causes a unacceptable instantaneous variation from its nominal design level.The accumulated change of the second, one device electrical parameters or drift for example, may influence circuit performance such as the parameter of threshold voltage, mutual conductance, leakage current or the like.The skew that device parameter is enough big may cause that of Mean Time Between Failures of a given type circuit must reduce, and promptly reduces reliability.
A kind of circuit, has an equipment, this equipment have basically with gate-to-source control independent from voltage, along with the minor variations of signal voltage or output-voltage levels fast-changing one or more electrical quantity, this circuit also may represent unacceptable variation in the circuit performance, for example, non-linear gain, distortion, impedance mismatching or the like.
The The Long-term Effect that occurs extra base current by the slow deterioration (the cervical orifice of uterus limit value leaks or the like for Vth, Gm) of device electrical parameters.The hot carrier of the known Isub of causing can cause the charge traps in the gate oxide, and it caused that along with the past of time threshold value, mutual conductance and the behavior of cervical orifice of uterus limit value change.Finally, because the deterioration of the extra caused device parameter of base current will reach a level, will no longer meet required specification and this cascode amplifying circuit will be out of order in this cascode amplifying circuit performance.
Known transistor characteristic of being come by base current worsens along with the bad circuit performance of can causing in the past of time changes.Described in the document and be used to calculate the transistor simulation and breadboardin technology of Isub the influence of circuit behavior.Known Isub and Vds pattern (for example, the Mar of the modification of describing elsewhere simulation and Sakurni simulation) and simulator (the known RELY simulator of Miao Shuing elsewhere) combine with the simulating scheme of part or repetition.
Referring to accompanying drawing 1, show the deterioration of the performance characteristics of attempting to reduce a simple amplifier output circuit that causes by base current and therefore a kind of prior art of improved circuit behavior.By a kind of simple earthing power supply, the amplifier circuit level that the single transistor output stage is formed is replaced by the tandem compound circuit arrangement 100 of two transistor M6A and M6.This tandem compound is commonly called a kind of cascode and connects, and M6A is high-end cascode transistor M6a, and transistor M6 is the power transistor of low side ground connection.High-end cascode transistor M6A is inserted between the drain electrode of power transistor of ground connection and the amplifier output (its output drain node be connected to amplifier output Vout and its source node be connected in the drain electrode of power transistor M6 of ground connection).
M6 is driven by input Vin, and M6A is connected on the reference voltage Vref its grid.The transistor M6 configuration section ground of connecting between output amplifier node Vout and M6 drain node has improved the deterioration of circuit gain Gc=Δ Vout/ Δ Vin, (a selected circuit function characteristic) and postponed the catastrophe failure of this functional characteristic of this specific analog circuit under a specific voltage pressure.Comprise Vref biasing public grid, output stage 100 is changed into cascode output and the maximum Vds voltage pressure on reduction transistor M6 between the peak output voltage drift episode with the buffer transistor M6A between the voltage output end Vout between the drain electrode 102 of the power supply output transistor M6 of ground connection.
Peak value base current Isub1 before substituting among the transistor M6 approximately is 10ma during output Vout place's crest voltage skew (4 volts).After alternative ground connection-grid cascode transistor M6A, the grid 104 of M6A is biased a fixed voltage V parameter ref.Select Vref be provided with M6A grid so that during the Vout peak excursion the maximum Vds by transistor M6 be limited (and therefore the peak I sub among the limit transistor M6).
When the drain source voltage of transistor M6 deducted the threshold voltage Vt of M6A near Vref, transistor M6A was biased so that transistor M6A begins to turn off (moving to the saturation region from triode region) and the auxiliary voltage that is provided by the source current Ido from power supply Vdd is provided.Therefore Vds will be restricted to a maximum, approximately be that Vref deducts Vt.Vref and M6A are restricted to Vdsmax to the Vds by transistor M6 so so that for 10 volts Vdd and 4 volts Vout of expectation, the peak value of transistor M6 base current (Isub1) is reduced for zero basically.Cascode connects makes transistor M6 and M6A share 4 volts peak.
Along with Isub1 is reduced to zero basically, therefore the gain G c of circuit is stabilized, and makes after 115 days simulation operations, does not contain 40% deterioration, and the skew of gain can be ignored substantially.This point makes some be reduced by the mis-behave that the gridistor M6A biasing of ground connection is produced, thus the peak value Vds of restricted passage transistor M6.
, cascode transistor M6A takies before the part of the voltage pressure that is absorbed fully by transistor M6 now.Though the Isub of M6A is lower than the value of front transistor M6, (4ma is than 10ma), it remains considerable.Because the working point of M6A is biased near the low value that is biased to the Vds of triode region in other words, so its impedance ratio transistor M6 is low and so it is to the not too many influence of the gain of circuit 100., high relatively Isub value is arranged still in M6A, then the detection above a stable circuit gain behind the long life is uncertain.
The cascode circuit of the adjustment of Miao Shuing can produce than common cascode circuit even higher gain in the literature.Referring to people's such as Bult United States Patent (USP) 5,039,954 and the United States Patent (USP) 5,748,040 of Leung, it is herein in conjunction with as a reference.How many their application is restricted to little voltage drift and is low to moderate medium output-voltage levels, because only just can obtain this high-gain at low drain source voltage place.Because their more high-gain obtains by high output impedance, so they are more vulnerable to the thermionic influence that base current causes.At higher output voltage place, that is, high Vds, gain is lowered to the rank that is similar to common cascode circuit.
In addition, be used for the common monitoring power supply electric current of LOCAL FEEDBACK of adjustment cascode circuit of front so that the holding circuit function., in the power supply loop, do not flow, therefore do not benefit from the influence of the cascode LOCAL FEEDBACK of adjustment from the extra base current in the thermoelectronic effect.
These of the circuit performance of base current (thermoelectronic effect) generation restriction and/or degradation critical circuit functional characteristic and inevitable its reliability of reduction and many other examples are known in integrated circuit fields.Along with the trend that reduces equipment work voltage along with the time is also continuing, forcing in the restriction of Performance And Reliability of using known circuit to provide the circuit function of usefulness increases.More the continuation of ordering about active electronic circuit dimension of the ever-increasing demand of fast-circuit performance reduces and to the susceptibility that must increase of the deterioration that caused by base current.
Existing provides circuit to improve so that circuit designers and manufacturer avoid huge and urgent needs of these restrictions.
Summary of the invention
MOS cascode amplifier circuit suffers the long-term or transient change (deterioration) of the performance characteristics that caused by extra base current.When the output voltage of MOS cascode amplifier circuit is maximum, during the peak excursion of drain source voltage is by the power transistor of ground connection, can in the earthing power supply transistor of the connection output transistor of cascode, produce these electric currents.The cascode amplifier circuit configuration of the present invention's improvement comprises a voltage limiting bias circuit configuration of extra transistor.When the maximum place of MOS cascode amplifier circuit output voltage at it, this biasing circuit configuration is connected a series voltage limiting device between the transistor drain node as MOS cascode amplifier circuit output node with the highest cascode.An embodiment of the MOS cascode amplifier circuit configuration of improvement is arranged to sensitive cascode transistor drain source voltage excursion peak is restricted to a numerical value that is lower than previously selected critical voltage Vcrit.Vcrit is defined as sensitive cascode transistor drain source voltage values, for it, by the peak value drain source voltage greater than Vcrit be offset caused instantaneous and/or the accumulation base current will immediately or cumulatively be reduced to a scope to transistorized sensitive electrical quantity, this scope will be reduced to one to amplifier performance characteristic (group) can assess degree.
The extra transistor of an embodiment of biasing circuit configuration is connected with the grid of setovering with fixed voltage separately by the link of the adjacent source drain node in inside as an order.An external drain node of link is connected to when on the output node of MOS cascode amplifier and an external source node of link is connected to uppermost cascode and connects on the transistor drain.Additional transistor size and fixed bias grid voltage are selected to the peak value drain source voltage offset-limited on the sensitive transistor under selected operating condition.
Voltage limit, the base current of this circuit invention minimizes, the embodiment of biasing circuit configuration expanded circuit performance, useful life significantly, perhaps reduces significantly because unnecessary circuit performance restriction that the electrical quantity varying effect of extra caused moment of base current or accumulation is caused in the single transistor by the excess pressure amplifying stage or the reliability that reduces.
By people such as Hsu disclosed ground connection source drain and output between insert the fixedly method of the prior art of grid bias transistor (the effective grounding grid of small-signal equivalence), the base current among the transistor M6 is reduced to enough useful life of how much expanding described circuit., now transistor M6A itself may experience a considerable base current total value at the crest voltage place, and it finally may be fully be reduced to its threshold voltage or shunt conductance and unacceptably changes this circuit performance.
This cascode biasing circuit configuration inventive embodiment has merged a first transistor chain, has at least one extra transistor, be connected in series between the drain electrode of the first transistor in a cascode output voltage terminal and the second cascode link in tandem, the power end connecting circuit ground connection of this second cascode transistor chains with it.Extra transistor in first chain (group) is located to be biased fixed voltage so that the transistorized maximum drain source voltage of two or more individualities in the second cascode transistor chains is passed through in restriction separately at gate terminal (group) separately.The maximum drain source voltage is restricted to the maximum separately of the critical voltage level (Vcrit) that is lower than separately, at critical voltage level place, separately base current (for example unacceptably changes a circuit performance characteristic in corresponding two or more single pipes, gain, output impedance, useful life or the like).In addition, embodiments of the invention are by the life-span of delay circuit, that is, prolong decide the time that circuit characteristic meets predeterminated level and improve reliability.
Description of drawings
Fig. 1 has illustrated a kind of cascode output circuit of prior art;
What Fig. 2 represented is the curve chart that is changed by the caused typical small-signal of base current output resistance of equal value;
Fig. 3 has described the cross-sectional view strength of nmos pass transistor of the origin of explanation base current and terminal;
Fig. 4 exemplarily represents the relation of the drain source voltage of typical standard base current and standard, represents its quick increase at a critical Vds level place;
Fig. 5 represents typical N-channel MOS device characteristics and corresponding work scope;
Fig. 6 has illustrated an a kind of as described in the present invention embodiment of a kind of transistor drain source voltage restriction biasing circuit configuration of cascode output circuit; With
Fig. 7 has shown an a kind of as described in the present invention alternative embodiment of drain source voltage restriction biasing circuit configuration of cascode current reflection circuit.
Embodiment
Two basic hypothesis mainly are to determine stabilizing circuit performance from the variation that is caused by extra base current (for example a group necessary condition { R}).First factor is to determine that those circuit function characteristics (gain, output resistance or the like) make needs stable.Second factor is to determine to allow which kind of degree change of circuit performance characteristic (group) of selecting or worsen to allow for MTBF.Summarize below and be used for these factors device related with the embodiment of the invention.
Circuit analysis technology, emulation mode and physical electronics characteristic effect be known in this area and quote as a reference herein and with usually known other of electronic applications technical staff with reference to representing.The use of these technology, method and knowledge is within the ability of the correlative technology field those of ordinary skill of physical electronics and electronic circuit theory and practice.
About Fig. 6, an embodiment of the stable invention of this performance is described to a n groove CMOS cascode output amplifier level 600.It is right that transistor N1 and N2 are connected as a cascode, and the N1 power supply is connected to an omnibus circuit earth terminal Vss.The grid of an input power supply signal Vin excitation N1, and that transistor N2 and the N1 power supply by separately and drain terminal are connected 602 places at a public drain electrode source electrode is combined.Performance requirement group { the upper and lower bound Vin-u that R} set up, a Vin-l that Vin has the specific operation by circuit 600 to require.
Additional transistor N4 and transistor N3 are coupled to the drain electrode of N3 according to the power supply of N4 the order of series connection source drain is connected.The power supply of N3 similarly is coupled to the drain electrode N2d of N2.N4 makes its drain coupled to output end vo ut.The current source Ido that provides from power power-supply terminal Vdd is provided output end vo ut.The grid of N3 receives a fixed bias voltage Vbias from the fixed bias power supply terminal.The grid of N4 is also by being coupled to the fixed voltage of setovering on the power power-supply terminal Vdd.
Embodiments of the invention 600 comprise an amplifier, for example, have the differential amplifier 604 of a positive sensing (non-return) input 606 and negative sensing (oppositely) input 608.In response to potential difference between non-inverting terminal 606 and the reverse terminal 608, output 610 provides the output voltage that just turning round.Output 610 is connected to the grid of N2.Non-return input 606 receives a fixed voltage reference Vref.Oppositely the input 608 public drain electrode source electrodes that are connected to N2 and N1 are connected 602.
Select Vref so that amplifier 604 bias transistor M6A so that under the selected operating condition of circuit 600, keep in the saturation region of transistor M6 at it, as described below.
{ particular group of R} generally includes a kind of like this demand: promptly, power power-supply Vdd can suppose that magnitude of voltage is up to maximum Vddmax in the fixed operation requirement of circuit 600.{ R} also can comprise other function and/or function circuit specification R1, R2-R (m) to the group that operation requires, for example, a least gain requires Gcmin＞R1, a maximum output voltage value Voutmax＜R2, a maximum input signal voltage level | Vin|＜R3, an average operation failure free time MTBF＞R4, a minimum output voltage drift Vout＞R5, or the like.
For the embodiment of stable performance biasing circuit of the present invention, { R} comprises that also drain source voltage V1 separately, the V2 of restricted passage cascode transistor N1 and N2 will be no more than maximum safety value V1max and V2max separately to the requirement group.
As an alternative, can place other restriction at extra transistor N3 and N4: drain source voltage V3 separately, the V4 by extra transistor N3 and N4 will be no more than maximum safety value V3max and V4max separately.
Sum up, select Vbias and Vref so that those transistors N1-N4 and amplifier 604 cooperations are to meet following constraints:
1. if output voltage V out is low (that is, near Vss), then N2, N3 and N4 are biased in (being the working point OP2 of Fig. 5) in their triode region separately, so they do not help circuit gain (Δ Vout/ Δ Vin) significantly.
2. simultaneously, when output voltage V out is low (for example, at some Vout-min place, near Vss), transistor N1 is biased so that its in its saturation region (that is, the working point OP1 of figure), and its output impedance is that height and circuit 600 meet group { the gain requirement of R}.
3. in addition, Vref and Vbias are also selected so that work as output voltage V out rising (promptly, near Vdd) time, each drain source voltage V1, the V2 of the terminal of drain-source separately by transistor N1, N2 (and V3, V4 by N3, N4, if so force) in set of specifications { R} under not above separately maximum safety level V1-max, V2-max (and V3-max, V4-max).
4. select each safety level (extreme value) VI-max, V2-max, V3-max, V4-max so as to keep base current Isub1, Isub2, Isub3, Isub4 are lower than separately maximum level Isub1m, Isub2m, Isub3m, Isub4m.
Come artificial circuit 600 by using known integrated circuit die to fit the synthetic and analysis tool of known circuit, can obtain to realize the selection of each maximum base current level Isub1m that specific embodiment 600 of the present invention considered, Isub2m, Isub3m, Isub4m.The known analog and the instrument that are used for calculating the transistor AND gate circuit behavior that changes with base current about transistor output resistance (electricity is led) are illustrated people such as W.Hsu " using the reliable VLSI circuit design of analogue technique ", IEEE, the solid-state circuit periodical, in March, 1991, Vol.26, pp.452457, at this as a reference in conjunction with it.
The common practitioner in circuit design, analysis and synthetic field utilizes familiar standard method can obtain in the restrictive condition { { calculating of Vi} group of the voltage extremity of circuit 600 under the R}.Circuit analysis and synthetic method and technology are such as " circuit composition principle " (E.S.Kuh and D.O.Pederson, McGrawHill, New York, NY, 1959) and " Linear System Analysis " (D.K.Cheng, AddisonWesley publishes, Readingl MA, 1959) and so on standard university text in be illustrated.Brief says, transistor N1-N4 and amplifier 604 are indicated in the π type or the simulation of T type equivalent electric circuit of standard, has passive component { the P} circuit branch and active relevant signal generation unit { G} of each group.P} and the G} element interconnection and cause forming one group of multinomial net hole or the current circuit equation { { N}, it comprises Vss, Vdd, V1-V4 and Vin and Vout for M} or voltage node equation separately.Passive component P} and active element G} be according to the transistor of standard and amplifier analog parameter (for example, pi{We, Le, A,, tee{We, Le A}) functionally represent.
{ { the N} equation is answered by the normal linearity device so that be drain source voltage V1-V4 generation one group of expression formula { Vi} separately for M} or node in the net hole.With w=f (x, y, u, form v) represent Vi}, at this, w represents to have one of them of voltage V1-V4 of an extreme value Vimax; Variable x, y, u, v represent constraint biasing variable V ref, Vbias and other circuit specification (for example, Vddmax, Vin-min) or the circuit operation characteristic of circuit 600 (for example Gc).
In general, n bound variable x, y, u, v are that (u v)=0 retrains for x, y by m additional relationships Nm.Nm represents net hole equation { M} or the modal equation formula { constraint equation that finds the N} from circuit 600.
The criterion numeral of LaGrange multiplier learns a skill and can be used in restrictive condition { { extreme value of Vi} is searched the numerical value of Vbias and Vref according to the drain source voltage group under some conditions of S}.For example, this be illustrated in " mathematics of physics and engineering " (I.S.Sokolnikoff, and R.M.Redheffer, McGraw-Hill New York, NY, 1958, pg.254-257) in.
The effective electrical length Le of each transistor N1-N4 of selection Fig. 6 circuit structure and the yardstick of width W e are so that obtain by set of specifications { the selected required gain G c and the resistance value (that is output impedance Rout) of R} definition.The device of being familiar with by the integrated circuit (IC) design practitioner can carry out system of selection.Yardstick Le, We, as voltage Vdd-max, Vin-u, Vin-l and required constraint Vbias, the function of Vref, can be by { R} and transistor merge to determine with the knowledge of the electrical property change of base current the set of specifications of breadboardin.These are described in the above-cited list of references all and all are that this area circuit design practitioner is known.
By suitably selecting bias voltage Vref and Vbias with respect to the circuit operation conditions (for example, Vdd, maximum output voltage Voutmax, Vinu and Vinl) of regulation, then maximum required output voltage V out-max is extended to surpass a transistor.This selects the maximum Vds voltage by each transistor N1-N4 is reduced to just separately the maximum safety level of expectation from the Vout-max of total head, that is, and and V1-max, V2-max, V3-max, V4-max.
Alternately, can select bias level Vref, Vbias so that except the restriction of safe voltage level, transistor N1 can operate a little exceed saturated or be in saturated in so that with gain G c and output voltage drift (for example Δ Vout) maximization.
Still in of the present invention another replaced, can select Vref, Vbias so that except the restriction of safe voltage level, circuit performance also obtains a maximum output voltage Voutmax at the gain G c place of hanging down some than the accessible gain of maximum slightly.
The distribution that transistor N3 and N4 go up maximum voltage by or by directly be connected to power supply potential or indirectly by with power supply on for example being connected to a multi-multi-tap voltage divider (for example frequency divider of a resistance) the Low ESR op-amps excitation of carrying out reference of the fixed potential that obtains their gate bias is kept to fixed potential basically.Stable said method is summarized as the series of steps of general introduction below so that the parameter that the performance resistance of circuit 600 is caused by the additional drain source voltage extreme value by one or more transistor N1-N4 changes to be used for bias voltage Vref and Vbias.
Thereby the circuit that is used to Fig. 6 is selected bias voltage numerical value so that revolt the method for the variation stabilizing circuit performance characteristics that is caused by extra base current
Step 1: select one or more circuit function characteristics (group) { Cc}; Circuit gain Gc for example, output impedance r0 and maximum instantaneous and/or changing value in useful life (group), { Ac} is as the set of specifications { first of R}.
Step 2: select one or more external circuit voltage limit; That is, external circuit restrictive condition group vX}, for example: VINmin/max, VDDmin/max, VOUTmin/max, Δ VOUTmax.As the set of specifications { second portion of R}.
Step 3: carry out the biasing of initialization point and analyze so that be grid N3--N (i),--N (n) selects initial fixation offset gate magnitude of voltage { Vi}.Select the initial fixation gate voltage values Vi} in case selected transistor Nn} operates in separately initial saturated, transistor N1 is that triode working point OP1, transistor N2, N3, CNn are OP2n).
Attention: for an extra transistor N3, i=1 and Vi}=(Vref), for two extra transistor N3, N4, i=2 and for example { Vi}=Vref, Vbias.
Step 4: { { Vi} carries out electronic circuit analysis and synthetic under given restrictive condition for Nn}, biasing to utilize 600 selected circuit transistors.Attention: if desired, carry out electronic circuit analysis and synthetic so that { Nn} transistor N1, N2--Nn select transistor width and length, and { Wn, Ln} is with up to specification group of { Cc}, (for example Gc and r0) for selected.
Step 5: utilize the known simulation tool and method from step 3 on circuit 600 executive circuit analysis and emulation so that calculate initial, instantaneous and endurance life characteristic.
5A: { Nn} calculates the base current { Isubn} of (useful life) expection of worst case instantaneous peak value and accumulation for transistor.
5B: confirm the transistor { series connection of the transistor voltage extreme value of Nn} and equal maximum output voltage: ∑ Vn max=VOUTmax.
5C: { Nn} calculates worst case instantaneous peak value voltage extremity { Vn max} for transistor.
5C: for transistor { Nn} counting circuit performance characteristics (group) { initial, the worst case instantaneous peak value of Δ c} and the electrical quantity of accumulation changes and the variation (group) of worst case instantaneous peak value and accumulation.
Step 7: test 1: because base current produces caused counting circuit performance characteristics and changes (group) { Δ c} is in the restriction that retrains { within the Δ Ac}? if, forward end to, if not, forward next step to.
Step 8: test 2: with respect to other n-i source drain transistor drain source voltage extreme value { numerical value of vds (n-i) max} that is connected in series, does extra base current in the transistor (i) that is caused by the maximum of drain source voltage extreme value Vds (i) max produce the especially variation that (Isub (i)) causes the worst case instantaneous peak value that calculates and summation circuit performance characteristics to change (group)? in other words, at transistor N1 and transistor N2, N3-Ni--Nn have drain source voltage Vds (i) thus unbalanced can the redistributing of distribution by transistor { total Voutmax of Nn}?
If test 2 for being, then jump over next step, if not, carry out next step.Step 9: the circuit structure of circuit 600 changed into comprise that one is connected transistor N (i+1) with the additional drain-source of N3 (and/or N4) series connection between the drain electrode of Vout and N2, and increase an additional fastening bias voltage Vb (i+1), be connected to the grid of this extra transistor N (i+1).
Test 3: if number of iterations (i) is too big, (for example the extra transistor number does not then have solution for selected circuit performance restrictive condition group greater than the tolerable degree) forwards end so to, otherwise, forward step 10 to.
Step 10: redistribute the drain source voltage extreme value V ' and (n) max} in case each extra voltage extreme value V (i) max by transistor (i) be reduced to V ' (i) max (and reduce it corresponding extra peak value base current Isub (i) max}), and distribution is by be connected in series (i) max of balance Voutmax-V ' of transistor N (n-i) of residue.
Step 11: calculate set of specifications R} and the drain source voltage extreme value of redistributing that in step 10, finds v ' (n) new fixed bias voltage group { vbi} under the restrictive condition of max}, for example (Vref, Vbias,---), the method of LAGRANGE multiplier (for example, by).Forward step 3 to.A kind of replacement circuit embodiment of the present invention
With reference to figure 7, in a current reflection circuit 700, an alternative embodiment of the present invention has been shown.Circuit 700 is a cascode current reflection, and it can be used a high impedance output stage as a high-gain amplifier level, for example circuit among Fig. 6.
A signal source electric current I s, an input terminal 701 of (for example, the output Vout of Fig. 6) exciting current reflection.An output end vo ut1 of another one current source Io drive current reflection.Is and Io stem from power power-supply terminal Vdd.
In other embodiment of the present invention, in current reflection circuit 700, the auxiliary voltage of sharing source-drain electrode connection serial transistor 702,704 is arranged among the input series connection current path L1.Series current path L1 extends to the drain terminal 705 and the low side cascode transistor 712 to Vss (ground connection) of continuation by being connected in series of high-end cascode transistor 710 by the transistor 702,704 that is connected in series from input terminal 701.High side transistor 710 and low side transistor 712 are sentenced separately source electrode and drain terminal and combination a common junction 709.
The auxiliary voltage of sharing source-drain electrode connection serial transistor 706,708 simultaneously is arranged among the output series current path L2.Series current path L2 extends to the drain terminal 707 and the low side cascode transistor 716 to Vss (ground connection) of continuation by being connected in series of high-end cascode transistor 714 by the transistor 706,708 that is connected in series from output end vo ut1.High side transistor 714 and low side transistor 716 are sentenced separately source electrode and drain terminal and combination a common junction 711.
Voltage source 722,724,726,728 biasings that are fixed respectively of transistor 702,704 and 706,708 respective gates.Transistor 710,714 grids are to be encouraged by the supplement (-) of a dual op-amp 740 and actual (+) output 730,734.Reverse, the non-return input 742,744 of op-amp 740 correspondences is connected to common junction 709,711 respectively.
Current reflection circuit 700 recently provides high output impedance and current gain by the size of transistor 716 and 712, as known.
Suppose Qc[J] be meant that one group of four source drain connects cascode transistor, (two transistor chains that are connected in series) [710,712] and [714,716].
Suppose Qa[K] be meant that one group of additional drain-source connects transistor, (two transistor attachment links that are connected in series) [702,704] and [706,708].For 1＜j＜2, transistor Qc[j] be from link Qc[J1] the first tandem paths L1 that connects of a high-end drain terminal 705 to Vss cascode (link) transistor Qc[J1].For 3＜j＜4, transistor Qc[j] be from link Qc[J2] the second tandem paths L2 that connects of a high-end drain terminal 707 to Vss cascode (link) transistor Qc[J2].In addition, suppose that separately bias voltage 722,724,726 and 728 is by corresponding to Qa[K] additional serial transistor 702,704,706 and 708 Vb[K] represent.
For 1＜k＜2, transistor Qa[K] be to be connected to the first cascode link Qc[J1 from input node 701] the tandem paths L1 of high-end drain terminal 705 additional drain-source (link) transistor Qa[K1 that is connected in series].Similarly, for 3＜k＜4, transistor Qa[k] be to be connected to cascode link Qc[J2 from output node Vouti] the tandem paths L2 of high-end drain terminal 707 additional drain-source (link) transistor Qa[K2 that is connected in series].
By drain source voltage pressure Vds[j separately] cause at link Qc[J1] and Qc[J2] in each transistor Qc[j] the limiting value of extra base current can be represented as transistor Qc[j] separately maximum can allow base current Isubmax (j), caused by corresponding drain electrode source voltage Vds (j)=Vdsmax (j).
For the gain of stabilizing circuit 700 prevent since the caused especially base current of electric voltage over press on the cascode transistor 712,710 and 714,714 (promptly, Vds (j)＞Vdsmax (j)) deterioration that causes, bias stabilization extra transistor Q[k], transistor 702,704 and 706,708 for example, by separately voltage bias source Vb (k) for example 722,724 and 726,728 carry out the selectivity biasing in case restriction cascode transistor voltage Vds (j) separately (promptly, 774,776,786,788) be no more than separately maximum Vdsmax (j).
The maximum voltage that passes through each cascode transistor QcW (Vds (j)=Vdsmax (j)) that occurs is depended on the operating condition that circuit 700 is operated.For one given group { the selected performance characteristics of R} (for example gain and output impedance) and the selected operating characteristic [the height limit (Ismax of input signal for example, Ismin), selected maximum electric supply voltage restriction VDDmax and selected maximum output voltage level Voutmax and maximum output voltage drift (dynamic range, Voutmax-Voutmin)], select bias voltage Vb (k) so that the drain source voltage Vds (j) of restriction cascode transistor Qc (j) is lower than maximum Vds (j) max separately, thus the selected circuit performance characteristic of stable selected operating characteristic.
In general; in a current path by the transistor that is connected in series (for example L1 or L2) of connection between current source (for example node 701 and/or Vout1) and ground connection (for example Vss); for at the link (L1 that is connected between an intermediate drain node (for example node 705 or 707) and the earth; L2) cascode part (for example Qc[J] in drain-source connect cascode transistor (Qc[J]); be no more than selected limiting value (for example Isub (j) max) in order to ensure base current Isub (j), be coupling in the link (L1 or L2) between intermediate drain node (for example node 705 or 707) and the current source separately (for example Io or Is) insertion portion (for example Qa[k] in each grid of corresponding extra transistor (for example Qa[k]) be connected to separately bias voltage (for example Vb[k]) and select this bias voltage so that limit transistor Qc[J] go up each maximum drain source voltage skew (for example Vds (j) max) and be no more than a corresponding maximum (for example Vdsmax (j)).
In addition, when output voltage V out1 when maximum output voltage Vout1max floats to minimum output voltage Vout1min, the transistor 702,704 of the bias stabilization that the voltage that is connected in series is shared and 706,708 can be by separately bias source 722,724 and 726,728 biasings so that operate their saturation regions separately from their triode region separately.
Therefore, thereby circuit 700 is stabilized at one and keeps high output impedance on the output voltage dynamic range widely, and a high gain characteristics, eliminate simultaneously or reducing to minimum because caused gain of extra base current that electric voltage over press produces or output impedance worsen.
Each bias source 722,724 and 726,728 actual bias voltage numerical value depend on the concrete numerical value of Vdd max, Voutmin, Voutmax, Ismin and Ismax and each specific transistor width (We (i)), length (Le (i)) and the length-width ratio considered (We (i)/Le (i) is at this (i) expression transistor Q (j) and Qa (k).The solution of each bias source 722,724 and 726,728 bias voltage numerical value Vb (k) becomes a breadboardin and transistor sunykatuib analysis problem then, shown in for example above-mentioned list of references.
Be used to solve this type of conditionally the solution of restricted problem be known.For example, utilize the linear circuit simulation of known transistor Qc (j) and Qa (k), circuit 700 can be represented as a linear circuit curve chart or sketch (not shown).Can write down and find the solution one group of loop or modal equation formula (not shown) so that determine each node voltage and the loop current of circuit 700 linear circuit figure by matrix method.From merging selected operation and performance boundary value, this group loop and modal equation formula can obtain the relevant polynomial equation formula of a corresponding group.Known mathematical technology such as LaGrange multinomial method is used Vb (k) bias voltage that can be used for determining the expectation group, is used to obtain the selected operation and the performance characteristics of circuit 700.
Suitably select the bias Vb (k) of each bias source 722,724 and 726,728 thus guarantee that the selected characteristic of current reflection circuit 700 (gain, output resistance) is stabilized on the operating power voltage and incoming signal level of expection so that the restriction base current is lower than additional limits.
Concerning the technical staff of design of electronic circuits and simulation obviously; by using, just can not protect not the drain influence of source voltage of accusative of two cascode transistors 710 and 712 or 714 and 716 outward in the technology shown in the stable invention of this circuit characteristic.Connect transistor Qa (k) and pass through suitably to select bias voltage Vb (k) by the series connection drain-source that in a current path L1 or L2, suitably increases more than two; other transistors, more clearly saying so connects also can protected not accusative the drain influence of source voltage Vds (k) of the transistor selected in transistor Qa (k) group outward from additional drain-source.
Though handle thermoelectronic effect, the invention of stable performance cascode circuit of having described reduction for single groove n channel CMOS, but clearly, by the appropriate change that voltage polarizing and electric current flow, use by the transistor of single groove P raceway groove or double flute CMOS processing structure and also can realize this base current bias stabilization circuit inventive embodiment.
Claims (20)
1. a cascode circuit comprises:
The first transistor has separately source electrode, drain electrode and gate terminal, and described the first transistor gate terminal is coupled to reference on the input signal of first power power-supply and described the first transistor source terminal is coupled to described first power power-supply;
Transistor seconds has separately source electrode, drain electrode and gate terminal;
Described transistor seconds source terminal is connected so that form first source drain with described the first transistor drain terminal coupling;
The first cascode circuit output is coupled to the second electrical power supply voltage;
First circuit arrangement, be used for respect to described first power power-supply setover described transistor seconds grid circuit terminal so so that described the first transistor operate in the operate in saturation scope; With
A voltage limiting circuit is inserted in and is used for first drain source voltage separately of the described the first transistor of restricted passage and second drain source voltage separately by described transistor seconds between the drain electrode of described first output and described transistor seconds so that be no more than the corresponding first maximum drain source voltage limiting value and the corresponding second maximum drain source voltage limiting value.
2. cascode circuit as claimed in claim 1, wherein, described voltage limiting circuit comprises:
At least one extra transistor, have separately source electrode, drain electrode and gate terminal, the described drain electrode of described at least one extra transistor is coupled to described output, and the described grid that the described source electrode of described at least one extra transistor is coupled to the described drain electrode of described transistor seconds and described at least one extra transistor is coupled on a kind of voltage of selected basic fixed.
3. cascode circuit as claimed in claim 2, wherein:
Select the voltage of described selected basic fixed so that limit described the first transistor drain source voltage and described transistor seconds drain source voltage is no more than described maximum drain source voltage limiting value separately.
4. cascode circuit as claimed in claim 2, wherein, the voltage of described selected basic fixed is the described second power power-supply terminal.
5. cascode circuit as claimed in claim 1, wherein, described voltage limiting circuit comprises:
First extra transistor has separately source electrode, drain electrode and gate terminal;
Second extra transistor has separately source electrode, drain electrode and gate terminal;
The described second extra transistor drain terminal is coupled to described output;
The described second extra transistor source terminal is coupled to the described first extra transistor drain terminal;
The described first extra transistor source terminal is coupled to the described first extra transistor drain terminal;
The described first extra transistor grid is suitable for being coupled on the first selected basic fixed voltage; With
The described second extra transistor grid is suitable for being coupled on the second selected basic fixed voltage.
6. cascode circuit as claimed in claim 5, wherein:
Select described first basic fixed voltage and the described second basic fixed voltage so that described the first transistor drain source voltage and described transistor seconds drain source voltage are no more than described maximum drain source voltage values separately.
7. cascode circuit as claimed in claim 6, wherein, one of them is suitable for being coupled to described second source terminal described first and second selected basic fixed voltages.
8. cascode circuit as claimed in claim 1, wherein, described voltage limiting circuit comprises:
A plurality of independent extra transistor, each all has separately source electrode, drain electrode and gate terminal, and described a plurality of independent extra transistor are inserted in during series connection source drain between described output and the transistor seconds drain terminal connects; With
Described a plurality of each grid separately of independent extra transistor is suitable for being coupled to a corresponding basic fixed voltage source, and each of corresponding fixed voltage is selected to cooperate with described voltage limiting circuit,
Therefore described the first transistor drain source voltage and described transistor seconds drain source voltage do not surpass described first and the described second maximum drain source voltage limiting value separately.
9. cascode circuit as claimed in claim 1, wherein:
By selecting described the first transistor, described transistor seconds, described coupling, described first circuit arrangement that is used to setover, described first drain source voltage and described second drain source voltage to make circuit performance characteristic of described cascode circuit definition to described second source electrode.
10. cascode circuit as claimed in claim 9, wherein, described described first and second transistors of the maximum drain source voltage value defined separately first and second maximum base current values separately.
11. cascode circuit as claimed in claim 10, wherein, a performance characteristics limiting value of the described circuit performance characteristic of described maximum base current value defined.
12. cascode circuit as claimed in claim 9 wherein, is selected described performance characteristics from comprise circuit gain, output resistance and the group of circuit mean free error time.
13. cascode circuit as claimed in claim 9, wherein, described performance characteristics limiting value is defined by described maximum drain source voltage values.
14. cascode circuit as claimed in claim 13, wherein, described voltage limiting circuit comprises:
At least one extra transistor, have separately source electrode, drain electrode and gate terminal, the described drain electrode of described at least one extra transistor is coupled to described output, the described grid that the described source electrode of described at least one extra transistor is coupled to the described drain electrode of described transistor seconds and described at least one extra transistor is coupled on a kind of voltage of selected basic fixed, described selected basic fixed voltage cooperates with described circuit
Therefore described circuit performance characteristic represents described performance characteristics limiting value.
15. cascode circuit as claimed in claim 14, wherein, described selected basic fixed voltage is described second source terminal.
16. cascode circuit as claimed in claim 14, wherein, described voltage limiting circuit comprises:
First and second extra transistor that drain-source is connected in series, have separately source electrode, drain electrode and gate terminal, described drain-source series connection is connected on first and second extra transistor that are inserted between described output and the described transistor seconds drain terminal;
The first selected basic fixed voltage is coupled to the described first additional transistor gate;
The second selected basic fixed voltage is coupled to the described second additional transistor gate; With
Select described first selected basic fixed voltage and the described second selected basic fixed voltage so so that described cascode circuit represents described performance characteristics limiting value.
17. cascode circuit as claimed in claim 16, wherein, described second source terminal is in the described selected first and second basic fixed voltages.
18. cascode circuit as claimed in claim 16 comprises:
For described transistorized middle corresponding selected long Le and wide We, described selected long Le and wide We are selected to cooperate so that set up a limiting value separately of corresponding circuit working characteristic with described voltage limiting circuit, said separately limiting value and corresponding circuit working characteristic comprise following at least one:
The maximum limit of described second source voltage;
The high-end input voltage limiting value of described input signal;
The low side input voltage limiting value of described input signal;
The high-end output voltage limiting value of described output;
The low side output voltage limiting value of described output;
The bias voltage limiting value of described bias voltage; With
The reference voltage limiting value of described reference voltage.
19. cascode circuit as claimed in claim 16, wherein, described cascode circuit operates in the voltage power supply limit of selecting from maximum cascode output voltage, minimum cascode circuit output voltage, maximum input terminal voltage and maximum input terminal voltage group.
20. cascode circuit as claimed in claim 1 wherein, is used for comprising with respect to setover described first circuit arrangement of described transistor seconds gate terminal of described first power power-supply:
A differential amplifier comprises:
An oppositely input is coupled to described first source drain and is connected;
A non-return input is coupled on the basic fixed reference voltage; With
An amplifier out, in response to a voltage difference between described reverse input and the described non-return input, wherein, described amplifier out is coupled to the described grid of described transistor seconds.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US09/545,321 | 2000-04-06 | ||
| US09/545,321 US6342816B1 (en) | 2000-04-06 | 2000-04-06 | Voltage limiting bias circuit for reduction of hot electron degradation effects in MOS cascode circuits |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1366732A true CN1366732A (en) | 2002-08-28 |
| CN1227808C CN1227808C (en) | 2005-11-16 |
Family
ID=24175754
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN01800836.4A Expired - Fee Related CN1227808C (en) | 2000-04-06 | 2001-04-05 | Voltage limiting bias circuit for reduction of hot electron degradation effects in MOS cascode circuits |
Country Status (10)
| Country | Link |
|---|---|
| US (1) | US6342816B1 (en) |
| EP (1) | EP1195004B1 (en) |
| JP (1) | JP2003532321A (en) |
| CN (1) | CN1227808C (en) |
| AT (1) | ATE278264T1 (en) |
| AU (1) | AU2001249919A1 (en) |
| CA (1) | CA2375073A1 (en) |
| DE (1) | DE60105932T2 (en) |
| IL (1) | IL146900A0 (en) |
| WO (1) | WO2001082470A2 (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101478294B (en) * | 2008-01-03 | 2011-12-28 | 三星电机株式会社 | System and method for cascode switch power amplifier |
| CN106783868A (en) * | 2017-02-16 | 2017-05-31 | 杰华特微电子（张家港）有限公司 | Single programmable read-only storage based on CMOS technology |
| CN107431463A (en) * | 2015-02-15 | 2017-12-01 | 天工方案公司 | The power amplifier of staggeredly cascode layout with the heat resistance for enhancing |
| CN109800489A (en) * | 2019-01-02 | 2019-05-24 | 广东工业大学 | A kind of stacking transistor npn npn optimization gate bias setting method based on model emulation |
| CN111628738A (en) * | 2020-05-20 | 2020-09-04 | 电子科技大学 | V-waveband CMOS power amplifier |
| WO2023168820A1 (en) * | 2022-03-11 | 2023-09-14 | 长鑫存储技术有限公司 | Bias signal generation circuit and clock input circuit |
Families Citing this family (21)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6545538B1 (en) * | 2000-10-03 | 2003-04-08 | Texas Instruments Incorporated | Rail-to-rail class AB output stage for operational amplifier with wide supply range |
| US6487701B1 (en) * | 2000-11-13 | 2002-11-26 | International Business Machines Corporation | System and method for AC performance tuning by thereshold voltage shifting in tubbed semiconductor technology |
| US7551024B2 (en) * | 2001-03-13 | 2009-06-23 | Marvell World Trade Ltd. | Nested transimpedance amplifier |
| JP3820172B2 (en) * | 2002-03-26 | 2006-09-13 | 松下電器産業株式会社 | Semiconductor device lifetime estimation method and reliability simulation method |
| US7190230B1 (en) * | 2002-09-11 | 2007-03-13 | Marvell International Ltd. | Method and apparatus for an LNA with high linearity and improved gain control |
| US7253690B1 (en) * | 2002-09-11 | 2007-08-07 | Marvell International, Ltd. | Method and apparatus for an LNA with high linearity and improved gain control |
| US6977553B1 (en) | 2002-09-11 | 2005-12-20 | Marvell International Ltd. | Method and apparatus for an LNA with high linearity and improved gain control |
| SE528052C2 (en) * | 2004-02-05 | 2006-08-22 | Infineon Technologies Ag | Radio frequency power amplifier with cascaded MOS transistors |
| US7312662B1 (en) | 2005-08-09 | 2007-12-25 | Marvell International Ltd. | Cascode gain boosting system and method for a transmitter |
| JP2008005160A (en) * | 2006-06-21 | 2008-01-10 | Sharp Corp | Cascode-connected amplifier circuit, semiconductor integrated circuit using the same, and receiving device |
| CN101304240B (en) * | 2007-05-09 | 2010-07-14 | 瑞鼎科技股份有限公司 | Voltage limiting apparatus as well as operation amplifier applying the same and circuit design method thereof |
| US7859243B2 (en) * | 2007-05-17 | 2010-12-28 | National Semiconductor Corporation | Enhanced cascode performance by reduced impact ionization |
| KR102076135B1 (en) * | 2012-12-27 | 2020-02-11 | 에스케이하이닉스 주식회사 | Semiconductor device |
| US11128261B2 (en) | 2012-12-28 | 2021-09-21 | Psemi Corporation | Constant Vds1 bias control for stacked transistor configuration |
| US10243519B2 (en) * | 2012-12-28 | 2019-03-26 | Psemi Corporation | Bias control for stacked transistor configuration |
| US9287829B2 (en) | 2012-12-28 | 2016-03-15 | Peregrine Semiconductor Corporation | Control systems and methods for power amplifiers operating in envelope tracking mode |
| US9935585B2 (en) * | 2013-12-02 | 2018-04-03 | Qorvo Us, Inc. | RF amplifier operational in different power modes |
| WO2015117217A1 (en) * | 2014-02-06 | 2015-08-13 | Ghannouchi Fadhel M | High efficiency ultra-wideband amplifier |
| JP2017163197A (en) * | 2016-03-07 | 2017-09-14 | パナソニック株式会社 | Power amplifier circuit |
| CN106921349B (en) * | 2017-03-02 | 2020-10-09 | 中国电子科技集团公司第二十四研究所 | Amplifier based on inverter structure |
| US20230076801A1 (en) * | 2021-09-07 | 2023-03-09 | Cobham Advanced Electronic Solutions, Inc. | Bias circuit |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3986132A (en) * | 1975-10-22 | 1976-10-12 | Rca Corporation | Series energized transistor amplifier |
| IT1214249B (en) * | 1987-06-10 | 1990-01-10 | Sgs Microelettronica Spa | HIGH PERFORMANCE CMOS OPERATIONAL AMPLIFIER. |
| NL9000326A (en) * | 1989-05-08 | 1990-12-03 | Philips Nv | AMPLIFIER CIRCUIT. |
| US5504444A (en) * | 1994-01-24 | 1996-04-02 | Arithmos, Inc. | Driver circuits with extended voltage range |
| US6177838B1 (en) * | 1998-11-25 | 2001-01-23 | Pixart Technology, Inc. | CMOS gain boosting scheme using pole isolation technique |
-
2000
- 2000-04-06 US US09/545,321 patent/US6342816B1/en not_active Expired - Lifetime
-
2001
- 2001-04-05 WO PCT/US2001/011292 patent/WO2001082470A2/en active IP Right Grant
- 2001-04-05 AT AT01923205T patent/ATE278264T1/en not_active IP Right Cessation
- 2001-04-05 CA CA002375073A patent/CA2375073A1/en not_active Abandoned
- 2001-04-05 JP JP2001579442A patent/JP2003532321A/en active Pending
- 2001-04-05 CN CN01800836.4A patent/CN1227808C/en not_active Expired - Fee Related
- 2001-04-05 AU AU2001249919A patent/AU2001249919A1/en not_active Abandoned
- 2001-04-05 IL IL14690001A patent/IL146900A0/en unknown
- 2001-04-05 EP EP01923205A patent/EP1195004B1/en not_active Expired - Lifetime
- 2001-04-05 DE DE60105932T patent/DE60105932T2/en not_active Expired - Fee Related
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101478294B (en) * | 2008-01-03 | 2011-12-28 | 三星电机株式会社 | System and method for cascode switch power amplifier |
| CN107431463A (en) * | 2015-02-15 | 2017-12-01 | 天工方案公司 | The power amplifier of staggeredly cascode layout with the heat resistance for enhancing |
| CN107431463B (en) * | 2015-02-15 | 2021-02-02 | 天工方案公司 | Power amplifier with staggered cascode topology for enhanced thermal endurance |
| CN106783868A (en) * | 2017-02-16 | 2017-05-31 | 杰华特微电子（张家港）有限公司 | Single programmable read-only storage based on CMOS technology |
| CN109800489A (en) * | 2019-01-02 | 2019-05-24 | 广东工业大学 | A kind of stacking transistor npn npn optimization gate bias setting method based on model emulation |
| CN109800489B (en) * | 2019-01-02 | 2023-04-07 | 广东工业大学 | Stacked transistor optimized gate bias setting method based on model simulation |
| CN111628738A (en) * | 2020-05-20 | 2020-09-04 | 电子科技大学 | V-waveband CMOS power amplifier |
| CN111628738B (en) * | 2020-05-20 | 2023-07-11 | 电子科技大学 | V-band CMOS power amplifier |
| WO2023168820A1 (en) * | 2022-03-11 | 2023-09-14 | 长鑫存储技术有限公司 | Bias signal generation circuit and clock input circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2001082470A3 (en) | 2002-01-31 |
| DE60105932D1 (en) | 2004-11-04 |
| EP1195004A2 (en) | 2002-04-10 |
| IL146900A0 (en) | 2002-08-14 |
| DE60105932T2 (en) | 2005-10-06 |
| ATE278264T1 (en) | 2004-10-15 |
| CN1227808C (en) | 2005-11-16 |
| WO2001082470A2 (en) | 2001-11-01 |
| JP2003532321A (en) | 2003-10-28 |
| EP1195004B1 (en) | 2004-09-29 |
| CA2375073A1 (en) | 2001-11-01 |
| US6342816B1 (en) | 2002-01-29 |
| AU2001249919A1 (en) | 2001-11-07 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN1227808C (en) | Voltage limiting bias circuit for reduction of hot electron degradation effects in MOS cascode circuits | |
| Lehmann et al. | 1-V power supply CMOS cascode amplifier | |
| US7737790B1 (en) | Cascode amplifier and method for controlling current of cascode amplifier | |
| CN100543631C (en) | Constant voltage outputting circuit | |
| US8207789B2 (en) | Differential amplifier circuit | |
| CN1266838C (en) | Semiconductor integrated circuit device capable of generating stably constant current under low power voltage | |
| US20100148857A1 (en) | Methods and apparatus for low-voltage bias current and bias voltage generation | |
| CN109947172B (en) | Mirror current source circuit with low voltage drop and high output resistance | |
| CN200983116Y (en) | Standard circuit of MOS voltage | |
| JP2007188245A (en) | Reference voltage generating circuit and semiconductor integrated device | |
| CN109742946B (en) | DCR sampling circuit applied to wide output voltage range Buck converter | |
| JP5646360B2 (en) | Semiconductor device | |
| CN101236447A (en) | Voltage pre-regulating circuit for reference voltage source | |
| CN111384940A (en) | High-linearity wide-swing CMOS voltage follower | |
| CN107404291B (en) | Bias circuit and low noise amplifier | |
| JP7224387B2 (en) | amplifier circuit | |
| US20190214983A1 (en) | Clock voltage step-up circuit | |
| CN1167188C (en) | Amplifier | |
| CN107896096A (en) | Sampling hold circuit front-end wideband amplifier | |
| US8823446B2 (en) | Current mirror with immunity for the variation of threshold voltage and the generation method thereof | |
| KR101055788B1 (en) | A differential amplifier circuit having a wide bandwidth common mode input voltage range and an input buffer including the differential amplifier circuit | |
| KR101895210B1 (en) | Power amplifier | |
| CN219418048U (en) | Constant current drive circuit suitable for wide voltage output | |
| CN211089632U (en) | High-linearity wide-swing CMOS voltage follower | |
| US6987421B2 (en) | Common mode voltage generation at a differential output of an amplifier |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20051116 Termination date: 20140405 |