CN1365137A - Method for forming self aligning contact window structure on semiconductor substrate - Google Patents
Method for forming self aligning contact window structure on semiconductor substrate Download PDFInfo
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- CN1365137A CN1365137A CN 01100532 CN01100532A CN1365137A CN 1365137 A CN1365137 A CN 1365137A CN 01100532 CN01100532 CN 01100532 CN 01100532 A CN01100532 A CN 01100532A CN 1365137 A CN1365137 A CN 1365137A
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- F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
- F01—MACHINES OR ENGINES IN GENERAL; ENGINE PLANTS IN GENERAL; STEAM ENGINES
- F01L—CYCLICALLY OPERATING VALVES FOR MACHINES OR ENGINES
- F01L3/00—Lift-valve, i.e. cut-off apparatus with closure members having at least a component of their opening and closing motion perpendicular to the closing faces; Parts or accessories thereof
- F01L3/10—Connecting springs to valve members
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- F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
- F01—MACHINES OR ENGINES IN GENERAL; ENGINE PLANTS IN GENERAL; STEAM ENGINES
- F01L—CYCLICALLY OPERATING VALVES FOR MACHINES OR ENGINES
- F01L1/00—Valve-gear or valve arrangements, e.g. lift-valve gear
- F01L1/02—Valve drive
- F01L1/04—Valve drive by means of cams, camshafts, cam discs, eccentrics or the like
- F01L1/08—Shape of cams
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- F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
- F01—MACHINES OR ENGINES IN GENERAL; ENGINE PLANTS IN GENERAL; STEAM ENGINES
- F01L—CYCLICALLY OPERATING VALVES FOR MACHINES OR ENGINES
- F01L1/00—Valve-gear or valve arrangements, e.g. lift-valve gear
- F01L1/30—Valve-gear or valve arrangements, e.g. lift-valve gear characterised by the provision of positively opened and closed valves, i.e. desmodromic valves
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Abstract
The method of forming self aligning contact window structure on semiconductor substrate features that composite interval wall formed in the margin of grid structure and comprising one lower layer silicon nitride interval wall and one upper layer un-doped silicon interval wall. The un-doped silicon in the un-doped silicon interval wall can fill the possibel faults and pinhole in the lower layer silicon nitride interval wall so as to eliminate short circular and leakage caused by the direct contact between the conducting self aligning contact window structure and conducting grid area.
Description
The present invention relates to the manufacture method of semiconductor element, particularly a kind of method that is used between grid structure forming a contact structure of aiming at voluntarily with the conduction region that exposes the semiconductor-based end.
At present, just begun a long time ago by target with the semiconductor industry that increases device performance.Yet compared to the assembly that uses big live width size manufacturing, reduction semiconductor minimum feature size will produce less conductive region, and reduce parasitic hand capacity value, and have the lower capacitance-resistance value that makes performance depreciation (RC value).Can finish the assembly of reduced size through several semiconductor fabrication processes (such as photography of optics microcosmic and dry-etching).The use of the use of more complicated exposure camera and more responsive photoresist layer has allowed the live width less than 1/4th microns to realize in the photoresist layer.In addition, the exploitation of more advanced dry-etching equipment and manufacture method has allowed in the photoresist layer can be placed on the other materials that semiconductor device uses in making less than 1/4th microns live width.Yet except the progress of making scope, structural innovation has also allowed the live width less than 1/4th microns to be achieved.For example aiming at contact (opening and structure are formed between the grid structure of metal oxide semiconductor field effect transistor (MOSFET) device) has voluntarily allowed the interval between the grid structure to reduce.The contact window of the Dui Zhuning contact structure that allows fully to be settled is formed in the contact window of aiming at voluntarily voluntarily, and the bottom conductive region between the grid structure (be arranged at interval, the diameter that width is aimed at contact hole more voluntarily is little) contact.And do not forming under the situation of the contact window of aiming at voluntarily, then must between grid structure, use bigger conductive region, to guarantee that its superstructure is set fully.Finishing of the contact window of Dui Zhuning is to form a conductive region (such as the source/drain regions of MOSFET) in the narrow interval of grid structure voluntarily, then form the contact window of aiming at voluntarily (than being spaced apart greatly between the grid structure), thereby expose the conduction region between grid structure.Then, the contact structure of aiming at voluntarily (being formed in the contact window of aiming at voluntarily) that forms subsequently is arranged on the bottom conductive region fully.So novel method need not bigger zone, to guarantee the contact window of complete installing structure.Yet, for the idea that makes the contact of aiming at voluntarily can be successful, the insulation gap wall of free of pinholes phenomenon be must form at the edge of grid structure, leakage current and short circuit phenomenon produced between contact structures (be arranged in and aim at contact hole voluntarily) and the grid structure to avoid aiming at voluntarily.
For this reason, the present invention will disclose a kind of novel process for preparing that is used for forming at the grid structure edge compound clearance wall, wherein in the bottom assembly of compound clearance wall, defective that may occur or pin hole can be covered by the lower layer components of dielectric compound clearance wall, thereby avoid substrate (conductive region under the contact structure of Dui Zhuning voluntarily) that the risk of the contact structure aimed at voluntarily and gate short (causing by aiming at contact structure voluntarily) takes place.Such as United States Patent (USP) the 6th, 033, the known technology of No. 962 people such as () Jeng has illustrated a kind of method that forms the contact structure that is used for aiming at voluntarily of insulation gap wall on the grid structure edge, yet the method that is used to form compound clearance wall described in this known technology and undeclared the present invention, compound clearance wall are characterised in that the dielectric upper strata clearance wall assembly of the contact structure use of aiming at voluntarily.
Main purpose of the present invention is to propose a kind of method that forms the contact structure of aiming at voluntarily on the semiconductor-based end, makes the MOSFET device can be used for dynamic random access memory (DRAM) and static RAM (SRAM) unit.
Another object of the present invention is to propose a kind of method that forms the contact structure of aiming at voluntarily on the semiconductor-based end, particularly forms compound clearance wall on the grid structure edge of MOSFET device.
Another purpose of the present invention is to propose a kind of method that forms the contact structure of aiming at voluntarily on the semiconductor-based end, and formed compound clearance wall comprises a underlying silicon nitride and do not mix in upper strata or the silicon compound of amorphous phase.
A further object of the present invention is to propose a kind of method that forms the contact structure of aiming at voluntarily on the semiconductor-based end, form the contact structure of aiming at voluntarily of conduction in the contact window of aiming at voluntarily between grid structure, wherein the contact structure of aiming at voluntarily is connected with the not doping or the amorphous silicon clearance wall compound of compound clearance wall.
For realizing above-mentioned purpose, the invention provides a kind of method, the contact window that especially a kind of formation is aimed at voluntarily and method of aiming at contact structures voluntarily between the grid structure of MOSFET device that on the semiconductor-based end, forms the contact structure of aiming at voluntarily.It is characterized in that compound clearance wall is positioned at the grid structure edge, and comprise one and do not mix or upper amorphous silicon layer clearance wall compound.On the semiconductor-based end, form after light dope source electrode/drain region, then form the grid structure that is covered by silicon nitride.Deposit one silicon nitride layer and do not mix in upper strata or amorphous silicon layer after, utilize non-isotropy dry-etching process, on the grid structure edge that is covered by silicon nitride, form compound clearance wall.It is characterized in that do not mix in the upper strata or amorphous silicon clearance wall compound will be inserted defective or pin hole in the bottom nitride spacer compound.Follow after the grid structure that is not covered or formation heavy doping source electrode/drain region, the zone at the semiconductor-based end that compound clearance wall covered on the grid structure that is not covered silicon oxide deposition by silicon nitride by silicon nitride.Then in silicon oxide layer, form a contact window of aiming at voluntarily, wherein the contact window of aiming at voluntarily will expose a width, this width is positioned at the heavy doping source electrode/drain region between the grid structure that is covered by silicon nitride, and exposes the compound clearance wall that is positioned on the grid structure edge that is covered by silicon nitride.Then depositing conductive material as doped polycrystalline silicon, tungsten, and carries out cmp (CMP), thereby forms the contact structure of aiming at voluntarily in the contact window of aiming at voluntarily, or the contact plunger of aligning voluntarily of conduction.Wherein these contact structures of aiming at voluntarily will place on the heavy doping source electrode/drain region of bottom fully, and be connected with compound clearance wall on being positioned at the grid structure edge that is covered by silicon nitride.
To describe purpose of the present invention and other advantages in a preferred embodiment in detail with reference to the accompanying drawings, these accompanying drawings are:
Fig. 1～5 form the schematic diagram of the preferred embodiment of the method for the contact structure of aligning voluntarily for the present invention on the semiconductor-based end, form the main process of the contact structure of aiming at voluntarily in the contact window of aiming at voluntarily of explanation between grid structure, wherein grid structure comprises compound clearance wall, it is characterized in that a upper strata do not mix or the amorphous silicon clearance wall.
The present invention mainly is the method that forms the contact structure of aiming at voluntarily in the contact window of aiming at voluntarily between grid structure.Wherein grid structure comprises compound clearance wall, is characterised in that the upper strata clearance wall is by doping or amorphous silicon are formed.The present invention is the MOSFET element explanation with the N raceway groove, but also can be applicable to the MOSFET element of P raceway groove.Illustrated compound clearance wall can be applicable to all MOSFET elements among the present invention, such as the MOSFET device of the logic OR memory cell of DRAM, SRAM or other types.
Fig. 1 is a P type semiconductor substrate 1, the semiconductor-based end 1 of this P shape by have＜100〉crystallization direction monocrystalline silicon forms; At first form the isolated area 20 of filling with insulant, as shallow trench isolation (STI) or heat growth field oxide (FOX), the heat growth forms a gate oxide 2 in oxygen atmosphere, and its thickness is between 50 to 100 dusts.Then on gate oxide 2, form the grid structure 5 that a silicon nitride covers.This step can form a polysilicon layer or metal silicide layer 3 by means of low-pressure chemical vapor phase deposition (LPCVD), and as tungsten silicide, its thickness is between 1000 to 3000 dusts.Yet, if metal silicide layer 3 can be made up of lower floor's polysilicon and upper strata metal silicified layer; And polysilicon layer 3 can dynamically mix during deposit to silane ambient by adding arsenic or phosphorus, and perhaps deposit polysilicon layer 3 at first mixes by the implantation of arsenic or phosphonium ion then.After polysilicon layer or metal silicide layer 3 deposits, through low-pressure chemical vapor phase deposition or silicon nitride layer 4 of plasma enhanced CVD (PECVD) deposit, its thickness is between 300 to 1500 dusts.
Be etched mask with a photoresist (not shown) then, form the grid structure 5 that is covered by silicon nitride through non-isotropic active-ion-etch (RIE) method, wherein the non-isotropy active-ion-etch uses CF
4Or CHF
3As the etchant of silicon nitride layer 4, use CL
2Or SF
6Etchant as polysilicon layer or metal silicide layer 3.The width of the grid structure 5 that is covered by silicon nitride is between 0.15 to 0.20 micron, and this will cause after regions and source forms, and the channel length of grid structure 5 belows that covered by silicon nitride is lower than 0.10 micron.Remove the photoresist that is used for determining the grid structure 5 that covered by silicon nitride by the ashing of plasma oxygen and wet-cleaned; And the circulation of the buffered hydrofluoric acid by wet clean process, silicon dioxide gate insulating barrier 2 parts that the grid structure 5 that is not covered by silicon nitride is covered are removed.Then form lightly doped regions and source 30 (being used for element) such as the discrete cell of SRAM, in the zone at the semiconductor-based end 1 that is not covered by silicon nitride cover layer grid structure 5, be by the arsenic between energy about 30 to 70KeV or the implantation of phosphorus, implant dosage is at 1E13 to 1E14 atom/cm
2Between.
Below, illustrate on grid structure 5 edges that covered by silicon nitride to form clearance wall.Because a contact window of aiming at voluntarily is optionally being formed in the one silica layer of producing subsequently, expose from the regions and source of conductivity that will be between grid structure, so clearance wall must be formed by the material beyond the silica, with the selectivity of the contact window process guaranteeing to aim at voluntarily.As previously mentioned, known technology uses silicon nitride as spacer material, is formed in the silicon oxide layer between the grid structure that silicon nitride covers to allow a contact window of aiming at voluntarily, and key is the silicon nitride gap wall on the grid structure edge.Yet the contact structures that the conductivity that produces subsequently that is arranged in voluntarily the contact window of aiming at will be aimed at voluntarily such as defectives in silicon nitride gap wall such as pin holes contact with grid structure, thereby cause leakage current or the short circuit of undesirable grid to substrate.Therefore, the invention is characterized in a kind of compound clearance wall, this compound clearance wall is made up of a underlying silicon nitride layer and dielectric undoped polycrystalline silicon or upper amorphous silicon layer clearance wall.Therefore, if the pin hole phenomenon is present in the underlying silicon nitride clearance wall assembly really, then the undoped silicon of upper strata clearance wall will be as non-conductive material filling defect or pin hole, thereby reduces leakage current or the short risk of grid to substrate.Therefore, at first pass through low-pressure chemical vapor phase deposition or silicon nitride layer 6a of plasma enhanced CVD process deposit, the thickness of silicon nitride layer 6a is reached between about 50 to 500 dusts, then process low-pressure chemical vapor phase deposition undoped polycrystalline silicon of process deposit or amorphous silicon layer 7a reach the thickness between about 50 to 200 dusts, as shown in Figure 2.
Then carry out non-isotropic active-ion-etch, that is, use Cl
2Or SF
6As the etchant of undoped polycrystalline silicon or amorphous silicon layer 7a, use CF
4Or CHF
3As the etchant of silicon nitride layer 6a, produce the compound clearance wall that is positioned at the tectal grid structure of silicon nitride 5 edges.Compound clearance wall is made up of the undoped polycrystalline silicon on upper strata or the silicon nitride gap wall 6b of amorphous silicon clearance wall 7b and bottom.This situation schematically is illustrated among Fig. 3.Heavy doping source electrode/drain region 8 then is formed on the grid structure 5 that is not covered by silicon nitride, or is not placed in the zone at the semiconductor-based end 1 that the compound clearance wall on the grid structure 5 that is covered by silicon nitride covers.Heavy doping source electrode/drain region 8 is to form through implanting arsenic or phosphonium ion, and its energy is between about 40 to 80KeV, and dosage is at about 1E14 to 1E15 atom/cm
2Between, implant angle is between about 0 to 70 degree.Low implant angle is very important, can limit ion and can not damage the own of undoped polycrystalline silicon or amorphous silicon clearance wall 7b.
Then with low-pressure chemical vapor phase deposition or plasma enhanced CVD one silica layer 9, its thickness is about between 3000 to 12000 dusts, uses tetrem alkane silicomethane (TEOS) as the deposit source.Then carry out cmp (CMP), produce the silicon oxide layer 9 of flat surfaces.Use the photoresist (not shown) as etching mask, and use CHF
3As the etchant of silicon nitride, optionally in silicon oxide layer 9, form the contact window of aiming at voluntarily 10.With respect to the low etch-rate of undoped polycrystalline silicon or silicon nitride, the high etch speed of silica will optionally form the contact window of aiming at voluntarily 10.In that the interval between the tectal grid structure 5 (comprising compound clearance wall) is between 0.01 to 0.10 micron by silicon nitride, and the diameter of the contact window of aiming at voluntarily 10 is about between 0.01 to 0.1 micron.Then utilize oxygen ashing and formula to clean the photoresist of removing the mask that is used to form the contact window of aiming at voluntarily 10, as shown in Figure 4.
Then in the contact window of aiming at voluntarily 10, form the contact structures 11 of aiming at voluntarily that schematically illustrate among Fig. 5.Through conductive layer of low-pressure chemical vapor phase deposition process deposit such as tungsten, tungsten silicide or doped polycrystalline silicon, reach the thickness that is about between 1000 to 5000 dusts, thus contact window 10 complete filling that will aim at voluntarily.Then (use Cl through cmp or through active-ion-etch processing procedure optionally
2Or SF
6Etchant as conductive layer) removes the partially conductive layer from the top end surface of silicon oxide layer 9, thereby in the contact window of aiming at voluntarily 10, form the contact structures 11 of aiming at voluntarily.Aim at contact structures 11 voluntarily and place fully on heavy doping source electrode/drain region 8, and be connected with undoped polycrystalline silicon or non-crystalline silicon clearance wall assembly 7b.The contact structures 11 of aiming at voluntarily that to eliminate conductivity with the ability of defective among undoped polycrystalline silicon or filling of amorphous silicon silicon nitride or the seal clearance wall assembly 6b or pin hole are connected to the risk of the conductive region of the grid structure 5 that is covered by silicon nitride, thereby avoid short circuit or the leakage current of grid to substrate.
More than be not to limit the scope of the invention at being described in detail of carrying out of the preferred embodiments of the present invention, and for the common technique personnel of this area, can under the situation that does not break away from design of the present invention, carry out suitable and trickle change and adjustment, but these change and adjustment all is a further result of implementation of the present invention.
Claims (27)
1, a kind of method that on the semiconductor-based end, forms the contact structure of aiming at voluntarily, the step that said method comprises has:
On the bottom gate insulator of substrate, form a grid structure that is covered by silicon nitride;
Form the regions and source of light dope in the zone at the semiconductor-based end that is not covered by grid structure;
Edge at the grid structure that is covered by silicon nitride forms compound clearance wall, and wherein each compound clearance wall includes a underlying silicon nitride clearance wall and a upper strata undoped silicon clearance wall;
Be not formation heavy doping source electrode/drain region in the semiconductor basal region that grid structure and compound clearance wall covered that is covered by silicon nitride;
The deposit one silica layer;
In silicon oxide layer, form the contact window of aiming at voluntarily, wherein aim at the window that touches that connects voluntarily and expose heavy doping source electrode/drain region; And
In the contact window of aiming at voluntarily, form contact structures of aiming at voluntarily, wherein the contact structures of aiming at voluntarily will place on the heavy doping source electrode/drain region of bottom fully, and be connected with described compound clearance wall on being positioned at the grid structure edge that silicon nitride covers.
2, form the method for the contact structure of aiming at voluntarily at the semiconductor-based end as claimed in claim 1, it is characterized in that gate insulator is a silicon dioxide layer, silicon dioxide layer forms with hot growth pattern, and its thickness is between 50 to 100 dusts.
3, form the method for the contact structure of aiming at voluntarily at the semiconductor-based end as claimed in claim 1, it is characterized in that the grid structure that is covered by silicon nitride is made up of the doped polycrystalline silicon of thickness 1000 to 3000 dusts.
4, form the method for the contact structure of aiming at voluntarily at the semiconductor-based end as claimed in claim 1, it is characterized in that by the grid structure that silicon nitride covers it being to form by the multi-crystal silicification metal of thickness 1000 to 3000 dusts, wherein the multi-crystal silicification metal is made up of a upper strata metal silicide layer and a bottom doped polysilicon layer, and the metal silicified layer thing can be tungsten silicide.
5, form the method for the contact structure of aiming at voluntarily at the semiconductor-based end as claimed in claim 1, it is characterized in that covering silicon nitride layer is to form through low-pressure chemical vapor phase deposition or plasma enhanced chemical gas deposit a kind of mode wherein, and thickness is between 300 to 1500 dusts.
6, form the method for the contact structure of aiming at voluntarily at the semiconductor-based end as claimed in claim 1, it is characterized in that the channel length between the light dope regions and source is lower than 0.10 micron.
7, form the method for the contact structure of aiming at voluntarily at the semiconductor-based end as claimed in claim 1, the silicon nitride gap wall that it is characterized in that compound clearance wall is to form through low-pressure chemical vapor phase deposition or plasma enhanced CVD a kind of mode wherein, and thickness is between 50 to 500 dusts.
8, form the method for the contact structure of aiming at voluntarily at the semiconductor-based end as claimed in claim 1, it is characterized in that the undoped silicon clearance wall of compound clearance wall is formed through low-pressure chemical vapor phase deposition by undoped polycrystalline silicon, thickness is between 50 to 200 dusts.
9, form the method for the contact structure of aiming at voluntarily at the semiconductor-based end as claimed in claim 1, it is characterized in that the undoped silicon clearance wall of compound clearance wall is formed through low-pressure chemical vapor phase deposition by amorphous silicon, thickness is between 50 to 200 dusts.
10, form the method for the contact structure of aiming at voluntarily at the semiconductor-based end as claimed in claim 1, it is characterized in that compound clearance wall is to form through non-isotropy active-ion-etch process, wherein uses Cl
2Or SF
6As the etchant of undoped polycrystalline silicon, and use CF
4Or CHF
3Etchant as silicon nitride layer.
11, form the method for the contact structure of aiming at voluntarily at the semiconductor-based end as claimed in claim 1, it is characterized in that this heavy doping source electrode/drain region is to form through implanting arsenic or phosphonium ion, its energy is between 40 to 80KeV, and dosage is at 1E14 to 1E15 atom/cm
2Between, implant angle is between 0 to 7 degree.
12, form at the semiconductor-based end as claimed in claim 1.The method of the contact structure of Dui Zhuning voluntarily is characterized in that including interval between the grid structure arranged side by side that is covered by silicon nitride of compound clearance wall between 0.01 to 0.10 micron.
13, form the method for the contact structure of aiming at voluntarily at the semiconductor-based end as claimed in claim 1, it is characterized in that the diameter of aiming at contact hole voluntarily in silicon oxide layer is between 0.01 to 0.1 micron.
14, form the method for the contact structure of aiming at voluntarily at the semiconductor-based end as claimed in claim 1, it is characterized in that one of them is formed by doped polycrystalline silicon, tungsten silicide or tungsten for the contact structure aimed at voluntarily.
15, a kind of method that in the suprabasil silicon oxide layer of semiconductor, forms the contact window of aiming at voluntarily, wherein the contact window of aiming at voluntarily exposes, place the compound clearance wall on the grid structure edge that is covered by silicon nitride, and compound clearance wall wherein comprises a underlying silicon nitride clearance wall and a upper strata undoped silicon clearance wall, and the step that said method comprises has:
On the bottom layer silicon dioxide gate insulator, form a grid structure that is covered by silicon nitride;
In the semiconductor basal region that the grid structure that is not covered by silicon nitride covers, form the light dope regions and source;
The deposit silicon nitride layer;
The deposit undoped silicon layer;
Carry out the non-isotropy dry-etching, form described compound clearance wall on the grid structure edge that is covered by silicon nitride, wherein compound clearance wall comprises upper strata undoped silicon clearance wall and underlying silicon nitride clearance wall;
At the grid structure that is not covered by silicon nitride, or the semiconductor basal region that the compound clearance wall on the grid structure that is not covered by silicon nitride covers forms heavy doping source electrode/drain region;
The described silicon oxide layer of deposit;
With the silicon oxide layer planarization;
In silicon oxide layer, form the contact window of aiming at voluntarily, wherein expose the contact window of aiming at voluntarily at the grid structure place that is covered by silicon nitride, and comprise the heavy doping source electrode/drain region in the interval of compound clearance wall, and expose compound clearance wall;
Deposit one conductive layer fills up the contact window of aiming at voluntarily; And
Remove the partially conductive layer from the top end surface of this oxide layer, in the contact window of aiming at voluntarily, form a contact structure of aiming at voluntarily, wherein the contact structure of aiming at voluntarily will place on this part heavy doping source electrode/drain region between the grid structure that is covered by silicon nitride fully, and the contact hole of wherein aiming at voluntarily is connected with the compound clearance mural margin.
16, the method that forms the contact hole of aiming at voluntarily in the suprabasil silicon oxide layer of semiconductor as claimed in claim 15 is characterized in that the silicon dioxide gate insulating barrier forms with hot growth pattern, and its thickness is between 50 to 100 dusts.
17, the method for contact hole in the suprabasil silicon oxide layer of semiconductor aimed in formation as claimed in claim 15 voluntarily, it is characterized in that the grid structure of the grid structure that covered by silicon nitride is made up of the doped polycrystalline silicon of thickness 1000 to 3000 dusts.
18, the method for contact hole in the suprabasil silicon oxide layer of semiconductor aimed in formation as claimed in claim 15 voluntarily, it is characterized in that the light dope regions and source forms through implanting arsenic or phosphonium ion, its energy is between 30 to 70KeV, and dosage is at 1E13 to 1E14 atom/cm
2Between.
19, the method for contact hole in the suprabasil silicon oxide layer of semiconductor aimed in formation as claimed in claim 15 voluntarily, it is characterized in that the channel length between the light dope regions and source is lower than 0.10 micron.
20, the method for contact hole in the suprabasil silicon oxide layer of semiconductor aimed in formation as claimed in claim 15 voluntarily, the silicon nitride gap wall that it is characterized in that compound clearance wall is to form through low-pressure chemical vapor phase deposition or plasma enhanced CVD a kind of mode wherein, and its thickness is between 50 to 500 dusts.
21, the method for contact hole in the suprabasil silicon oxide layer of semiconductor aimed in formation as claimed in claim 15 voluntarily, the undoped silicon clearance wall that it is characterized in that compound clearance wall forms through low-pressure chemical vapor phase deposition, and its thickness is between 50 to 200 dust thickness.
22, the method for contact hole in the suprabasil silicon oxide layer of semiconductor aimed in formation as claimed in claim 15 voluntarily, the undoped silicon clearance wall that it is characterized in that compound clearance wall is to form through low-pressure chemical vapor phase deposition, and its thickness is between 50 to 200 dusts.
23, the method for contact hole in the suprabasil silicon oxide layer of semiconductor aimed in formation as claimed in claim 15 voluntarily, it is characterized in that heavy doping source electrode/drain region forms through implanting arsenic or phosphonium ion, its energy is between 40 to 80KeV, and dosage is at 1E14 to 1E15 atom/cm
2Between, implant angle is between 0 to 7 degree.
24, the method for contact hole in the suprabasil silicon oxide layer of semiconductor aimed in formation as claimed in claim 15 voluntarily, it is characterized in that interval at the grid structure that is covered by silicon nitride that comprises compound clearance wall is between 0.01 to 0.10 micron.
25, the method for contact hole in the suprabasil silicon oxide layer of semiconductor aimed in formation as claimed in claim 15 voluntarily, it is characterized in that silicon oxide layer is to amass or one of them mode of plasma enhanced CVD forms through the low pressure chemical gas phase, its thickness is between 3000 to 12000 dusts.
26, the method for contact hole in the suprabasil silicon oxide layer of semiconductor aimed in formation as claimed in claim 15 voluntarily, it is characterized in that the diameter of aiming at contact hole voluntarily in silicon oxide layer is between 0.01 to 0.1 micron.
27, the method for contact hole in the suprabasil silicon oxide layer of semiconductor aimed in formation as claimed in claim 15 voluntarily, and one of them is formed by doped polycrystalline silicon, tungsten silicide or tungsten to it is characterized in that aiming at voluntarily contact structures.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 01100532 CN1206706C (en) | 2001-01-11 | 2001-01-11 | Method for forming self aligning contact window structure on semiconductor substrate |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 01100532 CN1206706C (en) | 2001-01-11 | 2001-01-11 | Method for forming self aligning contact window structure on semiconductor substrate |
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| CN1365137A true CN1365137A (en) | 2002-08-21 |
| CN1206706C CN1206706C (en) | 2005-06-15 |
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| CN 01100532 Expired - Lifetime CN1206706C (en) | 2001-01-11 | 2001-01-11 | Method for forming self aligning contact window structure on semiconductor substrate |
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Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN100394552C (en) * | 2005-04-18 | 2008-06-11 | 力晶半导体股份有限公司 | Contact window opening formation and its production of semiconductor component |
| CN100421218C (en) * | 2005-04-18 | 2008-09-24 | 力晶半导体股份有限公司 | Semiconductor with self-aligning contact window and its production |
| CN101989548B (en) * | 2009-08-06 | 2012-08-22 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and manufacturing method thereof |
| CN103632952A (en) * | 2012-08-29 | 2014-03-12 | 无锡华润华晶微电子有限公司 | Elimination method of suspension step in multilayer composite film |
| CN103824763A (en) * | 2012-11-19 | 2014-05-28 | 上海华虹宏力半导体制造有限公司 | Method for improving tungsten silicide bigrid edge roughness of self-aligning contact hole |
| CN106033742A (en) * | 2015-03-20 | 2016-10-19 | 中芯国际集成电路制造(上海)有限公司 | Forming method of semiconductor structure |
| CN106356299A (en) * | 2015-07-13 | 2017-01-25 | 联华电子股份有限公司 | Semiconductor structure with self-aligned spacer and manufacturing method of semiconductor structure with self-aligned spacer |
| CN107104145A (en) * | 2016-02-19 | 2017-08-29 | 北大方正集团有限公司 | The preparation method and field-effect transistor of field-effect transistor |
| CN109065456A (en) * | 2018-09-27 | 2018-12-21 | 上海华力微电子有限公司 | A kind of forming method of MOS transistor and the forming method of cmos image sensor |
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2001
- 2001-01-11 CN CN 01100532 patent/CN1206706C/en not_active Expired - Lifetime
Cited By (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100421218C (en) * | 2005-04-18 | 2008-09-24 | 力晶半导体股份有限公司 | Semiconductor with self-aligning contact window and its production |
| CN100394552C (en) * | 2005-04-18 | 2008-06-11 | 力晶半导体股份有限公司 | Contact window opening formation and its production of semiconductor component |
| CN101989548B (en) * | 2009-08-06 | 2012-08-22 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and manufacturing method thereof |
| CN103632952B (en) * | 2012-08-29 | 2016-12-21 | 无锡华润华晶微电子有限公司 | The removing method of hanging step in multilayer complex films |
| CN103632952A (en) * | 2012-08-29 | 2014-03-12 | 无锡华润华晶微电子有限公司 | Elimination method of suspension step in multilayer composite film |
| CN103824763A (en) * | 2012-11-19 | 2014-05-28 | 上海华虹宏力半导体制造有限公司 | Method for improving tungsten silicide bigrid edge roughness of self-aligning contact hole |
| CN103824763B (en) * | 2012-11-19 | 2016-08-17 | 上海华虹宏力半导体制造有限公司 | The method improving the tungsten silicide bigrid edge roughness of self-aligned contact hole |
| CN106033742A (en) * | 2015-03-20 | 2016-10-19 | 中芯国际集成电路制造(上海)有限公司 | Forming method of semiconductor structure |
| CN106033742B (en) * | 2015-03-20 | 2019-03-29 | 中芯国际集成电路制造(上海)有限公司 | The forming method of semiconductor structure |
| CN106356299A (en) * | 2015-07-13 | 2017-01-25 | 联华电子股份有限公司 | Semiconductor structure with self-aligned spacer and manufacturing method of semiconductor structure with self-aligned spacer |
| CN106356299B (en) * | 2015-07-13 | 2021-04-13 | 联华电子股份有限公司 | Semiconductor structure with self-aligned spacer and manufacturing method thereof |
| CN107104145A (en) * | 2016-02-19 | 2017-08-29 | 北大方正集团有限公司 | The preparation method and field-effect transistor of field-effect transistor |
| CN107104145B (en) * | 2016-02-19 | 2020-08-07 | 北大方正集团有限公司 | Preparation method of field effect transistor and field effect transistor |
| CN109065456A (en) * | 2018-09-27 | 2018-12-21 | 上海华力微电子有限公司 | A kind of forming method of MOS transistor and the forming method of cmos image sensor |
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