CN1355417A - Method of Measuring Equivalent Gate Channel Length by C-V Method - Google Patents

Abstract

The present invention provides a capacitance-voltage (C-V) method for measuring an equivalent gate channel length in a device and simultaneously obtaining a gate etch bias length and a gate-drain overlap length in the device. In the method, the error between the grid length measured by the method and the actual grid length measured by the actual electron microscope scanner is less than 5%. Furthermore, the calculation method used in the present invention is only a simple simultaneous equation, which can be obtained by using manual calculation or a computer. With the continuous reduction of design rules, the present invention provides a simple method to determine the important parameters of the device.

Description

Method of measuring equivalent gate channel length by C-V method

The present invention relates to a method for measuring the length of an equivalent gate channel, in particular to a method for measuring the length of an equivalent gate channel by a capacitance-voltage method (C-V method).

In CMOS fabrication technology, gate channel length is a key parameter for designing device performance (circuit mode), short channel design, and process control. The gate channel length is different from the gate length due to gate lithography and etching deviation, but depends on the source/drain lateral phase diffusion.

Usually, the gate channel length is obtained by using a current-voltage method (I-Vmethod). This I-V method is based on a series of lined (or low drain deviation) I-V curves, including The I-V curves of many components with different mask lengths were calculated. However, the gate channel length of MOSFETs becomes more difficult to measure in the deep sub-micron region. Because, with the change of gate voltage, there will be a greater variation in mobility, the more significant effect is in the appearance of graded source/drain doping, and the line width dependent micro The deviation of shadow technology is approaching the limit of optics.

However, the general IV method is suitable for components with long channel design, but not completely suitable for components with short channel design. Therefore, an improved channel length extraction algorithm (channel length extraction algorithm), such as a shift and ratio method (S & D method), was born accordingly. However, the S&D method is quite complicated and cumbersome in use and cannot separately calculate the gate etching deviation length L _pb and the gate-drain coverage length L _overlap .

Therefore, with the continuous reduction of components, the known method of measuring channel length does not meet the current needs, and finding a simple and suitable method has become an important issue, especially for measuring a gate channel length, a gate etching method, etc. offset length, and a gate-drain overlay length.

An object of the present invention is to measure an equivalent gate channel length of a device using a C-V method.

Another object of the present invention is to more accurately measure a gate-to-drain overlap length and a gate etch bias length in a device using a C-V method.

According to the purpose described above, the present invention provides a kind of method that can simultaneously measure an equivalent gate channel length, a gate-drain overlapping length, and a method for gate etching deviation length with a CV method. Include at least the following steps. First, a first device including a source/drain and a gate on a substrate is provided. Wherein, the gate has a predetermined length L ₁ , a predetermined width W ₁ , and a predetermined height H ₁ , and the predetermined height is perpendicular to the predetermined length. Then, apply a negative voltage on the gate of the first element and measure a first capacitance between the gate and source/drain of the first element. Next, provide a positive voltage on the gate of the first device and measure a second capacitance between the gate and source/drain of the first device. Afterwards, a gate-to-drain overlap length of the first element is obtained by measuring the first capacitance. Then, continue to use the measurement of the second capacitance to obtain a gate etch bias length of the first device. Finally, the equivalent gate channel length of the first element is calculated by using the gate-drain overlapping length and the gate etching deviation length.

FIG. 1 shows various lengths defining different concepts in a metal oxide semiconductor device according to the method disclosed in the present invention.

Fig. 2 is the predetermined dimensions of each gate in the first element, the second element, and the third element.

Figure 3 shows how capacitance-voltage (C-V) measurements are set up.

Figure 4 is a graph of measured capacitance from gate to source/drain versus gate voltage.

Figure 5 is a graph of measured capacitance per unit width from gate to source/drain versus gate voltage.

Representative symbols of main parts:

10 Substrate

12 source/drain

  14  Equivalent Gate Channel Length

16 Gate-drain overlap length

20 Gate oxide layer

40 grid

42 Gate length

52 half gate etching deviation length

60 Gate etch mask

62 Gate etching length

201 Gate of the first element

202 Gate of the second element

203 Gate of the third element

The semiconductor design of the present invention can be widely applied in many semiconductor designs, and can utilize many different semiconductor materials to make, when the present invention illustrates the method of the present invention with a preferred embodiment, those who are familiar with this field should have It is recognized that many steps can be changed, and materials and impurities can also be replaced, and these general replacements undoubtedly do not depart from the spirit and scope of the present invention.

Secondly, the present invention is described in detail with schematic diagrams as follows. When describing the embodiments of the present invention in detail, the cross-sectional view showing the semiconductor structure will not be partially enlarged according to the general scale in the semiconductor manufacturing process for the convenience of explanation, but it should not be used as a limited definition. Know. In addition, in actual production, the three-dimensional space dimensions of length, width and depth should be included.

Some embodiments of the present invention are described in detail as follows. However, the invention may be practiced broadly in other embodiments than those described in detail, and the scope of the invention is not limited except by the appended claims.

Referring to FIG. 1 , the lengths of various concepts in a metal oxide semiconductor device are defined in this figure. Wherein, L _mask 62 is a designed length of a gate etching mask 60 , and will be copied to the length L _gate 42 of a gate 40 on the substrate 10 through processes such as lithography and etching. However, the L _gate may be longer or shorter than _{the L mask ,} it all depends on the deviation of lithography technology and etching. In addition, L _pb is defined as a gate etch bias length (gate etch bias), and a length 52 in FIG. 1 is half of the gate etch bias length (L _pb /2). Although L _gate is an important parameter used to control the quality of the process, there is no easy way to obtain this parameter. Typically, L _gates are obtained from electronic microscanners and sectioning the entire wafer. In addition, with the trend of miniaturization, a gate-to-drain overlap length L _overlap in metal oxide semiconductor devices has a greater impact on the operation and performance of the device, and L _overlap depends on the substrate The lateral phase diffusion of a source/drain 12 in 10. In addition, L _eff is defined as an effective gate channel length between source and drain, and L _eff must be obtained by measuring some electronic signals of the MOS device. L _gate and L _eff can be represented by one equation (1) and one equation (1)

L _pb ＝L _mask -L _gate (1)

L _eff ＝L _mask -L _pb -2*L _overlap (2)

Where L _pb is a gate etching offset length, L _mask is a predetermined length on the gate etching mask, L _gate is a gate length, and L _overlap is a gate-drain overlap length.

The method of the present invention comprises at least the following steps. First, a first element, a second element, and a third element are provided. Each device includes a source/drain and a gate on a substrate, as shown in FIG. 1 . With reference to Fig. 2, this figure is the first element, the second element, the predetermined size of each grid in the third element, its grid 201,202, and a predetermined length of 203, a predetermined width, and a predetermined height L ₁ , W ₁ , H ₁ ; L ₂ , W ₂ , H ₂ ; L ₃ , W ₃ , H ₃ ; L, W, H; (L/2), W, H; and L, (W/ 2), H. The difference between the first element and the second element lies in the width of the gate, and the difference between the first element and the third element lies in the length of the gate. These devices contain an inherent capacitance per unit width C _total between the gate and source/drain when a constant voltage is applied to the gate, and where C _total can be expressed as equation (3)

C _total ＝C _gate +2*C _overlap +2*C _fringing +(C _offset /W)(3)

Where C _gate is an internal gate-to-channel capacitance per unit width, C _overlap is a gate-to-drain overlap capacitance per unit width, and C _fringing is a The fringing capacitance per unit width, C _offset is a deviation capacitance from a measurement device, and W is the predetermined width of the gate. Among them, the fringing capacitance per unit width C _fringing in equation (3) can be expressed as an equation (4)

C _fringing ＝2*ε _oxide /π*ln[1+(H _gate /H _gateoxide )](4)

Wherein H _gate is a predetermined height of the gate, H _{gate oxide} is the height of a gate oxide layer 20 as shown in FIG. 1 , and ε _oxide is an electric field of the gate oxide layer. In this method, H _gate , H _{gate oxide} , and ε _oxide are all known fixed values, so C _fringing is also a certain value.

In the next step, an electronic serial number test procedure is performed to obtain some characteristic parameters of the device for measuring the equivalent gate channel length of the device. The result of the electronic signal test procedure is shown in FIG. 4 as a plot of the measured capacitance from gate to source/drain versus gate voltage. The setup of the electronic signal test procedure is shown in FIG. 3 . When the inherent capacitance per unit width C _total is given a negative voltage on the gate, it can be expressed as an accumulation (acculumation) capacitance per unit width C _acculumation , as shown in the following equation (5)

C _accumulation ＝2*C _overlap +2*C _fringing +(C _offset /W)(5)

Where C _acculumation is an accumulative capacitance per unit width when the gate is given a negative voltage. Referring to Figure 5, this graph plots the measured capacitance from gate to source/drain per unit width versus gate voltage. It can be seen from the figure that the change of the gate-drain overlap capacitance per unit width C _overlap in the accumulation area is quite small.

In another state, the inherent capacitance per unit width C _total can be expressed as an inversion capacitance per unit width C _inversion when the gate is given a positive voltage, as shown in the following equation (6)

C _inversion ＝C _gate +2*C _fringing +(C _offset /W)(6)

where C _inversion is the inversion capacitance per unit width when the gate is given a positive voltage.

Next, measuring an equivalent gate channel length includes at least one row of steps. First, apply a negative voltage on the gate of the first element and the second element. Then, measure a first capacitance between the gate and source/drain in the first element C _{acculumation, measured, 1} and measure a second capacitance between the gate and source/drain in the second element Between C _{acculumation, measured, 2} . In the next step, C _{accumulation, measured, 1} and C _{accumulation, measured, 2} are substituted into equation (5) and converted into one equation (5-1) and one equation (5-2)

C _{accumulation, measured, 1} = 2C _{overlap, 1} *W ₁ +2C _{fringing, 1} *W ₁ +C _{offset, 1} (5-1)

C _{accumulation, measured, 2} = 2C _{overlap, 2} *W ₂ +2C _{fringing, 2} *W ₂ +C _{offset, 2} (5-2)

Among them, W ₁ and W ₂ are known, while C _{fringing, 1} and C _{fringing, 2} are the same fixed value. C _{overlap, 1} and C _{overlep, 1} are considered equal because the gate-drain overlap capacitance per unit width varies relatively little over the accumulation area. Therefore, C _overlap and C _offset of the first element are immediately obtained by uncoupling Equation (5-1) and Equation (5-2).

Then, a gate-drain overlap length L _overlap of the first element can be obtained by an equation (7)

L _overlap ＝(H _gateoxide *C _overlap )/ε _oxide (7)

Where H _gateoxide is the height of a gate oxide layer 20 as shown in FIG. 1 , and ε _oxide is an electric field of the gate oxide layer.

Next, apply a positive voltage on the gates of the first element and the third element. A third capacitance C _{inversion,measured,1 is measured} between gate and source/drain in the first element and a fourth capacitance is measured between gate and source/drain in the second element Capacitance C _{inversion, measured, 3} . In the next step, C _{inversion, measured, 1} and C _{inversion, measured, 3} are substituted into equation (6) and converted into an equation (6-1) and an equation (6-2)

C _{inversion, measured, 1} = C _{gate, 1} *W ₁ +2C _{fringing, 1} *W ₁ +C _{offset, 1} (6-1)

C _{inversion, measured, 3} = C _{gate, 3} *W ₃ +2C _{fringing, 3} *W ₃ +C _{offset, 3} (6-2)

where W ₁ and W ₃ are known, while C _{fringing, 1} and C _{fringing, 3} are fixed values. C _overlap and C _offset can be obtained immediately by solving equation (5-1) and equation (5-2). Therefore, C _gate,1 and C _gate,3 can be obtained from Equation (6-1) and Equation (6-2). Furthermore, the gate length L _gate of the first element can be obtained from an equation (8)

.L _gate = (C _gate *W)*(L ₁ -L ₃ )/[(C _{gate, 1} -C _{gate, 3} )*W] (8)

Wherein L _gate is the gate length of the first element, C _gate is equivalent to the C _{gate, 1} of the first element, and W is equivalent to W ₁ and W ₃ .

Next, the _gate etching deviation length L _pb can be obtained from the equation (1) L _pb =L _mask −L gate. Finally, the equivalent gate channel length L _eff is obtained from the equation (2) L _eff =L _mask -L _pb -2*L _overlap .

Based on the above, the present invention provides a capacitance-voltage method to measure the equivalent gate channel length in an element, and can simultaneously obtain a gate etching deviation length and a gate-drain overlap in the element length. In the method, the error between the grid length measured by the method and the actual grid length measured by the actual electron microscope scanner is less than 5%. What's more, the calculation method used in the present invention is only simple simultaneous equations, which can be obtained by manual calculation or computer. With the continuous miniaturization of design rules, the present invention provides a simple method to obtain important parameters in components.

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the patent scope of the present invention; all other equivalent changes or modifications that do not deviate from the spirit disclosed in the present invention should be included in the following within the scope of the patent application.

Claims (15)

1. A method for measuring an equivalent gate channel length with a capacitance-voltage method, is characterized in that, at least includes: providing a first element comprising a source/drain and a gate on a substrate, wherein the gate has a predetermined length L ₁ , a predetermined width W ₁ , and a predetermined height H ₁ , and the the predetermined height is perpendicular to the predetermined length; providing a negative voltage on the gate of the first element; measuring a first capacitance between the gate and the source/drain of the first element when at the negative voltage; providing a positive voltage on the gate of the first element; measuring a second capacitance between the gate and the source/drain of the first element when at the positive voltage; using said measured first capacitance to find a gate-drain overlap length of said first element; using the measured second capacitance to find a gate etch offset length of the first element; and The equivalent gate channel length of the first element is calculated from the gate-drain overlapping length and the gate etching deviation length. 2. The method of claim 1, wherein the first element comprises an inherent capacitance per unit width C _total between the gate and the source/drain, and wherein C _total can be As shown in a first equation C _total =C _gate +2*C _overlap +2*C _fringing +(C _offset /W) in C _gate is an internal gate-to-channel capacitance per unit width, C _overlap is a gate-drain overlap capacitance per unit width, C _fringing is a fringe capacitance per unit width, C _offset is an offset capacitance from a measurement device, and W is the predetermined width of the gate. 3. The method according to claim 2, characterized in that, when the inherent capacitance per unit width C _total is under the negative voltage, it can be expressed as a cumulative capacitance per unit width C _acculumation , as shown in the following second equation C _accumulation ＝2*C _overlap +2*C _fringing +(C _offset /W) 4. The method of claim 3, wherein said step of using said measured first capacitance to obtain said gate-drain overlap length of said first element comprises at least the following steps: Substituting the measured first capacitance C _{acculumation, measured, 1} into the second equation into a third-party formula C _{acculumation, measured, 1} = 2*C _{overlap, 1} *W ₁ +2*C _{fringing, 1} *W ₁ +C _{offset, 1} providing a second element, wherein a gate of the second element differs from the first element only by a predetermined width; providing the negative voltage on the gate of the second element; measuring a third capacitance between the gate of the second element and a source/drain when at the negative voltage; Substituting the measured third capacitance C _{acculumation, measured, 2} into the second equation into a fourth equation C _{accumulation, measured, 2} = 2*C _{overlap, 2} *W ₂ +2*C _{fringing, 2} *W ₂ +C _{offset, 2} The gate-drain overlap capacitance per unit width C _overlap of the first element is calculated by using the third equation and the fourth equation. 5. The method of claim 4, wherein the gate-drain overlap length L _overlap of the first element is calculated by a fifth equation L _overlap ＝(H _gateoxide *C _overlap )/ε _oxide in H _gateoxide is a height of a gate oxide layer of the first element and ε _oxide is an electric field of a gate oxide layer of the first element. 6. The method according to claim 2, wherein, when the inherent capacitance per unit width C _total is under the positive voltage, it can be expressed as an inversion capacitance per unit width C _inversion , as shown in the sixth equation Show C _inversion ＝C _gate +2*C _fringing +(C _offset /W) 7. The method according to claim 6, wherein the step of obtaining the gate etching deviation length of the first element by using the measured second capacitance comprises at least the following steps: Substituting the measured second capacitance C _{inversion,measured,1} into the sixth equation into a seventh equation C _{inversion, measured, 1} = C _{gate, 1} *W ₁ +2*C _{fringing, 1} *W ₁ +C _{offset, 1} providing a third element, wherein a gate of the third element differs from the first element only by a predetermined length; providing said positive voltage on said gate of said third element; measuring a fourth capacitance between said gate of said third element and a source/drain when at said negative voltage; Substituting the measured fourth capacitance C _{inversion,measured,3} into the sixth equation into an eighth equation C _{inversion, measured, 3} = C _{gate, 3} *W ₃ +2*C _{fringing, 3} *W ₃ +C _{offset, 3} in W ₃ is a predetermined width of the gate of the third element; and An equivalent gate length L _gate of the first element is calculated according to the seventh equation and the eighth equation. 8. The method according to claim 7, wherein the gate etching deviation length _Lpb is calculated by a ninth equation L _pb ＝L _mask -L _gate in L _mask is a length on a photomask used to define the predetermined length of the gate of the first element and L _gate is the equivalent gate length of the first element. 9. The method according to claim 8, wherein the equivalent gate channel length L _eff of the first element is calculated by the following (10) equation L _eff ＝L _mask -L _pb -2*L _overlap 10. A method for measuring an equivalent gate channel length with a capacitance-voltage method, characterized in that it at least includes: providing a first element comprising a source/drain and a gate on a substrate, wherein the gate has a predetermined length L ₁ , a predetermined width W ₁ , and a predetermined height H ₁ , and the The predetermined height is perpendicular to the predetermined length, and wherein the first element comprises an inherent capacitance per unit width C _total between the gate and the source/drain, and wherein C _total can be expressed as a first equation shown C _total ＝C _gate +2*C _overlap +2*C _fringing +(C _offset /W) in C _gate is an internal gate-to-channel capacitance per unit width, C _overlap is a gate-drain overlap capacitance per unit width, C _fringing is a fringe capacitance per unit width, C _offset is an offset capacitance from a measurement device, and W is the predetermined width of the gate; Providing a negative voltage on the gate of the first element, wherein the inherent capacitance per unit width C _total at the negative voltage can be expressed as an accumulation capacitance per unit width C _acculumation , such as a second equation shown C _accumulation = 2*C _overlap +2*C _fringing +(C _offset /W); measuring a first capacitance between the gate and the source/drain of the first element when at the negative voltage; Provide a positive voltage on the gate of the first element, wherein when the inherent capacitance per unit width C _total is under the positive voltage, it can be expressed as an inversion capacitance per unit width C _inversion , such as a third shown in the equation C _inversion = C _gate +2*C _fringing +(C _offset /W); measuring a second capacitance between the gate and the source/drain of the first element when at the positive voltage; using said measured first capacitance to find a gate-drain overlap length of said first element; using the measured second capacitance to find a gate etch offset length of the first element; and The equivalent gate channel length of the first element is calculated from the gate-drain overlapping length and the gate etching deviation length. 11. The method of claim 10, wherein said step of using said measured first capacitance to find said gate-drain overlap length of said first element comprises at least the following steps: Substituting the measured first capacitance C _{acculumation, measured, 1} into the second equation into a fourth equation C _{accumulation, measured, 1} = 2*C _{overlap, 1} *W ₁ +2*C _{fringing, 1} *W ₁ +C _{offset, 1} providing a second element, wherein a gate of the second element differs from the first element only by a predetermined width; providing the negative voltage on the gate of the second element; measuring a third capacitance between the gate of the second element and a source/drain when at the negative voltage; Substituting the measured third capacitance C _{acculumation, measured, 2} into the second equation into a fifth equation C _{accumulation, measured, 2} = 2*C _{overlap, 2} *W ₂ +2*C _{fringing, 2} *W ₂ +C _{offset, 2} The gate-drain overlap capacitance per unit width C _overlap of the first element is calculated according to the fourth equation and the fifth equation. 12. The method of claim 11, wherein the gate-drain overlap length L _overlap of the first element is calculated by a sixth equation L _overlap ＝(H _gateoxide *C _overlap )/ε _oxide in H _gateoxide is a height of a gate oxide layer of the first element and ε _oxide is an electric field for a gate oxide layer of the first element. 13. The method according to claim 10, wherein the step of obtaining the gate etching deviation length of the first element by using the measured second capacitance comprises at least the following steps: Substituting the measured second capacitance C _{inversion,measured,1} into the third-party program into a seventh equation C _{inversion, measured, 1} = C _{gate, 1} *W ₁ +2*C _{fringing, 1} *W ₁ +C _{offset, 1} providing a third element, wherein a gate of the third element differs from the first element only by a predetermined length; providing said positive voltage on said gate of said third element; measuring a fourth capacitance between said gate of said third element and a source/drain when at said negative voltage; Substituting the measured fourth capacitance C _{inversion, measured, 3} into the third-party program into an eighth equation C _{inversion, measured, 3} = C _{gate, 3} *W ₃ +2*C _{fringing, 3} *W ₃ +C _{offset, 3} in W ₃ is a predetermined width of the gate of the third element; and An equivalent gate length L _gate of the first element is calculated according to the seventh equation and the eighth equation. 14. The method according to claim 13, wherein the gate etching deviation length L _pb is calculated by a ninth equation L _pb ＝L _mask -L _gate in L _mask is a length on a photomask used to define the predetermined length of the gate of the first element and L _gate is the equivalent gate length of the first element. 15. The method according to claim 10, wherein the equivalent gate channel length L _eff of the first element is calculated from the following equation L _eff =L _mask -L _pb -2*L _overlap .

Images