CN1355417A - Method for measuring equivalent length of grid channel by C-V method - Google Patents
Method for measuring equivalent length of grid channel by C-V method Download PDFInfo
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- CN1355417A CN1355417A CN 00135213 CN00135213A CN1355417A CN 1355417 A CN1355417 A CN 1355417A CN 00135213 CN00135213 CN 00135213 CN 00135213 A CN00135213 A CN 00135213A CN 1355417 A CN1355417 A CN 1355417A
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Abstract
A capacitance-voltage (C-V) method for measuring an equivalent length of grid channel in an element, the etching deviation length of grid and the overlap legnth between grid and drain is disclosed. Its advantages include high measuring precision (deviation in length less than 5%), and simple algorithm (simultaneous equations).
Description
The present invention is about the method for a kind of measurement one equivalent length of grid channel, and particularly (capacitance-voltage method C-Vmethod) measures the method for an equivalent length of grid channel with a capacitance-voltage method about a kind of.
In the complementary metal oxide semiconductor fabrication, length of grid channel is that a key parameter is used for design element usefulness (circuit-mode), short channel design, and processing procedure control.Length of grid channel is different from grid length and depends on grid micro image technology and etched deviation, but depends on that the side of source/drain spreads mutually.
Usually, length of grid channel is to use a current-voltage method (current-voltage method, I-Vmethod) try to achieve, this I-V method is that the I-V curve that has wherein comprised the element of many different shade length is calculated to be obtained with the I-V curve of a series of one-tenth lines (or low drain electrode deviation).Yet the metal oxide semiconductor field effect electric crystal gets length of grid channel more difficult the going that become and measures in the deep-sub-micrometer zone.Because, along with the variation mobility (mobility) of grid voltage has bigger variation, more significant effect is mixed presenting of (graded source/drain doping) at the gradient source/drain, and little shadow technology deviation that live width relies on is in the approaching optic limit.
Yet general I-V method is applicable to the element of long channel design, and also not exclusively is applicable to the element of short channel design.Therefore, a kind of channel length extraction algorithm of improvement (channel length extractionalgorithm) in response to and give birth to, for example one the displacement and ratio method (shift and ratio method, S ﹠amp; Dmethod).Yet, this S ﹠amp; The D method is quite complicated in the use loaded down with trivial details and can't obtain gate etch deviation length L respectively
PbWith gate-to-drain overlay length L
Overlap
Therefore, be not inconsistent present needs along with element constantly dwindles known measurement channel length method, finding out once the simple method that is fit to again becomes an important topic, particularly is used for measuring a length of grid channel, an one gate etch deviation length and a gate-to-drain overlay length.
A purpose of the present invention is to use a C-V method to measure an equivalent length of grid channel of an element.
Another object of the present invention is to use a C-V method to measure overlapping (gate-to-drain overlap) length of a gate-to-drain and a gate etch deviation (gate etch bias) length in the element more accurately.
According to above-described purpose, the invention provides and a kind ofly can measure an equivalent length of grid channel simultaneously with a C-V method, the method for a gate-to-drain overlap length and a gate etch deviation length, the method comprises the following step at least.At first, provide one first element to comprise source and a grid on a substrate.Wherein, this grid has a predetermined length L
1, a preset width W
1An and predetermined altitude H
1, and predetermined altitude is perpendicular to predetermined length.Then, provide a negative voltage on the grid of first element, also to measure at the grid of first element and one first electric capacity of source/drain interpolar.Then, provide a positive voltage on the grid of first element, also to measure again at the grid of first element and one second electric capacity of source/drain interpolar.Afterwards, use measurement first electric capacity with a gate-to-drain of obtaining first element overlapping (gate-to-drain overlap) length.Then, continue to use a gate etch deviation (the gate etch bias) length of measurement second electric capacity to obtain first element.At last, mat gate-to-drain overlap length and gate etch deviation length gauge are calculated the equivalent length of grid channel of first element.
Fig. 1 is all lengths that defines different concepts according to the disclosed method of the present invention in a metal-oxide semiconductor element.
Fig. 2 is first element, second element, the preliminary dimension of each grid in the three element.
Fig. 3 is the setting means that capacitance-voltage (C-V) is measured.
Fig. 4 is a grid to the measurement electric capacity of the source/drain diagrammatic sketch to grid voltage.
Fig. 5 is a grid to the measurement electric capacity per unit width of the source/drain diagrammatic sketch to grid voltage.
The conventional letter of major part:
10 substrates
12 source/drains
14 equivalent length of grid channel
16 gate-to-drain overlap lengths
20 grid oxic horizons
40 grids
42 grid lengths
52 half gate etch deviation length
60 gate etch shades
62 gate etch length
The grid of 201 first elements
The grid of 202 second elements
203 three-element grids
Semiconductor design of the present invention can be widely applied in many semiconductor design, and can utilize many different semi-conducting material manufacturings, when the present invention illustrates the inventive method with a preferred embodiment, the due cognition of personage of being familiar with this field is that many steps can change, material and impurity are also replaceable, and these general replacements also do not break away from spirit of the present invention and category far and away.
Secondly, the present invention is described in detail as follows with synoptic diagram, and when the detailed description embodiment of the invention, the sectional view of expression semiconductor structure can be disobeyed general ratio and be done local the amplification in order to explanation in manufacture of semiconductor, so should be with this as the cognition that qualification is arranged.In addition, in the making of reality, should comprise the three dimensions size of length, width and the degree of depth.
Some embodiments of the present invention can be described in detail as follows.Yet except describing in detail, the present invention can also be widely implements at other embodiment, and scope of invention do not limited, and is as the criterion with appending claims.
With reference to Fig. 1, on this figure, define the length of various different concepts in the metal-oxide semiconductor element.Wherein, L
Mask62 is a design length of a gate etch shade 60, and can copy to the length L of a grid 40 on the substrate 10 by processing procedures such as little shadow and etchings
Gate42.Yet, L
GateMay compare L
MaskLong or compare L
MaskShort, this depends on little shadow technology and etched deviation fully.In addition, L
PbBe defined as a gate etch deviation length (gateetchbias), and a length 52 is the gate etch deviation length (L of half among Fig. 1
Pb/ 2).Though, L
GateBe the quality that an important parameters is used for operating the control processing procedure, but do not have simple mode to go to obtain this parameter.Usually, L
GateAcquisition come from electronic type microscan device and cut entire wafer open.In addition, along with trend gate-to-drain in the metal-oxide semiconductor element overlapping (gate-to-drainoverlap) length L of downsizing
OverlapOperation and usefulness influence to element are increasing, and L
OverlapThe side that depends on source 12 in the substrate 10 spreads mutually.In addition, L
EffBe defined as an equivalent length of grid channel (effectivegate channel length) at the source/drain interpolar, and L
EffMust obtain by some electronic signals of measuring the metal-oxide semiconductor element.L
GateAnd L
EffCan an equation (1) and an equation (1) represent
L
pb＝L
mask-L
gate(1)
L
eff＝L
mask-L
pb-2*L
overlap(2)
L wherein
PbBe a gate etch deviation length, L
MaskBe a preset length on the gate etch shade, L
GateBe a grid length, and L
OverlapIt is a gate-to-drain overlap length.
Method of the present invention comprises the following step at least.At first, provide one first element, one second element and a three element.Each element system comprises source and a grid on a substrate, as shown in Figure 1.With reference to Fig. 2, this figure is first element, second element, the preliminary dimension of each grid in the three element, its grid 201,202 and a predetermined length of 203, a preset width and a predetermined altitude L
1, W
1, H
1L
2, W
2, H
2L
3, W
3, H
3Be respectively L, W, H; (L/2), W, H; And L, (W/2), H.The different width differences that are in grid of first element and second element, and first element is different with the length of the three-element grid that do not coexist.These element systems comprise a natural capacity per unit width C
TotalGive one when deciding voltage at grid and source/drain interpolar when grid, and C wherein
TotalCan be shown in equation (3)
C
total＝C
gate+2*C
overlap+2*C
fringing+(C
offset/W)(3)
C wherein
GateBe one internal gate-raceway groove (gate-to-channel) electric capacity per unit width, C
OverlapBe a gate-to-drain overlapping (gate-to-drain overlap) electric capacity per unit width, C
FringingBe an edge (fringing) electric capacity per unit width, C
OffsetBe a deviation (deviation) electric capacity, and W is the preset width of grid from a measurement mechanism.Wherein, the edge capacitance per unit width C in the equation (3)
FringingCan be expressed as an equation (4) again
C
fringing＝2*ε
oxide/π*ln[1+(H
gate/H
gateoxide)](4)
H wherein
GateBe a predetermined altitude of grid, H
GateoxideBe the height of a grid oxic horizon 20 as shown in Figure 1, and ε
OxideIt is an electric field of grid oxic horizon.In the method, H
Gate, H
Gateoxide, and ε
OxideAll be known definite value, so C
FringingIt also is certain value.
Next step carries out an electronic serial number test procedure and is used for the equivalent length of grid channel of measuring sensor with the characteristic parameter that obtains some elements.This electronic signal test procedure result is illustrated in figure 4 as grid to the mapping to grid voltage of the measurement electric capacity of source/drain, and the setting of electronic signal test procedure then as shown in Figure 3.As natural capacity per unit width C
TotalBe given negative voltage following time at grid and can be expressed as accumulation (acculumation) electric capacity per unit width C
Acculumation, shown in next equation (5)
C
acculumation＝2*C
overlap+2*C
fringing+(C
offset/W)(5)
C wherein
AcculumationBeing an accumulation electric capacity per unit width is given negative voltage following time at grid.With reference to Fig. 5, this figure is a grid to the mapping to grid voltage of the measurement electric capacity per unit width of source/drain.By gate-to-drain overlap capacitance per unit width C as can be known on the figure
OverlapVariation when the accumulation area is quite little.
Under another state, natural capacity per unit width C
TotalBe given positive voltage following time at grid and can be expressed as counter-rotating (inversion) electric capacity per unit width C
Inversion, shown in next equation (6)
C
inversion＝C
gate+2*C
fringing+(C
offset/W)(6)
C wherein
InversionBeing the inversion capacitance per unit width is given positive voltage following time when grid.
Next, measure an equivalent length of grid channel and comprise the row step at least.At first, provide a negative voltage on grid at first element and second element.Then, in first element, measure one first electric capacity at grid and source/drain interpolar C
Acculumation, measured, 1With in second element, measure one second electric capacity at grid and source/drain interpolar C
Acculumation, measured, 2Next step is with C
Acculumation, measured, 1And C
Acculumation, measured, 2Convert an equation (5-1) and an equation (5-2) in the substitution equation (5) to
C
accumulation，measured，1＝2C
overlap，1*W
1+2C
fringing，1*W
1+C
offset，1(5-1)
C
accumulation，measured，2＝2C
overlap，2*W
2+2C
fringing，2*W
2+C
offset，2(5-2)
W wherein
1And W
2Be known, and C
Fringing, 1And C
Fringing, 2It is identical definite value.Because the variation of gate-to-drain overlap capacitance per unit width when the accumulation area is quite little, so C
Overlap, 1And C
Overlep, 1Be considered as equating.Therefore, equation (5-1) and equation (5-2) are de-connected the C that can obtain first element immediately
OverlapAnd C
Offset
Then, a gate-to-drain overlap length L of first element
OverlapCan obtain by an equation (7)
L
overlap＝(H
gateoxide*C
overlap)/ε
oxide(7)
H wherein
GateoxideBe the height of a grid oxic horizon 20 as shown in Figure 1, and ε
OxideIt is an electric field of grid oxic horizon.
Next step provides a positive voltage on grid at first element and three element.In first element, measure one the 3rd capacitor C at grid and source/drain interpolar
Inversion, measured, 1With one the 4th capacitor C that in second element, measures at grid and source/drain interpolar
Inversion, measured, 3Next step is with C
Inversion, measured, 1And C
Inversion, measured, 3Convert an equation (6-1) and an equation (6-2) in the substitution equation (6) to
C
inversion，measured，1＝C
gate，1*W
1+2C
fringing，1*W
1+C
offset，1(6-1)
C
inversion，measured，3＝C
gate，3*W
3+2C
fringing，3*W
3+C
offset，3(6-2)
W wherein
1And W
3Be known, and C
Fringing, 1And C
Fringing, 3It is definite value.C
OverlapAnd C
OffsetCan de-connect immediately and can obtain by equation (5-1) and equation (5-2).Therefore, can obtain C by equation (6-1) and equation (6-2)
Gate, 1And C
Gate, 3Further, can obtain the grid length L of first element by an equation (8)
Gate
.L
gate＝(C
gate*W)*(L
1-L
3)/[(C
gate，1-C
gate，3)*W](8)
L wherein
GateBe the grid length of first element, C
GateBe the C that is equivalent to first element
Gate, 1, and W is equivalent to W
1And W
3
Then, can be by equation (1) L
Pb=L
Mask-L
GateObtain gate etch deviation length L
PbAt last, again by equation (2) L
Eff=L
Mask-L
Pb-2*L
OverlapObtain equivalent length of grid channel L
Eff
Comprehensive the above, the capacitance-voltage method that the invention provides is measured the equivalent length of grid channel in the element, and can obtain gate etch deviation length and gate-to-drain overlap length one by one in the element simultaneously.In this method, the actual gate error that grid length that use this method is measured and actual electron microscopic formula scanner are measured is lower than 5%.What is more, computing method used in the present invention only are simple simultaneous equations, use artificial calculating or computer just can obtain.Along with the continuous downsizing of Design Rule, the simple method that the invention provides is to obtain important parameters in the element.
The above only is the present invention's preferred embodiment, is not in order to limit the present invention's claim; All other do not break away from following equivalence of finishing of disclosed spirit and changes or modification, all should be included in the following claim.
Claims (15)
1. measure the method for an equivalent length of grid channel with a capacitance-voltage method for one kind, it is characterized in that, comprise at least:
Provide one first element to comprise source and a grid on a substrate, wherein said grid has a predetermined length L
1, a preset width W
1An and predetermined altitude H
1, and described predetermined altitude is perpendicular to described predetermined length;
Provide a negative voltage on the described grid of described first element;
When being under the described negative voltage, measure at the described grid of described first element and one first electric capacity of described source/drain interpolar;
Provide a positive voltage on the described grid of described first element;
When being under the described positive voltage, measure at the described grid of described first element and one second electric capacity of described source/drain interpolar;
Use described measurement first electric capacity to obtain a gate-to-drain overlap length of described first element;
Use described measurement second electric capacity to obtain a gate etch deviation length of described first element; And
Calculate the described equivalent length of grid channel of described first element by described gate-to-drain overlap length and described gate etch deviation length gauge.
2. the method for claim 1 is characterized in that, described first element is included in a natural capacity per unit width C of described grid and described source/drain interpolar
Total, and C wherein
TotalCan be shown in a first party formula C
Total=C
Gate+ 2*C
Overlap+ 2*C
Fringing+ (C
Offset/ W)
Wherein
C
GateBe an internal gate to the channel capacitance per unit width,
C
OverlapBe a gate-to-drain overlap capacitance per unit width,
C
FringingBe an edge electric capacity per unit width,
C
OffsetBe a deviation electric capacity from a measurement mechanism, and
W is the described preset width of described grid.
3. method as claimed in claim 2 is characterized in that, described natural capacity per unit width C
TotalBeing in described negative voltage following time can be expressed as an accumulation electric capacity per unit width C
Acculumation, shown in next second party formula
C
acculumation＝2*C
overlap+2*C
fringing+(C
offset/W)
4. method as claimed in claim 3 is characterized in that, the described step of using described measurement first electric capacity to obtain the described gate-to-drain overlap length of described first element comprises the following step at least:
With described measurement first capacitor C
Acculumation, measured, 1The described second party formula of substitution is converted to third party's formula C
Acculumation, measured, 1=2*C
Overlap, 1* W
1+ 2*C
Fringing, 1* W
1+ C
Offset, 1
One second element is provided, and a grid of wherein said second element is only different with described first element at a preset width;
Provide described negative voltage on the described grid of described second element;
When being under the described negative voltage, measure at the described grid of described second element and one the 3rd electric capacity between source;
With described measurement the 3rd capacitor C
Acculumation, measured, 2The described second party formula of substitution is converted to a cubic formula
C
acculumation，measured，2＝2*C
overlap，2*W
2+2*C
fringing，2*W
2+C
offset，2
Calculate the described gate-to-drain overlap capacitance per unit width C of described first element with described third party's formula and described cubic formula
Overlap
5. method as claimed in claim 4 is characterized in that, the described gate-to-drain overlap length L of described first element
OverlapCalculated by one the 5th equation
L
overlap＝(H
gateoxide*C
overlap)/ε
oxide
Wherein
H
GateoxideFor a height of a grid oxic horizon of described first element and
ε
OxideElectric field for a grid oxic horizon of described first element.
6. method as claimed in claim 2 is characterized in that, described natural capacity per unit width C
TotalBeing in described positive voltage following time can be expressed as an inversion capacitance per unit width C
Inversion, shown in next the 6th equation
C
inversion＝C
gate+2*C
fringing+(C
offset/W)
7. method as claimed in claim 6 is characterized in that, the described step of using described measurement second electric capacity to obtain the described gate etch deviation length of described first element comprises the following step at least:
With described measurement second capacitor C
Inversion, measured, 1Described the 6th equation of substitution is converted to one the 7th equation
C
inversion，measured，1＝C
gate，1*W
1+2*C
fringing，1*W
1+C
offset，1
One three element is provided, and a wherein said three-element grid is only different with described first element at a predetermined length;
Provide described positive voltage on described three-element described grid;
When being under the described negative voltage, measure one the 4th electric capacity between described three-element described grid and source;
With described measurement the 4th capacitor C
Inversion, measured, 3Described the 6th equation of substitution is converted to an all directions formula
C
inversion，measured，3＝C
gate，3*W
3+2*C
fringing，3*W
3+C
offset，3
Wherein
W
3Preset width for described three-element described grid; And
Calculate an equivalent grid length L of described first element with described the 7th equation and described all directions formula
Gate
8. method as claimed in claim 7 is characterized in that, described gate etch deviation length L
PbBe to calculate with one the 9th equation
L
pb＝L
mask-L
gate
Wherein
L
MaskBe a length on the light shield described grid that is used for defining described first element described predetermined length and
L
GateDescribed equivalent gate length for described first element.
9. method as claimed in claim 8 is characterized in that, the described equivalent length of grid channel L of described first element
EffSystem is with next the tenth equation) calculate
L
eff＝L
mask-L
pb-2*L
overlap
10. measure the method for an equivalent length of grid channel with a capacitance-voltage method for one kind, it is characterized in that, comprise at least:
Provide one first element to comprise source and a grid on a substrate, wherein said grid has a predetermined length L
1, a preset width W
1An and predetermined altitude H
1, and described predetermined altitude is perpendicular to described predetermined length, and wherein said first element is included in a natural capacity per unit width C of described grid and described source/drain interpolar
Total, and C wherein
TotalCan be shown in a first party formula
C
total＝C
gate+2*C
overlap+2*C
fringing+(C
offset/W)
Wherein
C
GateBe an internal gate to the channel capacitance per unit width,
C
OverlapBe a gate-to-drain overlap capacitance per unit width,
C
FringingBe an edge electric capacity per unit width,
C
OffsetBe a deviation electric capacity from a measurement mechanism, and
W is the described preset width of described grid;
Provide a negative voltage on the described grid of described first element, wherein said natural capacity per unit width C
TotalBeing in described negative voltage following time can be expressed as an accumulation electric capacity per unit width C
Acculumation, shown in a second party formula
C
acculumation＝2*C
overlap+2*C
fringing+(C
offset/W)；
When being under the described negative voltage, measure at the described grid of described first element and one first electric capacity of described source/drain interpolar;
Provide a positive voltage on the described grid of described first element, wherein said natural capacity per unit width C
TotalBeing in described positive voltage following time can be expressed as an inversion capacitance per unit width C
Inversion, shown in third party's formula
C
inversion＝C
gate+2*C
fringing+(C
offset/W)；
When being under the described positive voltage, measure at the described grid of described first element and one second electric capacity of described source/drain interpolar;
Use described measurement first electric capacity to obtain a gate-to-drain overlap length of described first element;
Use described measurement second electric capacity to obtain a gate etch deviation length of described first element; And
Calculate the described equivalent length of grid channel of described first element by described gate-to-drain overlap length and described gate etch deviation length gauge.
11. method as claimed in claim 10 is characterized in that, the described step of using described measurement first electric capacity to obtain the described gate-to-drain overlap length of described first element comprises the following step at least:
With described measurement first capacitor C
Acculumation, measured, 1The described second party formula of substitution is converted to a cubic formula
C
acculumation，measured，1＝2*C
overlap，1*W
1+2*C
fringing，1*W
1+C
offset，1
One second element is provided, and a grid of wherein said second element is only different with described first element at a preset width;
Provide described negative voltage on the described grid of described second element;
When being under the described negative voltage, measure at the described grid of described second element and one the 3rd electric capacity between source;
With described measurement the 3rd capacitor C
Acculumation, measured, 2The described second party formula of substitution is converted to one the 5th equation
C
acculumation，measured，2＝2*C
overlap，2*W
2+2*C
fringing，2*W
2+C
offset，2
Calculate the described gate-to-drain overlap capacitance per unit width C of described first element with described cubic formula and described the 5th equation
Overlap
12.. method as claimed in claim 11 is characterized in that, the described gate-to-drain overlap length L of described first element
OverlapCalculated by one the 6th equation
L
overlap＝(H
gateoxide*C
overlap)/ε
oxide
Wherein
H
GateoxideFor a height of a grid oxic horizon of described first element and
ε
OxideFor being an electric field of a grid oxic horizon of described first element.
13.. method as claimed in claim 10 is characterized in that, the described step of using described measurement second electric capacity to obtain the described gate etch deviation length of described first element comprises the following step at least:
With described measurement second capacitor C
Inversion, measured, 1The described third party's formula of substitution is converted to one the 7th equation
C
inversion，measured，1＝C
gate，1*W
1+2*C
fringing，1*W
1+C
offset，1
One three element is provided, and a wherein said three-element grid is only different with described first element at a predetermined length;
Provide described positive voltage on described three-element described grid;
When being under the described negative voltage, measure one the 4th electric capacity between described three-element described grid and source;
With described measurement the 4th capacitor C
Inversion, measured, 3The described third party's formula of substitution is converted to an all directions formula
C
inversion，measured，3＝C
gate，3*W
3+2*C
fringing，3*W
3+C
offset，3
Wherein
W
3Preset width for described three-element described grid; And
Calculate an equivalent grid length L of described first element with described the 7th equation and described all directions formula
Gate
14. method as claimed in claim 13 is characterized in that, described gate etch deviation length L
PbBe to calculate with one the 9th equation
L
pb＝L
mask-L
gate
Wherein
L
MaskBe a length on the light shield described grid that is used for defining described first element described predetermined length and
L
GateDescribed equivalent gate length for described first element.
15. method as claimed in claim 10 is characterized in that, the described equivalent length of grid channel L of described first element
EffBe to calculate with next the tenth equation
L
eff＝L
mask-L
pb-2*L
overlap。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB00135213XA CN1174216C (en) | 2000-11-27 | 2000-11-27 | Method for measuring equivalent length of grid channel by C-V method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB00135213XA CN1174216C (en) | 2000-11-27 | 2000-11-27 | Method for measuring equivalent length of grid channel by C-V method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1355417A true CN1355417A (en) | 2002-06-26 |
| CN1174216C CN1174216C (en) | 2004-11-03 |
Family
ID=4596655
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB00135213XA Expired - Lifetime CN1174216C (en) | 2000-11-27 | 2000-11-27 | Method for measuring equivalent length of grid channel by C-V method |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104218027B (en) * | 2013-06-05 | 2017-02-22 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor test structure and test method thereof |
| CN110400668A (en) * | 2018-04-24 | 2019-11-01 | 莫列斯有限公司 | Electronic component |
-
2000
- 2000-11-27 CN CNB00135213XA patent/CN1174216C/en not_active Expired - Lifetime
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104218027B (en) * | 2013-06-05 | 2017-02-22 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor test structure and test method thereof |
| CN110400668A (en) * | 2018-04-24 | 2019-11-01 | 莫列斯有限公司 | Electronic component |
| US11037895B2 (en) | 2018-04-24 | 2021-06-15 | Molex, Llc | Electronic component |
| CN110400668B (en) * | 2018-04-24 | 2022-02-08 | 莫列斯有限公司 | Electronic component |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1174216C (en) | 2004-11-03 |
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