CN1344982A - Method and apparatus for suspension and recovery of computer system operation - Google Patents
Method and apparatus for suspension and recovery of computer system operation Download PDFInfo
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- CN1344982A CN1344982A CN01141038A CN01141038A CN1344982A CN 1344982 A CN1344982 A CN 1344982A CN 01141038 A CN01141038 A CN 01141038A CN 01141038 A CN01141038 A CN 01141038A CN 1344982 A CN1344982 A CN 1344982A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/4401—Bootstrapping
- G06F9/4418—Suspend and resume; Hibernate and awake
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
- G06F1/3296—Power saving characterised by the action undertaken by lowering the supply or operating voltage
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0614—Improving the reliability of storage systems
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0625—Power saving in storage systems
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0673—Single storage device
- G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
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- Computer Security & Cryptography (AREA)
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Abstract
A method and apparatus for saving the state of computer systems components provides a resume capability for battery operated computer systems after integrated circuits within the computer system have been completely powered-down. The state is read from the microprocessor and various peripheral components and stored in non-volatile storage until computer system operation is resumed.
Description
Technical field
The present invention relates generally to computing system, and relate in particular to by end and recover the method for operating and the equipment of computer system at the state of storage computation machine system before microprocessor and peripheral assembly outage.
Background technology
Current computer systems provides power management, to preserve energy and reduce the heat that computer system produces when not needing system to activate.Notebook computer system and personal digital assistant (PDAs) also use power management to preserve the power of battery.Can be set to buttoned-up status to computer system, or place it in the various patterns that are known as " termination " or " recovery ", be used for together describing a kind of operator scheme together with other terms, wherein computer system partly activates, and waits for stimulating and recover the total system operation.Can detectedly be used for the example of stimulation of recovery operation is that mouse moves, modulator-demodular unit is dialled in and LAN (Local Area Network) (LAN) activates.
When the user was operating a computer system, " termination " function was vital for quick operation.When computer system short time interval when not having the user to import was preserved energy, it did not require and must or ressemble computer system from the buttoned-up status guiding.But abort function does not cut off the power supply to the microprocessor of control computer system usually.The large-scale microprocessor that uses in the current computer system and other integrated circuit have up to ten million transistors.Leakage current when microprocessor is in complete static state with other integrated circuit may be too big, and can not realize long battery life or can not satisfy the energy management strategy.
The system design people must weigh operating power and leakage current when selecting the device of enforcement processor and other system assembly.For low operating power, require low supply voltage, and then require logical circuit that low threshold voltage is arranged.But low threshold logic cirtuic produces high leakage current when device remains static.
For avoiding high leakage current, the electron device to computer system cuts off the power supply possibly.But, when outage, will lose the state of microprocessor and other integrated circuit.In some cases, before outage, can use software to extract and store this state, yet for controller on every side, as LAN controller and storage controller, the state of integrated circuit usually can not visit from operating system software.This makes can not store the state or the configuration of hardware down, requires hardware also to keep power supply under static state, or requires operating system shutdown system and back to restart it.
Therefore, need provide a kind of state to end and recover the method for operating and the equipment of computer system, make, not need to reboot computer system and come recovery operation the computer system component outage by storage computation machine system component.
Summary of the invention
State by storage computation machine system component makes to computer system component outage end and the purpose of recovering computer system realizes with the method for operating and the system of the computer system of the internal register state of one or more assemblies in termination and the recovery storage computation machine system.Use the latch in the scanning computer system component to read state.Scan register can be through the internal scan chain inter access, or by using serial test port interface or boundary scan interface external reference.Then with state storage in nonvolatile memory, and computer system component cut off the power supply.One receives restoring signal, recovers computer system power supply is read the state of storage from nonvolatile memory, and state is write back to computer system component.Through scan chain state inside is write back, or use serial test port interface or boundary scan interface that the state outside is write back.The execution of computer system recovers with the computer system component under the state of earlier stored then.
Become obvious in the concrete below written explanation of above-mentioned and other purpose, feature and advantage of the present invention.
Description of drawings
Novel characteristics of the present invention, believable characteristic propose in appended claim.But the present invention self, optimal way, its further purpose and the advantage used be when reading in conjunction with the accompanying drawings, by reference back specifying better of illustrated embodiment understood, in the accompanying drawing identical reference number represent identical assembly and:
Figure 1A is a block diagram of having implemented the computer system component of a preferred embodiment of the present invention;
Figure 1B is the sketch of scan register of the computer system component of Figure 1A;
Fig. 2 is the block diagram of computer system according to a preferred embodiment of the invention;
Fig. 3 is a process flow diagram of describing the operation of operating system according to a preferred embodiment of the invention;
Fig. 4 is a process flow diagram of describing the operation of power control logic circuit according to a preferred embodiment of the invention;
Fig. 5 is the block diagram of computer system according to another embodiment of the present invention;
Embodiment
With reference to the accompanying drawings, and, described the block diagram of the computer system component 10 of having implemented a preferred embodiment of the present invention especially with reference to Figure 1A.Computer system component 10 can be processor core core, computer system application-specific IC (ASIC) or peripheral assembly controller.System component 10 comprises function logic block 11A, 11B and the 11C that carries out function according to the operation of computer system.Provide level-sensitive scan design (LSSD) scan chain 12 to read and write-in functions logical block 11A the state of the internal register in 11B and the 11C.LSSD scan chain 12 provides usually and is used for test and checking purpose.Visit permission execution before being used for computer system of all states in the system component 10 being kept element is provided with checking and production line test.The scan chain architecture that can use with technology of the present invention is the U.S. Patent No. 5 of " VLSITest Circuit Apparatus and Method " at exercise question, 920, describe in 575, this patent is incorporated herein and is reference, but can use other boundary scans and test port circuit and topological structure under the situation that does not deviate from the spirit and scope of the present invention.
Except that LSSD scan chain 12, integrated JTAG (JTAG) interface 13 in system component 10.Jtag interface 13 provides and connects 15, the internal register through this connects the addressable system component 10 of 15 external testing machines in, and the common in order that purpose of test system components 10, and allow the state of nearly all internal register to be read out or to write.The details of jtag interface 13 is by IEEE (institute of electrical and electronic engineers) standard 1149.1-IEEE, 1994 complementary definitions of standard test access port and boundary-scan architecture and 1149.1 specifications.Used interface is not limited to JTAG type interface, and using the JTAG hardware layer and can providing the compatibility with current common spendable testing apparatus with JTAG standard interface compatible protocols basically is very easily.
The present invention uses in a novel way from function logic block 11A, 11B, the status information of 11C, the state of storage system assembly 10 and returning to form before recovery operation before the operation of computer system is ended.Reading and write status information there can visit by multitude of different ways from LSSD scan chain 12.LSSD scan chain 12 can through particular command by jtag interface 13 or through boundary scan interface 14 by system component 10 being positioned in the scan pattern and directly accessed in system component 10.Order through providing from jtag interface 13 or be connected to form parts through the external pin of boundary scan interface 14 and can start and finish scan pattern.
The LSSD structure is favourable implementing technical elements of the present invention, because it provides the visit to the state of all internal lock storages.In addition, but LSSD structure Already in the LSSD Test Design, so the present invention's circuit design technique of not looking for novelty or to the modification of the circuit of the assembling LSSD scan chain that designed.Other method is called " magnetic bubble scanning ", and each LSSD latch is added another low leak condition memory device, and this state storage device is used for the state that during low power intervals (as suspending mode) keeps latch.Compare with the present invention, must be to comprising the assembly holding power of state storage latch.In addition, " magnetic bubble scanning " method requires to realize novel circuit design and bigger circuit area.Semiconductor is manufactured on repeated use aspect, circuit storehouse has investment and total system design to make up standard LSSD structure at present.The present invention can support these investments by existing structure being added simple control logic circuit and Control Software.
With reference now to Figure 1B,, the structure of the scanning element in the LSSD scan chain 12 of Figure 1A has been described.Register 16 has system data input 18, is used for from function logic block 11A, and 11B, 11C loads logical value, and system data output 17, is used to be provided with function logic block 11A, the logical value in the 11B, 11C.Register 16 chainings connected in series have a scan-data input, are used for loading logical value on the top of each chain, and have a scan-data output in the end of each chain.But chain input and output inter access, and can be through boundary scan interface 14 and jtag interface 15 visits.Scan clock provides the control that the data in the LSSD scan chain 12 are moved, and system clock provides high frequency clock to be used for the conventional system operation.
With reference to figure 2, expression computer system according to a preferred embodiment of the invention.Computer system nuclear core 20 is large-scale chunks of computer system.The external device (ED) 42 that joins through bus 43 is finished the funtion part of computer system.External device (ED) comprises storer, memory storage, graphics device, artificial input media etc.The nonvolatile memory 40 that is positioned at computer system nuclear core 20 outsides is used for storaging state information, is used to end/recover function of the present invention.The controllable electric power that comprises nmos pass transistor 41 is also included within the computer system, is used to control the basic power supply to the chunk in the computer system nuclear core 20.For offering power control logic circuit 24 and being provided for for the standby power supply of other computer system components that can not be cut off the power supply fully, the low current standby power supply connects 44 provides reserved state information in the part of computer system nuclear core 20.
In the computer system nuclear core 20, processor core core 21 provides the execution and the data value control of programmed instruction.Integrated peripheral assembly 23 provides computer system functions as serial port, direct memory visit (DMA) controller etc.External bus interface 29 provides the bus 43 that is connected in external device (ED) 42 through I/O piece 45.Processor core core 21, I/O piece 45, integrated peripheral assembly 23 and external bus interface 29 all comprise the LSSD scan chain register.Scan-data output 32 from each chain is connected to scanning multiplexer 27, to allow to choose each scan chain output 34 of power processor controls 24.Power control logic circuit 24 can come reading scan chain register by obtaining with transferring status data from the piece that comprises scan chain through multiplexer controling signal 33 selection scan chains and through 38 controls of control bus interface.In case power control logic circuit 24 is by the state of reading scan chain search to computer system nuclear core 20, with data storage in non-volatile internal storage 26, this storer can be implemented through standby power supply 44 power supplies or with a kind of technology of keeping its state of powering that do not require, as the erasable ROM (read-only memory) of removing.If at first status information was sent to non-volatile external memory storage 40 before controllable electric power 24 stops 20 power supplies of computer system nuclear core, non-volatile internal storage 26 also can be powered by the mainframe computer system nuclear core power supply that provides through controllable electric power 41.Before controllable electric power 41 outages, I/O piece 45 can be mounted with suitable value.If some external device (ED)s 42 are not de-energized, then this will be necessary.Must control the outside connection status that computer system is examined core 20, be placed under the high-leakage state, produce wrong bus cycle or cause damage potentially external device (ED) 42 to avoid an external device (ED) 42.
Power control logic circuit 24 can be processor or hardwire logic piece, begins the pause sequence of computer system nuclear core 20 by the order that receives from processor nuclear core 21 through control bus interface 38.Perhaps, can implement to be used to generate other schemes of abort request, as be coupling in the single control line between power control logic circuit 24 and the processor core core 21.Power control logic circuit 24 can be by the clock of control clock control 22 abort process devices nuclear core 21 and integrated peripheral assembly 23.This freezes the operation of the computer system nuclear core except that power control logic circuit 24 and associated component.From various reading scan chain data and it is stored in the non-volatile internal storage 26 then.Then, power control logic circuit 24 can be removed primary power from computer system nuclear core 20 through controllable electric power 41.
In the sequence of termination or close event, non-volatile internal storage 26 or non-volatile external memory storage 40 selectively are used to provide the energy-conservation of different stage.For example, (it can be the very long time cycle for the beginning of hang up part, according to leakage value can be some months), hold mode and keep computer system nuclear core 20 needed certain other source current of level in non-volatile internal storage 26 preferably.After the time cycle of determining through the timer in the power control logic circuit 24 46 that has disappeared, by state that writes computer system nuclear core 20 to non-volatile external memory storage 40 and the power supply of removing computer system nuclear core 20 fully, can start more senior energy-conservation.If power control logic circuit comprises a microprocessor, perhaps examine the piece of the outside of the power control logic circuit 24 in the core 20 as computer system, perhaps cause power control logic circuit 24 log-on datas other appropriate configuration, then also available programs instruction enforcement of timer 46 to the transmission of non-volatile external memory storage 40.A plurality of transistors in the programmable power supply 41 are connected in computer system nuclear core 20 with a plurality of power supplys, can be used for finishing the energy-conservation of different stage, perhaps can be because disconnection is energy-conservation to the clock control 22 of the clock of home block.Error checking and correction (ECC) piece 30 can provide the more storage and the retrieval status information of high reliability, and coding perhaps capable of being combined or compression reduce storage and required energy and time of retrieval status information.Error checking and correction (ECC) is necessary in given structure, because some Nonvolatile memory devices have finite population to write circulation before inefficacy.
The use of non-volatile internal storage 26 and non-volatile external memory storage 40 is for the system customization of implementing.For example, if computer system nuclear core 20 is used for the system that the most of the time is in abort state, then specially with non-volatile external memory storage 40.But, if not normal activation system continually, then specially with non-volatile internal storage 26.For using two types the system of nonvolatile memory, data are the function of the power requirement condition of 26 pairs of non-volatile external memory storages 40 of non-volatile internal storage from non-volatile internal storage 26 to the timing that non-volatile external memory storage 40 transmits.
The control that resets 25 is received power control logic circuit 24, resets and/or recovers to send signal to provide.In case send restoring signal, the power processor controls is recovered primary power by starting controllable electric power 41, and from non-volatile internal storage 26 or non-volatile external memory storage 40 retrieval status.Through scan chain input 31 status information is write various functional blocks.Select specific scan chain input to come to receive scan-data output 35 by scanning demultiplexer 28 from power control logic circuit 24.For this purpose, provide scanning demultiplexer 36.Control bus interface 38 is used for the loading of state of a control data to processor core core 21, integrated peripheral assembly 23 and external bus interface 29.In case status data has loaded, clock control 22 can be issued signal, to restart to the clock of processor core core 21 and integrated peripheral assembly 23.
The ability of state that can read and write the internal lock storage of computer system nuclear core 20 makes may store and retrieve this information.Although originally providing is for test purpose, but make it require to use LSSD scanning string and LSSD scan latch to retrieve and return to form to the needs of the energy management of complexity.This will make that computer system is placed on can be to required time minimization in the state of primary clustering outage, also the duty of minimizing recovery computer system (for example, do not guide or reconfigure system after the outage again) required correlation time, and closing the complete reorganization of prerequisite for machine state.Past must be restarted the computer system order fully after to processor and peripheral assembly outage.Because can not be fully visiting in the software, machine state obtains.The present invention makes it may directly recover the state of machine through scan interface.Operating system only needs to refresh or store the memory array that can not scan except that the state of memory module integrated circuit, as cache memory and compiling look-aside buffer etc.After the memory image that can not scan is resumed, the assembly integrated circuit is restored electricity, and recover the state of storage through scan interface.
Complete state storage for example of the present invention and recovery begin the dish visit in particular memory device, but do not finish the search to particular sector.Disk controller keep order and etc. in to be searched the finishing, system does not change the state (mandatum cassatorium) of machine and then can not close.And by the storage device drive management, this driver does not provide down interface to the operating system of the sequence that outage/energising in an orderly manner is provided to the interface of memory storage usually.
Improvement of the present invention also is applied to the network interface operation.Network interface can have the information that writes configuration protocol, IP address etc., and this information is kept by device driver or the application program moved in computer system.For to network interface outage, and restore electricity subsequently, when recovering, all-network, the state of interface must recover.The network equipment driver can not be read and write state fully, this feasible application program that must restart device driver or supervising the network interface.
With reference now to Fig. 3,, expresses the process flow diagram of operation of the operating system of the preferred embodiment of describing the method according to this invention.When receiving the System Halt request (determining 61) of user button or software command triggering, scheduler (task time segment management device or preference manager) stops scheduler task and distribution is executed the task, and can not handle and interrupt (step 63).This moment, execution is single threading (single-threaded) and can not interrupts.Then, any cache memory and compiling look-aside buffer (TLBs) are flushed in the external memory storage.This storer can be the storer of still powering, or a magnetic hard-disk file.After refreshing cache memory, provide signal to come shutdown system (step 65) to power control logic circuit 24.Operating system all stopped before clock stops then, and the assembly outage (step 66) to cutting off the power supply.Power control logic circuit 24 is responsible for the states of the assembly of storage outage, and returns to form before recovery operation, restores electricity and recovers machine state again during applied clock with box lunch.Operating system is to remove abort request then, and the recovering state before ending is operated (step 67).
With reference to figure 4, express the process flow diagram of operation of the power control logic piece (as the power control logic circuit 24 of Fig. 2) of the preferred embodiment of describing the method according to this invention.When not receiving turn-off request (determining 70), power control logic circuit 24 keeps idle state or carries out other tasks (step 71).When receiving turn-off request, power control logic circuit 24 halt system clocks (step 72).Then, read state (step 73) through the scanning port in integrated circuit from the system and device that comprises processor.The state of all devices is sent to nonvolatile memory (step 74), and scan clock stops.And to 20 outages (step 75) of computer system nuclear core.Power control logic circuit 24 enters idle state (step 76) then, recovers indication up to receiving from user button, timer or other mechanisms that posts a letter.When the recovery indication receives (determining 77), recovery is powered to system and device, and scan clock restarts (step 78), reads the state (step 79) of earlier stored from nonvolatile memory, through scanning port state is written to system and device (step 80).Then, recovery system clock (step 81) allows operation to recover to carry out from stopping place.
With reference to figure 5, computer system is according to another embodiment of the invention described.In these embodiments, assembly has test interface and/or boundary scan interface, but specific customization is not come inner assembled state storer and recovered the present invention.Test interface and/or boundary scan interface are used for the outside provides a kind of mechanism that can read state therefrom or state is written to assembly.Central computer unit 100 is connected in and is used for stored program instruction and memory of data 110 and peripheral unit 111.Peripheral unit 111 can comprise Video Controller, network interface, input media, printer interface, memory device interface, and other provide the device for the useful connection of central computer unit 100.The state of peripheral unit 111 also can connect 114 storages through JTAG, connects 112 to close/to restart processor controls 113 or boundary scan.Because JTAG and boundary scan are realized spreading in the large scale circuit of present use.A lot of existing peripheral unit assemblies can not join by the mode of describing among Fig. 5 with making an amendment.
Central computer unit 100 comprises processor 101 that is used for execution of program instructions and the cache memory 102 that is used to keep the instruction and data value.According to the integrated art of the high density of using in the current integrated circuit, central computer unit 100 also comprises peripheral and system's supporting assembly, to implement most of computer system.The Memory Controller 105, direct memory visit (DMA) controller 104 and the bus bridge 103 that are used for the memory sub-system of supervisory computer provide system's support, are used for transmitting from central computer unit 100 diode-capacitor storages and I/O.UART106 provides serial communication, and network interface 107 provides the network service between central computer unit 100 and the device that is connected.
Except that the functional block relevant with computer system operation, JTAG (JTAG) interface 108 is integrated in the central computer unit 100.Jtag interface 108 provides port, by the internal register in the addressable central computer unit 100 of this port external testing machine, usually for use or be installed in computer system before the purpose of test central computer unit integrated circuit, allow the state of nearly all internal lock storage to be read out or to write.The interface that uses is not limited to JTAG type interface, and using the JTAG hardware layer and can providing the compatibility with current normally used testing apparatus with JTAG standard interface compatible protocols basically is very easily.
In the computer system of Fig. 5, jtag interface 108 connects 114 through JTAG and is connected in power control logic circuit 113, this circuit can be processor or hardwire logic piece, is provided for the mechanism of power control logic circuit 113, reads or write the state of central computer unit 100.Embodiment according to first change of the present invention, the specific command sequence of sending to jtag interface 108 by power control logic circuit 113, before closing, store the state of central computer unit 100 and before restarting, recover this state, make the operation of computer system in closing routine, to freeze, for recovery operation does not but need booting computer system again.
The embodiment of second change of the present invention can implement in the computer system of Fig. 5.Except that JTAG connects 114, power control logic circuit 113 connects 112 through boundary scan and is connected in central computer unit 100.When starting certain test modes when the external pin on central computer unit 100 or by the particular command that jtag interface 108 sends, central computer unit 100 can be placed on " scanning " pattern, and wherein the part (subset) of the connection of the pin on the central computer unit 100 becomes the boundary scan testing pin.Connect 112 by boundary scan, the state of central computer unit 100 can be read sooner, and these data can be read through jtag interface 108, and are more complicated but cost is a circuit.
Except that it is unified the termination/recovery mechanism of PDA(Personal Digital Assistant) as department of computer science, the present invention also is used for server and assembled redundant component or caused online assembly by " needs ", provides " Hot Spare " performance as other critical computer systems of LAN switch or modulator-demodular unit group.In system initialization, the state of the assembly of " Hot Spare " is initialized to the state that needs, and then this state is read in the nonvolatile memory, and assembly is cut off the power supply.When needs " Hot Spare ", restore electricity and state is write back in the assembly of " Hot Spare "." Hot Spare " that be initialised to the state that needs can use in computer system then.
Although the present invention is described with reference to specific embodiment, this explanation and not meaning that is constructed on limited significance.With reference to description of the invention, various modifications of the disclosed embodiments and additional embodiments of the present invention are conspicuous for those of ordinary skill in the art.Therefore in the spirit and scope of the present invention that do not deviate from the appended claim qualification, can carry out these modifications.
Claims (32)
1. method of operating of ending and recovering computer system, described method comprises:
In response to receive ending indication, scan the state of the internal register of described computer system inner assembly integrated circuit, read corresponding to data from the described state of scan register;
The described state of storage in nonvolatile memory; With
To described assembly integrated circuit outage.
2. according to the method for claim 1, also comprise step:
In response to recovering the power supply of indication recovery to described assembly integrated circuit;
Read described state from described nonvolatile memory; With
By recovering described state in the described assembly integrated circuit write described scan register corresponding to the data of described state.
3. according to the method for claim 2, also comprise:
Before the described state of storage, stop clock signal of system in the described assembly integrated circuit; With
After described assembly integrated circuit is restored electricity, start the clock signal of system in the described assembly integrated circuit.
4. according to the method for claim 2, wherein said non volatile memory bits is in described assembly integrated circuit, and the wherein said described state of storage moves corresponding to described state in described assembly integrated circuit in described nonvolatile memory data and the described state of wherein said recovery recover described state from described assembly integrated circuit.
5. according to the method for claim 4, wherein said nonvolatile memory comprise the random access memory that is coupled in standby power supply and wherein said to described assembly integrated circuit outage to described nonvolatile memory outage.
6. according to the method for claim 5, also comprise:
Behind the described state of scanning, wait for a schedule time,
In response to through the described schedule time, the state of described scanning is sent to second nonvolatile memory of described assembly integrated circuit outside.
7. according to the method for claim 4, wherein said nonvolatile memory be erasable remove ROM (read-only memory) and wherein store described state described state is write described erasable except that ROM (read-only memory).
8. according to the method for claim 2, wherein said nonvolatile memory is in described assembly integrated circuit outside, and wherein said storage and the reading step interface between described internal register and described external memory storage transmits described state.
9. according to the method for claim 2, also comprise:
Receiving described termination indication back schedule time of wait, store described condition responsive in carrying out through the described schedule time.
10. according to the method for claim 2, the described state of wherein said scanning is read described state through serial test port interface.
11. according to the method for claim 2, the described state of wherein said scanning is read described state through boundary scan register, described method also comprises in response to receiving described termination indication described assembly integrated circuit is placed in the scan pattern.
12. method according to claim 2, wherein said computer system comprises activation and the stand-by unit that is coupled in common bus, wherein said assembly integrated circuit is positioned at described stand-by unit, the described state of wherein said scanning, the described state of storage and outage are carried out when system initialization, and the described step that restores electricity, reads described state and recover described state activates in response to the described stand-by unit of indication and carries out.
13. a computer system comprises:
The assembly integrated circuit, having can be through the internal function register of scan register visit;
Be coupled in the nonvolatile memory of described assembly integrated circuit, be used in response to the state of ending the described assembly integrated circuit of indication storage, wherein said state is read from described assembly integrated circuit through described scan register;
Be coupled in the controllable electric power of described assembly integrated circuit, be used for when described assembly integrated circuit operation described assembly integrated circuit power supply, and be used for described state storage in the back outage of described nonvolatile memory.
14. according to the computer system of claim 13, also comprise clock control circuit, be used for gate disconnection (gate off) clock signal of system in described assembly integrated circuit, so that freeze described status condition.
15. according to the computer system of claim 13, wherein said non volatile memory bits is in described assembly integrated circuit.
16. computer system according to claim 15, wherein said nonvolatile memory comprises the random access memory that is coupled in standby power supply, and wherein after described controllable electric power was to described assembly integrated circuit outage, described standby power supply recovered described random access memory power supply.
17. the computer system according to claim 13 also comprises
Be coupled in second nonvolatile memory that is used to store described state of described assembly integrated circuit; With
Timer is used to determine when through the schedule time with wherein before described controllable electric power is to the outage of described assembly integrated circuit, and described state is write described second nonvolatile memory.
18. according to the computer system of claim 13, wherein said nonvolatile memory is the erasable ROM (read-only memory) of removing.
19. computer system according to claim 13, wherein said nonvolatile memory is in described assembly integrated circuit outside, wherein said computer system also is included in the interface between described internal register and the described external memory storage, and wherein said state transmits through described interface.
20. according to the computer system of claim 19, wherein said interface is a serial test port interface.
21. according to the computer system of claim 20, wherein said serial test port interface comprises the test port according to JTAG (JTAG) specification, and wherein said state is transmitted by sending specific JTAG order.
22. according to the computer system of claim 13, wherein said assembly integrated circuit comprises that boundary scan register and wherein said state read by described assembly integrated circuit is put in the scan pattern.
23. the computer system according to claim 13 also comprises:
Bus is used for coupling and handles and peripheral assembly;
Be coupled in the activation component of described bus; With
Spare module comprises described assembly integrated circuit, is coupled in described bus and wherein said state and is stored in when system initialization in the described nonvolatile memory, activates the described state of retrieving in response to the described stand-by unit of indication.
24. the computer system according to claim 13 also comprises:
The power control logic processor is used to read the state of described assembly integrated circuit.
25. according to the computer system of claim 24, wherein said power control logic processor is controlled described controllable electric power and is controlled power supply to described assembly integrated circuit.
26. the computer system according to claim 24 also comprises:
Be coupled in the clock control circuit of described power control logic circuit, be used in response to the described processor gate parting system clock signal in described assembly integrated circuit of closing.
27. computer system according to claim 24, the wherein said processor of cutting out is positioned at described assembly integrated circuit, be coupled in another power supply with wherein said power control logic circuit, so that when described controllable electric power cuts off the power supply to described assembly integrated circuit, described power control logic circuit is kept power supply.
28. an assembly integrated circuit that uses in computer system comprises:
Can be through the internal register of scan register visit; With
Internal non-volatile memory is used in response to the state of ending the described internal register of indication storage.
29. according to the assembly integrated circuit of claim 28, wherein said internal non-volatile memory comprises the erasable ROM (read-only memory) of removing.
30. according to the assembly integrated circuit of claim 28, wherein said nonvolatile memory comprises the random access memory that is coupled in the standby power supply input, is used for from primary power pin outage back described random access memory being powered.
31. according to the assembly integrated circuit of claim 28, in described assembly integrated circuit, also comprise power control logic circuit, be used for described state is sent to described nonvolatile memory.
32. the assembly integrated circuit according to claim 28 also comprises the clock control logic circuit, is used for after storing described state the functional logic circuit gate being disconnected clock signal.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
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| US67694300A | 2000-10-02 | 2000-10-02 | |
| US09/676943 | 2000-10-02 |
Publications (2)
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| CN1344982A true CN1344982A (en) | 2002-04-17 |
| CN1218232C CN1218232C (en) | 2005-09-07 |
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| CN011410388A Expired - Fee Related CN1218232C (en) | 2000-10-02 | 2001-09-29 | Method and apparatus for suspension and recovery of computer system operation |
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| JP (1) | JP2002182803A (en) |
| KR (1) | KR20020026814A (en) |
| CN (1) | CN1218232C (en) |
| TW (1) | TW544585B (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100426269C (en) * | 2005-04-18 | 2008-10-15 | 纬创资通股份有限公司 | Method for controlling axiliary device in status of electrically connecting computer system with axiliary device |
| CN103777537A (en) * | 2014-01-28 | 2014-05-07 | 无锡云动科技发展有限公司 | Low-power-consumption control circuit and storage device |
| CN109154907A (en) * | 2016-05-27 | 2019-01-04 | 超威半导体公司 | Virtual address is executed to physical address translation using multiple memory components in input-output memory administrative unit |
| CN116400795A (en) * | 2023-06-09 | 2023-07-07 | 上海芯联芯智能科技有限公司 | Power gating method and system-on-chip |
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| JP3910902B2 (en) | 2002-10-02 | 2007-04-25 | 松下電器産業株式会社 | Integrated circuit device |
| US7451333B2 (en) * | 2004-09-03 | 2008-11-11 | Intel Corporation | Coordinating idle state transitions in multi-core processors |
| JP4724461B2 (en) * | 2005-05-17 | 2011-07-13 | Ｏｋｉセミコンダクタ株式会社 | System LSI |
| US7574591B2 (en) | 2006-01-12 | 2009-08-11 | Microsoft Corporation | Capturing and restoring application state after unexpected application shutdown |
| US7716461B2 (en) * | 2006-01-12 | 2010-05-11 | Microsoft Corporation | Capturing and restoring application state after unexpected application shutdown |
| TWI398755B (en) * | 2006-12-22 | 2013-06-11 | Hon Hai Prec Ind Co Ltd | Method for restoring an embedded system |
| US9329919B2 (en) | 2008-07-16 | 2016-05-03 | Freescale Semiconductor, Inc. | Micro controller unit including an error indicator module |
| TWI482033B (en) * | 2009-01-23 | 2015-04-21 | Wistron Corp | Method for arranging schedules and computer using the same |
| JP5452041B2 (en) * | 2009-03-13 | 2014-03-26 | ローム株式会社 | Data processing device |
| US9135988B2 (en) | 2011-09-09 | 2015-09-15 | Nec Corporation | Semiconductor device and control method of the same |
| JP5999097B2 (en) * | 2011-11-21 | 2016-09-28 | 日本電気株式会社 | Semiconductor integrated circuit and control method thereof |
| JP6252799B2 (en) | 2013-03-25 | 2017-12-27 | 日本電気株式会社 | Arithmetic processing device and control method thereof |
| JP5974133B1 (en) * | 2015-03-20 | 2016-08-23 | 株式会社東芝 | Memory system |
| WO2017009982A1 (en) * | 2015-07-15 | 2017-01-19 | 株式会社東芝 | Electronic circuit board and information processing apparatus |
| US11295792B2 (en) * | 2019-09-30 | 2022-04-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Back-up and restoration of register data |
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| JPH01279312A (en) * | 1988-04-30 | 1989-11-09 | Toshiba Corp | Computer system |
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| IT1250562B (en) * | 1991-12-30 | 1995-04-20 | Prima Ind Spa | PRECISION BENDING PRESS FOR RELATIVELY SHORT SHEET PIECES. |
| KR0172003B1 (en) * | 1995-03-28 | 1999-03-30 | 김광호 | Computer system and its control method |
| KR0130711B1 (en) * | 1995-08-01 | 1998-04-10 | 이승춘 | Baggage carrying device |
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2001
- 2001-09-24 KR KR1020010058930A patent/KR20020026814A/en not_active Application Discontinuation
- 2001-09-26 TW TW090123778A patent/TW544585B/en not_active IP Right Cessation
- 2001-09-28 JP JP2001301550A patent/JP2002182803A/en active Pending
- 2001-09-29 CN CN011410388A patent/CN1218232C/en not_active Expired - Fee Related
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100426269C (en) * | 2005-04-18 | 2008-10-15 | 纬创资通股份有限公司 | Method for controlling axiliary device in status of electrically connecting computer system with axiliary device |
| CN103777537A (en) * | 2014-01-28 | 2014-05-07 | 无锡云动科技发展有限公司 | Low-power-consumption control circuit and storage device |
| CN103777537B (en) * | 2014-01-28 | 2018-03-13 | 无锡云动科技发展有限公司 | A kind of low power consumpting controling circuit and storage device |
| CN109154907A (en) * | 2016-05-27 | 2019-01-04 | 超威半导体公司 | Virtual address is executed to physical address translation using multiple memory components in input-output memory administrative unit |
| CN109154907B (en) * | 2016-05-27 | 2023-09-15 | 超威半导体公司 | Virtual address to physical address translation using multiple memory elements in an input-output memory management unit |
| CN116400795A (en) * | 2023-06-09 | 2023-07-07 | 上海芯联芯智能科技有限公司 | Power gating method and system-on-chip |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1218232C (en) | 2005-09-07 |
| KR20020026814A (en) | 2002-04-12 |
| JP2002182803A (en) | 2002-06-28 |
| TW544585B (en) | 2003-08-01 |
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