In traditional broadband data access circuit of Fig. 1, the input of signal and transmission all are to realize by two ports of loop.Input signal passes through by R1 R2.R3 by the inductance coupling high of loop, R4, R5, R6 is behind the balancing network that Zi constitutes, insert respectively by resistance R 9, the receiver B that R10 and operational amplifier are formed reaches by resistance R 11, the receiver A that R12 and operational amplifier are formed, and signal constitutes the fully differential pattern herein, its common-mode voltage is predefined value, and the purpose of She Zhiing is to make things convenient for the direct coupling of late-class circuit like this.
After the anti-mixed repeatedly filtering that the analog input signal process low noise input of fully differential and the amplitude adjustment of automatic gain level and filter are 2 grades, be converted into digital signal by the analog to digital converter level and deliver to DSP, DSP will be through the processing opposite with modulation, as IFFT, deinterleave etc., signal is reverted to original transmission data.
Equally, the data that send will be passed through the modulation of DSP earlier, as FFT, interweave etc., send it to digital to analog converter then and be converted to the analog signal of fully differential, analog signal will be through the smothing filtering of 1 grade in filter, with the target signal filter beyond the communication band, puts the access interface circuit in advance through the power amplification output stage then.
At node transmitA and transmitB, the transmission signal of fully differential will pass through AC coupled, the reason of not carrying out direct-current coupling is the working point by the common-mode voltage decision of fully differential signal, with the working point of cable driver is different, carries out the direct-current coupling meeting and causes big direct current and power consumption.
The transmission signal of fully differential is through by R7, R8 and line driverA and R13, and the power DC coupling of R14 and line driver B, after the adjustment, by by R1, R2, R3, R4, R5, R6, the balancing network that Zi constitutes utilizes inductance coupling high to send to the port of loop.
The problem that passband leaks and frequency band changes that Fig. 2~traditional place in circuit shown in Figure 4 exists is as indicated above, repeats no more herein.
Broadband data access circuit of the present invention shown in Figure 6 comprises: input and output coupling and hybrid network 31; The receiving loop that constitutes by low noise amplifier B2, type step gain controller circuit B3, filter B4 and analog to digital converter B5; The transmission loop that constitutes by digital to analog converter B18, filter B17, stepping attenuation control circuit B16 and power amplifier B15; DSP circuit B19, its digital signal output end mouth, digital signal input end mouth connect the corresponding port of described digital to analog converter B18 and analog to digital converter B5 respectively; Wherein filter 34 and filter B17 are tunable optic filter.
It also comprises: a control data registers group B8 who receives the various control data of DSP circuit B19 output, be connected voltage mode digital to analog converter B11 between its filter parameter register 2 and the tuning input of described filter B4, be connected voltage mode digital to analog converter B14 between its filter parameter register 4 and the tuning input of described filter B17, its gain controlling register 1 output connects described type step gain controller circuit 33 control ends, and its decay control register 3 outputs connect described stepping attenuation control circuit B16 control end;
An output connects the Echo Cancellation network B 6 of described low noise operational amplifier B2 input; And a stepping attenuation control circuit B7 who adjusts described Echo Cancellation network B 6 input signal amplitudes, its two input connects the output of the control register 5 of described filter B17 output and control register group B8 respectively.
Above-mentioned voltage mode digital to analog converter B11, B14 all can be made of current-voltage converter and current-mode digital to analog converter, and the latter's output connects the former input.As shown in Figure 7, current-voltage converter B10 and current-mode digital to analog converter B9 form voltage mode digital to analog converter B11, and current-voltage converter B13 and current-mode digital to analog converter B12 form voltage mode digital to analog converter B14.
The connection in the loop of testing oneself of circuit of the present invention as shown in Figure 7.B1, B6, B7 are placed off position, with B15 output and B2 input short circuit, buffer B8 control data 2 contents are set, system promptly enters the self-test state.
Data are from being converted to the analog signal of certain frequency domain DSP end is sent to B18 with the form of digital signal after, analog signal is handled through smoothing filter B17, amplitude to signal is controlled in B16 then, B15 adjusts the power of signal, the input that then signal is directly added B2, B3 adjusts to permissible accuracy with the amplitude of signal, and B4 is converted to the expression of digital signal after resisting mixed repeatedly filtering in B5.
DSP handles the signal of input, judges whether the parameter configuration of filter B4 is suitable, and new parameter configuration data is inserted control data 2 registers of B8, by the circuit of B9, B10 or B11, the parameter of filter is reset.After circulation several times, with the parameter configuration of filter B4 to the setting that requires.
After the transceiver of two place in circuit compositions is set up the cross-beta loop, system will carry out cross-beta according to following principle.
Local side sends cycle tests to user side, after user side is handled through DSP, the parameter configuration situation of local side signal transmission path filter is sent it back local side, and local side reconfigures the parameter of signal transmission path filter by DSP; User side sends cycle tests to local side, and after local side was handled through DSP, with the parameter configuration situation transmission meeting user side of user side signal transmission path filter, user side reconfigured the parameter of signal transmission path filter by DSP.
The flow chart that Fig. 8 adjusts for the channel self-adapting of circuit of the present invention.The self adaptation adjustment process of its channel is as described below.
At local side, its adjusting range to filter system is: the cut-off frequency of receiving low pass filter, the low side frequency of transmitting terminal high pass filter; At user side, its adjusting range to filter system is the low side frequency of receiving terminal high pass filter, the cut-off frequency of transmitting terminal low pass filter.
Because when the cut-off frequency of low pass filter is adjusted, with the adjustment to high pass filter be in the same way, when soon the cut-off frequency of low pass filter is heightened, similarly need the low side frequency of high pass filter is heightened, this is because in the manufacturing of integrated circuit, though the variation of the device parameters of chip chamber is at random, in same chip, by suitable layout, can be so that parameter change direction between similar device and variation size be basic identical.
System can utilize training sequence that the performance of channel is measured at initial phase.After initialization finished, each parameter of filter system was optimised for and makes the capacity of descending and up channel reach maximum or predetermined value.Because product to each producer, all to carry out initialization optimization, so, major vendor is provided with the scope of adjusting appropriately in product, the system that can make reaches best configuration on data communication rates, thereby makes that the product of each producer or same producer different batches can be compatible.
Because the adjustment of filter system is finished at initial phase, analysis by following implementation method, can see and utilize 1 to 8 training sequence can realize the configuration of parameter, in data communication phase, the setting of each parameter remains unchanged, so, can not handle formation pressure to the DSP of system; Simultaneously, the maximum duration of system initialization is 11.3 seconds, according to the speed of 4000frames/s, can finish in the time at 0.25--2ms the configuration of filter system, can not constitute obstruction to other initial work of system.
The performed task of each step is among Fig. 8:
S1: utilize the control signal of dsp chip inside, system is placed self-test state shown in Figure 7.
S2: the filter parameter to signal input path is checked, and is an internal register setting.
S3-1: the low band filter parameter is provided with, utilizes method adjustment such as traverse tree that parameter is set.
S3-2: the high band filter parameter is provided with, utilizes method adjustment such as traverse tree that parameter is set.
S4-1: whether the parameter setting of checking low band filter reaches system requirements.
S4-2: whether the parameter setting of checking the high band filter reaches system requirements.
S5: after the configuration of signal input path filters finishes, initially reply according to the foundation of ITU-T agreement.
S6: transceiver is placed the cross-beta state, the cycle tests that utilizes the other side to send, the filter parameter configuration of beginning test signal transmit path.
S7: the filter parameter to signal transmission path is checked, and is an internal register setting.
S8-1: the low band filter parameter is provided with, utilizes method adjustment such as traverse tree that parameter is set.
S8-2: the high band filter parameter is provided with, utilizes method adjustment such as traverse tree that parameter is set.
S9-1: whether the parameter setting of checking low band filter reaches system requirements.
S9-2: whether the parameter setting of checking the high band filter reaches system requirements.
S10: after the signal transmission path filter configuration finishes, carry out other initial configuration and test according to the ITU-T agreement.
S11: set up satisfactory communication channel, data communication services is provided.
Fig. 9 is provided with the parameter schematic diagram for utilizing the adjustment of traverse tree method.For any one channel, the adjustment of the traverse tree by as shown above can be with the parameter adjustment of filter to the optimum value in the error that requires.In eight training sequences, if in the interstage, the parameter of filter is adjusted to the right place, then can end training sequence in advance.
Last graph traversal tree is a kind of method of parameter adjustment, also can be by other algorithm, and as the intermediate value insertion, fixed step size insertion etc. is adjusted.
For a tunable filter, setting its cut-off frequency is fc since the deviation that manufacturing process etc. causes for+/-25%; When the tuning range of filter be+/-30% the time, deviation that can its cut-off frequency of full remuneration. the range of linearity control of setting thyrite is 1.0V, quiescent potential is Vop, and control voltage be changed to Vop+/-0.5V, can obtain the voltage controlled frequency deviation ratio and be
For 8 bit DAC, its resolution is 1/256, so after carrying out normalization, final deviation is
This resolution can satisfy the requirement of system fully.
The adjustment of above-described place in circuit and channel thereof all is on the tunable optic filter basis that is based upon in the circuit.The tuning of filter can be realized by adjustable resistance or tunable capacitor.In the fully differential network, in order to realize the equilibrium treatment of signal, designed adjustable resistance network shown in Figure 10, to improve the performance of filter system.
This filter system belongs to the R-MOSFET-C type, the function of its frequency tuning part can be achieved by the resistance that changes the metal-oxide-semiconductor active pull-up, can increase linearity realization low distortion filter function thereby adopt active metal-oxide-semiconductor to be operated in linear zone as variable resistor.The active mixing variable resistance circuit figure of filter is auspicious to see Figure 10, its active mixing variable resistor contains: the passive resistance of two equivalences and four identical MOS transistor M1~M4, resistance of the source series of MOS transistor M1, M3, another resistance of the source series of MOS transistor M2, M4, the grid of MOS transistor M1, M2 is an one control end, the grid of MOS transistor M3, M4 is its another control end, the equal ground connection of the drain electrode of four MOS transistor, the free end of two resistance is respectively two lead-out terminal.Mate fully at device, setover under the ideal conditionss such as independence is adjustable, the complete symmetry of input signal, this variable resistor has good linearty, although ideal conditions is difficult to reach, and, the major advantage of this network is the size that can regulate resistance.The size of its equivalent resistance is:
In above-mentioned broadband data access circuit, the filter B17 in the filter B4 of receiving loop and transmission loop is tunable optic filter, this tunable filter be axis of pitch with the operational amplifier, each input resistance and feedback resistance to symmetry all adopt active mixing variable resistor shown in Figure 10.
Figure 11 is a quadravalence Chebyshev tunable low pass filter principle sketch, and the primary structure of circuit and traditional circuit are roughly the same.Comprising: Chebyshev (Chebyshev) filter and a reference source squelch circuit with two inputs, all symmetrical feedback resistances, input resistance all adopt active mixing variable resistor in the Chebyshev filter, and variable-resistance two control ends of described each active mixing all are connected to the corresponding output end of a reference source squelch circuit.
Resistance in low pass filter shown in Figure 11, electric capacity have following relation:
R1=R2=0.66R,?R4=R5=R,?R3=R6=0.5R, R7=R8=R,
R10=R11=0.5R,R9=R12=R,R14=R15=0.5R,?R13=R16=R,
R17=R18=R, C1=C2=C,?3=CA=1.411C, C5=C6=1.31C,
C7=C8=1.135C
Resistance R in the circuit diagram is made of passive resistance and active metal-oxide-semiconductor resistance two parts, the inverting input of one end of resistance R 1, R3, R4 and capacitor C 1 and fully differential amplifier A1 joins, and an end of resistance R 2, RS, R6 and capacitor C 2 and the in-phase input end of amplifier A1 join.The other end of resistance R 4, capacitor C 1 and an end of resistance R 7 are connected to the in-phase output end of fully differential amplifier A1 mutually, and the other end of resistance R 5, capacitor C 2 and an end of resistance R 8 are connected to the reversed-phase output of fully differential amplifier A1 mutually.One end of resistance R 7, capacitor C 3 and resistance R 9 is connected to the inverting input of amplifier A2 mutually, and the in-phase input end of resistance R 8, capacitor C 4 and resistance R 12 and fully differential amplifier A2 joins, and the in-phase output end of resistance R 10, R6 and capacitor C 3 and amplifier A2 joins.Resistance R 11, R3 and capacitor C 4 are joined with the reversed-phase output of transporting A2.The inverting input of resistance R 10, capacitor C 5 and resistance R 13 and amplifier A3 joins, the in-phase input end of resistance R 11, capacitor C 6 and resistance R 16 and amplifier A3 joins, the in-phase output end of resistance R 14, R12 and capacitor C 5 and amplifier A3 joins, and the reversed-phase output of resistance R 15, R9 and capacitor C 6 and amplifier A3 joins.Resistance R 14, capacitor C 7 and resistance R 17 are connected to the inverting input of amplifier A4 mutually, resistance R 15, capacitor C 8 and resistance R 18 are connected to the in-phase input end of amplifier A4 mutually, the other end of resistance R 17, capacitor C 7 and resistance R 16 are joined with the in-phase output end of transporting A4, and the other end of resistance R 18, capacitor C 8 and the reversed-phase output of amplifier A4 join.
In Figure 11, resistance value R comprise active metal-oxide-semiconductor resistance and passive electrical resistance two-part and, capacitance is: C1=C, C2=1.411C, C3=1.31C, CA=1.135C.Below our design center frequency be ripple in the 138KHz, 1dB passband, quadravalence Chebyshev low pass filter.
The quadravalence Chebyshev low-pass filter function that the interior ripple of passband is 1dB can be write as following form:
By the conversion equation:
Obtain normalized 1dB ripple, 4 rank Chebyshev low-pass filter function:
Wherein: ω
c=2 π f
c=2 * 3.14 * 138 * 10
3=866.64 * 10
3Radian per second
The designed 1dB ripple that obtains, centre frequency be 138KHz quadravalence Chebyshev low pass filter as shown in figure 10, resulting resistance, capacitance size as shown in drawings, this moment active metal-oxide-semiconductor control voltage be respectively: CTRL-V0=3.3V, CTRL-V1=2.6V.Change the size of active metal-oxide-semiconductor control voltage, can obtain passband ripple 1dB accordingly, centre frequency is the quadravalence Chebyshev low pass filter of 103.5KHz, 172.5KHz.
Another embodiment of tunable filter as shown in figure 12, it is three rank Butterworth tunable low pass filter, the primary structure of circuit is substantially with traditional circuit.It comprises: the Bart irrigates husband (Butterworth) filter, and can suppress a reference source squelch circuit of power-supply ripple, all symmetrical feedback resistances, input resistance all adopt active mixing variable resistor in the fertile husband's filter of Bart, and variable-resistance two control ends of described each active mixing all are connected to the corresponding output end of a reference source squelch circuit.
This three rank Butterworth low pass filter also belongs to the R-MOSFET-C type, and the function of its frequency tuning part can be achieved by the resistance that changes the metal-oxide-semiconductor active pull-up.The big I of active pull-up value obtains changing by the grid voltage that changes metal-oxide-semiconductor, when the control voltage of active metal-oxide-semiconductor is: when CTRL-V3=3.3V, CTRL-V2=2.6V, the centre frequency 1.104MHz of filter.When the control voltage of active metal-oxide-semiconductor is: when CTRL-V3=3.3V, CTRL-V2=2.1V, the centre frequency of filter is 621KHz.In three rank Butterworth low pass filters shown in Figure 11, resistance value R comprise active metal-oxide-semiconductor resistance value and passive electrical resistance two-part and, below we begin the three rank Butterworth low pass filters that design center frequency is 1.104MHz.
Three rank Butterworth low-pass filter function can be write as following form:
By the conversion equation:
Can obtain following transfer function
Wherein: ω
c=2 π f
c=2 * 3.14 * 1.104 * 10
6=6.93312 * 10
6The transfer function that radian per second is derived by filter system shown in Figure 12 is as follows:
Resistance in low pass filter shown in Figure 12, electric capacity have following relation:
R1=R2=R, R4=R5=R, R3=R6=2R, R7=R8=0.5R,
R10=R11=R, R9=R12=R,?R14=R13=R, C1=C2=C,
C3=CA=2C, C5=C6=C,
Resistance R in the circuit diagram is made of passive resistance and active metal-oxide-semiconductor resistance two parts, the inverting input of one end of resistance R 1, R3, R4 and capacitor C 1 and fully differential amplifier A1 joins, and an end of resistance R 2, R5, R6 and capacitor C 2 and the in-phase input end of fully differential amplifier join.The other end of resistance R 4, capacitor C 1 and an end of resistance R 7 are connected to the in-phase output end of fully differential amplifier A1 mutually, and the other end of resistance R 5, capacitor C 2 and an end of resistance R 8 are connected to the reversed-phase output of fully differential amplifier A1 mutually.One end of resistance R 7, capacitor C 3 and resistance R 9 is connected to the inverting input of amplifier A2 mutually, and the in-phase input end of resistance R 8, capacitor C 4 and resistance R 12 and fully differential amplifier A2 joins, and the in-phase output end of resistance R 10, R6 and capacitor C 3 and amplifier A2 joins.The reversed-phase output of resistance R 11, R3 and capacitor C A and amplifier A2 joins.The inverting input of resistance R 10, capacitor C 5 and resistance R 13 and amplifier A3 joins, the in-phase input end of resistance R 11, capacitor C 6 and resistance R 14 and amplifier A3 joins, the in-phase output end of resistance R 14, capacitor C 5 and resistance R 12 and amplifier A3 joins, and resistance R 14, capacitor C 6 and resistance R 9 are joined with the reversed-phase output that amplifier is put A3.
Above circuit is to be operated in ideally, in actual environment, has many factors need consider to improve the performance of whole system.When the power supply of power supply is not desirable direct voltage, there is bigger high frequency ripple to exist as power supply, then can greatly reduce the performance of filter system.
In the filter system circuit, because its cut-off frequency is subjected to the control of active metal-oxide-semiconductor resistance size, and active metal-oxide-semiconductor resistance size is subjected to the control of its grid voltage size, when supply voltage in the circuit has ripple to disturb, can make active metal-oxide-semiconductor grid voltage fluctuate, and then make active metal-oxide-semiconductor resistance value size change, filter frequencies is offset.
As shown in figure 13, when power supply ripple existed, the cut-off frequency of filter can be followed power supply ripple and be swung between Fc-delta and Fc+delta.
The amplitude of setting power supply ripple is 100mV, and range of linearity control is 1.0V, and then delta is 10%.The descending slope of filter is 48dB/ frequency multiplication (8 a rank filter), if be changed to linear, then at cut-off frequency Fc place, being changed to of signal amplitude
The signal resolution that is set in the Fc place is 31dB when the non-transformer ripple, i.e. 5bits (1bit=6dB).Then when having power supply ripple to exist, the signal resolution of the subchannel at Fc place is swung between 28.6dB and 33.4dB.According to above analysis, have two kinds of situations and take place.
(1) when the initial phase subchannel is defined as 5dB resolution, in the practical communication stage, can be because the bigger error rate takes place in the existence of power supply ripple
(2) when the initial phase subchannel is defined as 4dB resolution,, can reduce the speed of data communication in the practical communication stage.
In the worst case, DSP can handle the variation of channel in real time according to the size and the frequency of power supply ripple, like this, has just increased the weight of the DSP Processing tasks.
Below just discussed the problem that single channel takes place.In actual applications, setting Fc is 1MHz, and the frequency band that influenced by power supply ripple is
The bandwidth of setting subchannel is 2.5KHz, and then affected channel number is
Then when above-mentioned situation 2 took place, the data communication rates of system dropped to
Bit * SYMBOL transfer rate=160kbps that Δ T=Δ N* channel resolution reduces
Can see that from above analysis because the influence of power supply ripple, the absolute value that the message transmission rate of communication channel descends remains appreciable.
For fear of the appearance of this situation, in filter circuit, introduced a reference source squelch circuit, to improve the influence of mains voltage ripple to the filter frequencies skew.The reduction of data transfer rate causes mainly due to the tuned frequency variation of filter system, and the variation of filter tuner frequency is because the control voltage of adjustable resistance is subjected to the influence of power supply ripple.Therefore, substitute the power supply that adjustable resistance is controlled voltage generation circuit, head it off effectively with a reference source squelch circuit.
The embodiment of described a reference source squelch circuit as shown in figure 14.This circuit comprises: voltage follower, be used for metal-oxide-semiconductor transmission gate and squelch circuit that path is selected; Squelch circuit has the degenerative fully differential amplifier of common mode by one, two filter capacitors and the some resistance that are connected across fully differential amplifier input/output terminal constitute, voltage follower A2 and the metal-oxide-semiconductor transmission gate I13 of input termination harmonic ringing INP, the series arm that I6 constitutes is connected in the inverting input of fully differential amplifier A3, voltage follower A1 and the metal-oxide-semiconductor transmission gate I12 of input termination harmonic ringing INN, the series arm that I11 constitutes is connected in the in-phase input end of fully differential amplifier A3, the resistance R 6 of one termination harmonic ringing INP is connected to the in-phase input end of fully differential amplifier A3 by metal-oxide-semiconductor M8, the resistance R 5 of one termination harmonic ringing INN is connected to the inverting input of fully differential amplifier A3 by metal-oxide-semiconductor M7, be connected metal-oxide-semiconductor M4 and resistance R 4 series arms between the negative output terminal of fully differential amplifier A3 and the load resistance R2, be connected metal-oxide-semiconductor M3 and resistance R 3 series arms between the positive output end of fully differential amplifier A and the load resistance R1, metal-oxide-semiconductor M1, the equal cross-over connection of the series arm of M2 and common mode feedback circuit between two outputs of fully differential amplifier A3, metal-oxide-semiconductor M1, the common point of M2 connects an end of common mode feedback circuit.
The course of work of this circuit is as follows: in a reference source squelch circuit, at the input of INP, INN end two reference voltage 1.98V, 1.32V, if the INN end has added interchange interference signal AC1, added interference signal AC2 at INP end, wherein the AC1 signal by amplifier A1, capacitor C 1 and metal-oxide-semiconductor selector switch after and join the in-phase input end of fully differential amplifier A3 together by the AC2 signal that resistance R 6, metal-oxide-semiconductor M8 transmit.The AC2 signal by amplifier A2, capacitor C 2 and metal-oxide-semiconductor selector switch after and join the inverting input of fully differential amplifier A3 together by the signal AC1 that resistance R 5, metal-oxide-semiconductor M7 transmit.So after handling like this, just the same in the AC signal of the input of fully differential amplifier amplifier A3, thereby can utilize the common-mode rejection ratio of fully differential operational amplifier to remove as common-mode signal with exchanging interference signal.Obtain more stable active metal-oxide-semiconductor resistance grid control voltage at last at output OUT1, OUT2 place.