CN1335680A - Frequency discrimination signal treating method and frequency discriminator adopting simplified maximum likelihood frequency difference - Google Patents
Frequency discrimination signal treating method and frequency discriminator adopting simplified maximum likelihood frequency difference Download PDFInfo
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Abstract
The frequency discrimination signal treating method is a simplified one based on the maximum likelihood frequency difference estimating principle, and one frequency discriminator based on the simplified maximum likelihood frequency different is proposed. The frequency discriminator of the present invention has greatly simplified hardware structure compared with maximum likelihood frequency different one, and obviously improved performance and no obvious increase in hardware complexity compared with traditional cross product one. In phase lock loop capable of raising S/N ratio, the frequency discriminator may be well applied.
Description
The invention relates to an automatic frequency control technology, in particular to a simplified frequency discrimination signal processing method of maximum likelihood frequency difference and a frequency discriminator thereof, which are provided by simplifying a frequency difference estimation equation on the basis of a maximum likelihood frequency difference estimation principle and on the premise of a certain signal-to-noise ratio, and belong to the technical field of automatic frequency control in a digital communication system by taking MPSK (multiple phase shift keying) as a modulation technology.
In many wireless communication systems, a transmitting end and a receiving end respectively adopt clock sources with different accuracies, so that a certain frequency difference exists between the frequency of a received carrier signal and a locally synthesized carrier, and as various stages of frequency converters of a receiver are introduced into an actually demodulated signal, in a coherent demodulation process, if the frequency difference is not eliminated, errors occur in the received signal. A common method of eliminating this Frequency difference is to use an Automatic Frequency Control (AFC) technique. The automatic frequency control technology can be divided into open-loop automatic frequency control and closed-loop automatic frequency control, wherein the open-loop automatic frequency control directly estimates the frequency difference of a signal by using a frequency discriminator and directly corrects the frequency difference of the signal by using the estimated frequency difference; such open loop frequency difference control requires a high accuracy of the discriminator estimation. The closed-loop automatic frequency control is to utilize a frequency discriminator to feed back the frequency difference of an estimated signal to a voltage-controlled oscillator, and adjust the frequency difference of the output of the voltage-controlled oscillator to correct the frequency difference of a received signal and a local signal; this is a closed loop adjustment process that requires the frequency discrimination curve of the frequency discriminator to have an odd symmetry characteristic.
Referring to fig. 1, a schematic block diagram of an automatic frequency control loop commonly used in spread spectrum communications is shown. The received intermediate frequency signal 1 has frequency difference due to the fact that the transmitting end and the receiving end adopt clock sources with different accuracies, the intermediate frequency signal 1 and a signal output by a local voltage controlled oscillator 107 (usually, a local clock source) are mixed, and in-phase and quadrature baseband signals 101 and 102 with frequency difference are obtained. Then, the two paths of signals are respectively sent to the integrating-removing devices 103 and 104 to be digitalized and improve the signal-to-noise ratio of the signals, so as to obtain two paths of digital baseband signals Ik and Qk, wherein Ik is an in-phase digital baseband signal, and Qk is a quadrature digital baseband signal. Then, the signals Ik and Qk are input into the frequency discriminator 105 for discriminating the frequency difference of the signals, and an error correction voltage forming a certain proportional relation with the frequency difference of the signals is output through a certain signal processing method, and the error correction voltage is sent to the voltage-controlled oscillator 107 after noise is filtered by the loop filter 106, so that the frequency of the output signals of the voltage-controlled oscillator can be controlled, and the purpose of correcting the frequency difference is achieved. The performance of the frequency discriminator 105 in the feedback control process determines the accuracy of the frequency correction and the capture time of the loop, which are also the key points for implementing the automatic frequency control technique.
Currently used frequency discriminators are generally of two types: one is a cross product frequency discriminator using the cross product principle, and its basic functional block diagram is shown in fig. 2, where Ik and Qk are digital baseband signals of in-phase term and quadrature term, respectively, and the corresponding signal processing equation is:
vd(k)＝Ik-1Qk-IkQk-1the frequency discrimination range of the cross product frequency discriminator is as follows: <math> <mrow> <mi>Δf</mi> <mo>=</mo> <mfrac> <mn>1</mn> <mrow> <mn>2</mn> <mi>T</mi> </mrow> </mfrac> </mrow> </math> where T denotes the receiver unit sample time. The frequency discriminator is characterized by a large frequency discrimination range, but the capability of suppressing noise is general. It is desirable to achieve a higher noise capability by reducing the bandwidth of the loop filter, so that the loop isThe capture time is correspondingly lengthened, so that the contradiction between the noise performance and the capture time is difficult to overcome.
The other type is a frequency discriminator based on the maximum likelihood estimation principle, and the corresponding signal processing method has the following equation: <math> <mrow> <mover> <mi>ω</mi> <mo>^</mo> </mover> <mi>d</mi> <mo>=</mo> <mi>arg</mi> <mi>max</mi> <mo>|</mo> <munderover> <mi>Σ</mi> <mrow> <mi>k</mi> <mo>=</mo> <mn>0</mn> </mrow> <mrow> <mi>N</mi> <mo>-</mo> <mn>1</mn> </mrow> </munderover> <msub> <mi>r</mi> <mi>k</mi> </msub> <msup> <mi>e</mi> <mrow> <mo>-</mo> <mi>jk</mi> <msub> <mi>ω</mi> <mi>d</mi> </msub> <mi>T</mi> </mrow> </msup> <msup> <mo>|</mo> <mn>2</mn> </msup> </mrow> </math> wherein,
indicates the identified frequency difference, arg [.]Representing the operation of taking the argument, max representing the maximum value, | | representing the operation of taking the absolute value, | representing the number of the received symbols participating in the signal processing, rkRepresents the complex representation of the kth received signal, T represents the sampling period of the received signal, and Σ represents the accumulation operation. Omegad＝Is the fundamental frequency. The equation of the discriminator signal processing method is actually obtained by aligning the received signal sequence rkAnd performing discrete Fourier transform operation, finding the frequency corresponding to the maximum periodic peak to obtain an estimated frequency difference, wherein the estimation precision can reach the Cramer-Lo lower bound (CRLB), and the estimated frequency difference can directly correct the frequency difference of the signal. However, the computational effort of such discriminator signal processing equations is considerable. Although the computation workload and computation time of the discrete fourier transform can be reduced by the fast fourier transform, the complexity of such computation is not very suitable for real-time computation processing, especially as a real-time discriminator in an afc loop. Meanwhile, if the characteristics of the signal-to-noise ratio cannot be improved by using the upper loop, the estimation accuracy must be ensured under a certain signal-to-noise ratio condition. That is to sayThis increase in accuracy of the discriminator comes at the expense of increased complexity.
From the above analysis, it is difficult to overcome the contradiction between accuracy and capture time, accuracy and complexity by the two frequency discrimination methods used at present. The cross product frequency discriminator has a simpler structure and operation, but the improvement of the precision is at the cost of increasing the capture time. The maximum likelihood frequency difference estimation needs complex operation, and the signal-to-noise ratio SNR required by the frequency difference estimation of the open loop is high.
The invention aims to provide a novel simplified frequency discrimination signal processing method of maximum likelihood frequency difference, which is provided on the basis of further simplifying the current maximum likelihood estimator, greatly reduces the complexity of the realization of the estimation on the premise of reducing the original estimation precision and improves the contradiction between the precision and the complexity; meanwhile, the low complexity and the high precision relative to the cross product frequency discriminator are utilized to be applied to an automatic frequency control loop, and the capture time of the loop can be greatly shortened under the condition of reaching the same tracking precision. Meanwhile, the frequency discriminator can work in a lower signal-to-noise ratio environment by utilizing the characteristics of the loop, and the practicability is enhanced.
It is another object of the present invention to provide a frequency discriminator using a simplified frequency discrimination signal processing method of maximum likelihood frequency difference.
It is still another object of the present invention to provide a frequency discriminator applied in an afc loop, and a simplified and practical hardware circuit for an afc loop.
The simplified frequency discrimination signal processing method of the maximum likelihood frequency difference is realized as follows: let the input signal be rkI (k) + jq (k), representing a complex representation of the received signal, where i (k) is its real part and q (k) is its imaginary part; the physical significance of the input signal is that the in-phase term and the orthogonal term of the multi-phase shift keying MPSK signal after intermediate frequency demodulation are two paths of baseband numbersA word signal with a residual frequency offset; the method comprises the following implementation steps: (1) the received signal is sent to a conjugate arithmetic unit (301), and the specific operation method is as follows: the real part i (k) signal remains unchanged, while the imaginary part signal q (k) is inverted;
(2) the received signal after passing through the conjugate arithmetic unit (301) is sent to a plurality of delay units (302), (303), … (304) connected in sequence, the number of stages of the delay units is determined by the maximum correlation length M, and the delay time T is the sampling time of the received signal;
(3) performing complex accumulation operations (305), (306), … (307), (308) on the signals output by the delay units of each stage;
(4) carrying out complex multiplication and imaginary part taking operation on the accumulated signals and signals entering at the current moment in sequence; the complex multiplication and imaginary part taking operation is realized by two real multipliers (309), (310) and a real adder (311);
(5) smoothly accumulating the multiplication results, wherein the operation process is to shift the front N numbers backwards, when the Nth number is shifted out of the sliding filter, the vacated first number is supplemented by a newly input value, and at the moment, the N values are accumulated and averaged to obtain the current filtering result;
(6) and carrying out corresponding processing on the obtained complex result value to obtain the required frequency difference value.
The signal processing method has the following formula: <math> <mrow> <mover> <msub> <mi>f</mi> <mi>d</mi> </msub> <mo>^</mo> </mover> <mo>=</mo> <mfrac> <mn>1</mn> <mrow> <mi>πT</mi> <mrow> <mo>(</mo> <mi>M</mi> <mo>+</mo> <mn>1</mn> <mo>)</mo> </mrow> </mrow> </mfrac> <mi>arg</mi> <mo>{</mo> <munderover> <mi>Σ</mi> <mrow> <mi>k</mi> <mo>=</mo> <mn>1</mn> </mrow> <mi>M</mi> </munderover> <munderover> <mi>Σ</mi> <mrow> <mi>i</mi> <mo>=</mo> <mn>1</mn> </mrow> <mi>N</mi> </munderover> <msub> <mi>r</mi> <mi>i</mi> </msub> <msubsup> <mi>r</mi> <mrow> <mi>i</mi> <mo>-</mo> <mi>k</mi> </mrow> <mo>*</mo> </msubsup> <mo>}</mo> </mrow> </math> where T represents the sampling period of the received signal, N represents the number of received symbols participating in signal processing, rkRepresenting the complex representation of the kth received signal and M representing the maximum correlation length between the received signals. arg [.]Showing the argument operation.
The step (6) may be to obtain the corresponding argument value by looking up a table in a memory table in which corresponding argument values are stored in advance, based on the real and imaginary values of the obtained complex result value as addresses, where the argument value is the frequency difference value to be detected.
The frequency discriminator of the invention adopts a simplified frequency discrimination signal processing method of maximum likelihood frequency difference, which is realized as follows: the following hardware devices are included: conjugate operator for receiving in-phase term I (k) and quadrature term Q (k) of baseband branch signals demodulated by intermediate frequency respectively, so as to perform conjugate operation of negating imaginary part signal Q (k) therein; two paths of output signals of the conjugate arithmetic unit are respectively connected with a subsequent delayer, and a multistage delayer is sequentially connected behind the delayer; a plurality of groups of accumulators and a complex multiplier are arranged so as to carry out complex accumulation operation on two paths of output signals of each stage of delayer and the output signal of the delayer at the next stage respectively, and the accumulated sum and the sampling signal value at the current moment are sent to the complex multiplier to carry out complex multiplication operation; the device is also provided with an N-length sliding filter, a storage calculation argument module and a read-only memory corresponding to the calculation argument module, so as to smoothly accumulate the result of the complex multiplication to obtain the current filtering result of averaging N accumulated values, and then the obtained complex result value is used as an address to obtain the corresponding argument value through table lookup in a memory table in which the corresponding argument value is stored in advance according to the numerical values of the real part and the imaginary part of the complex number, wherein the argument value is the frequency difference value to be detected.
The number of stages of the sequentially connected multi-stage delays is determined by the maximum correlation length M between the received signals.
The complex multiplier comprises four real multipliers and two real adders.
The invention applies a simplified frequency discrimination signal processing method of maximum likelihood frequency difference, and a frequency discriminator applied in an automatic frequency control loop is realized as follows: the following hardware devices are included: conjugate operator for receiving in-phase term I (k) and quadrature term Q (k) of baseband signal demodulated by intermediate frequency, respectively, to perform conjugate operation of negating imaginary signal Q (k) therein; two paths of output signals of the conjugate arithmetic unit are respectively connected with a subsequent delayer, and a multistage delayer is sequentially connected behind the delayer; a plurality of groups of accumulators and a complex multiplier are arranged so as to carry out complex accumulation operation on two paths of output signals of each stage of delayer and the output signal of the delayer at the next stage respectively, and the accumulated sum and the sampling signal value at the current moment are sent to the complex multiplier to carry out complex multiplication operation and imaginary part taking operation; and an N-length sliding filter is also arranged to smoothly accumulate the imaginary part result obtained by the complex multiplication, and N values are accumulated and averaged to obtain an error voltage value sent to the loop filter.
The number of stages of the sequentially connected multi-stage delays is determined by the maximum correlation length M between the received signals.
The complex multiplier comprises two real multipliers and a real adder to complete the operation of taking the imaginary part by the complex multiplication.
The invention is mainly characterized in that: compared with the formula of the signal processing method of the frequency discriminator based on the maximum likelihood estimation principle, the complexity of the operation is greatly simplified. Here, the amount of computation of the frequency discrimination signal processing method of the present invention may be estimated: the total operation amount of the signal processing method is 4N real number multiplications, 2N (M-1) +2(N-1) real number addition and one ROM reading operation. The accuracy of the frequency discriminator can approach the lower bound of the Clarithrome bound, and the frequency discrimination range is as follows: wherein: m is the maximum correlation length of the discriminator.
Compared with the cross-product frequency discriminator, although the frequency discrimination range of the invention is reduced along with the increase of M, different frequency discrimination requirements can be met by properly adjusting the value of M.
In conclusion, compared with the two current frequency discriminators, the simplified maximum likelihood estimation method provided by the invention better solves the contradiction between the improvement of the frequency discrimination performance and the reduction of the complexity. In the application process of the AFC loop, although the structure of the cross-product frequency discriminator is simple and easy to realize, when good noise performance is realized, the capture time of the loop must be long enough, and the cross-product frequency discriminator cannot be applied to the field of fast tracking AFC. The maximum likelihood frequency difference estimation and some simplified maximum likelihood estimation methods applied at present are mostly used in the field of frequency difference estimation of post-processing and open-loop because the complexity is difficult to realize by hardware; although open-loop automatic frequency control can improve the frequency offset correction time, the open-loop frequency offset estimation needs to have good performance under the condition of high signal-to-noise ratio. The estimation performance of the method is close to the lower bound of CRLB (CrAlmeror), the implementation process is greatly simplified, and the method can be used for open-loop frequency difference estimation in real time; and the implementation steps of the frequency discriminator are simplified aiming at the automatic frequency control loop, and the hardware design is simple and flexible according to the performance requirement. Under the condition of realizing the same performance, the capture time of the frequency detector is doubled compared with that of a cross-product frequency detector, and the frequency detector can be used in the field of fast frequency difference tracking.
The processing method, hardware composition structure, signal processing steps and efficacy of the present invention are described in detail below with reference to the accompanying drawings and embodiments:
fig. 1 is a functional block diagram of an automatic frequency control loop, which is now common.
Figure 2 is a block diagram of the discriminator architecture for cross product automatic frequency control now in use.
Fig. 3 is a schematic block diagram of a hardware configuration of a frequency discriminator according to the present invention using a simplified frequency discrimination signal processing method of maximum likelihood frequency difference.
Fig. 4 is a schematic block diagram of a hardware configuration of a frequency discriminator in an afc loop according to the present invention using a simplified frequency discrimination signal processing method of maximum likelihood frequency difference.
The invention is a simplified frequency discrimination signal processing method of maximum likelihood frequency difference, it is put forward on the basis of further simplifying the present maximum likelihood frequency difference estimator, on the premise of reducing the original estimation precision, greatly reduce its complexity of realizing, has improved the contradiction between precision and complexity; meanwhile, the low complexity and the high precision relative to the cross product frequency discriminator are utilized to be applied to an automatic frequency control loop, and the capture time of the loop can be greatly shortened under the condition of reaching the same tracking precision. Meanwhile, the characteristic frequency discriminator of the loop can work in a lower signal-to-noise ratio environment, and the practicability is enhanced.
The simplified frequency discrimination signal processing method or equation of the processing formula of the maximum likelihood frequency difference is as follows: <math> <mrow> <mover> <msub> <mi>f</mi> <mi>d</mi> </msub> <mo>^</mo> </mover> <mo>=</mo> <mfrac> <mn>1</mn> <mrow> <mi>πT</mi> <mrow> <mo>(</mo> <mi>M</mi> <mo>+</mo> <mn>1</mn> <mo>)</mo> </mrow> </mrow> </mfrac> <mi>arg</mi> <mo>{</mo> <munderover> <mi>Σ</mi> <mrow> <mi>k</mi> <mo>=</mo> <mn>1</mn> </mrow> <mi>M</mi> </munderover> <mfrac> <mn>1</mn> <mrow> <mi>N</mi> <mo>-</mo> <mn>1</mn> </mrow> </mfrac> <munderover> <mi>Σ</mi> <mrow> <mi>i</mi> <mo>=</mo> <mn>1</mn> </mrow> <mi>N</mi> </munderover> <msub> <mi>r</mi> <mi>i</mi> </msub> <msubsup> <mi>r</mi> <mrow> <mi>i</mi> <mo>-</mo> <mi>k</mi> </mrow> <mo>*</mo> </msubsup> <mo>}</mo> <mo>=</mo> <mfrac> <mn>1</mn> <mrow> <mi>πT</mi> <mrow> <mo>(</mo> <mi>M</mi> <mo>+</mo> <mn>1</mn> <mo>)</mo> </mrow> </mrow> </mfrac> <mi>arg</mi> <mo>{</mo> <munderover> <mi>Σ</mi> <mrow> <mi>k</mi> <mo>=</mo> <mn>1</mn> </mrow> <mi>M</mi> </munderover> <munderover> <mi>Σ</mi> <mrow> <mi>i</mi> <mo>=</mo> <mn>1</mn> </mrow> <mi>N</mi> </munderover> <msub> <mi>r</mi> <mi>i</mi> </msub> <msubsup> <mi>r</mi> <mrow> <mi>i</mi> <mo>-</mo> <mi>k</mi> </mrow> <mo>*</mo> </msubsup> <mo>}</mo> </mrow> </math> where T represents the sampling period of the received signal, N represents the number of received symbols participating in signal processing, rkRepresenting the complex representation of the kth received signal and M representing the maximum correlation length between the received signals. arg [.]Showing the argument operation. By adopting the signal processing method, the estimation precision can be close to the Cramer-Rao bound, so the frequency discriminator can be applied to open-loop automatic frequency control. Aiming at the signal processing method, the invention also provides a structural schematic block diagram of the hardware implementation of the signal processing method, as shown in FIG. 3. The system comprises the following hardware devices: conjugate operator 301 receiving in-phase term i (k) and quadrature term q (k) of the baseband branch signals demodulated by the if respectively, so as to perform conjugate operation of negating imaginary part signal q (k) therein; the two output signals of the conjugate arithmetic unit are respectively connected with the following delayer 302, the multistage delayers 303, … 304 are sequentially connected behind the delayer 302, and the stage number of the sequentially connected multistage delayers 303, … 304 is determined by the maximum correlation length M between the received signals. Multiple groups of accumulators 305, 306, 307, 308, 313 and 314 and a complex multiplier 315 are provided, so that two output signals of each stage of delayer respectively perform complex accumulation operation with the output signal of the delayer of the next stage, and the accumulated sum and the sampling signal value at the current moment are sent to the complex multiplier 315 for complex multiplication operation, wherein the complex multiplication operation is completed by four multipliers 309, 310, 311 and 312 and two real adders 313 and 314. An N-length sliding filter 316 and a module for storing the calculated argument are also providedAnd a corresponding frequency offset rom 317, for performing smooth accumulation on the result of the complex multiplication to obtain a current filtering result obtained by averaging N accumulated values, and then obtaining a corresponding argument value by looking up a table in a memory table in which corresponding argument values are stored in advance, according to the real and imaginary values of the complex number as addresses.
The signal processing steps of the frequency discriminator shown in fig. 3 are as follows: let the input signal be rkI (k) + jq (k), representing a complex representation of the received signal, where i (k) is its real part and q (k) is its imaginary part; the physical significance of the input signal is that the input signal is in-phase and quadrature baseband digital signals after multi-phase shift keying MPSK signal intermediate frequency demodulation, and the in-phase and quadrature baseband digital signals have residual frequency difference.
(1) The received signal is sent to the conjugate operation unit 301, and the specific operation method is as follows: the real part i (k) signal remains unchanged, while the imaginary part signal q (k) is inverted;
(2) the received signal after passing through the conjugate operation unit 301 is sent to a plurality of delay units 302, 303, … 304 connected in sequence, the number of stages of the delay units is determined by the maximum correlation length M, and the delay time T is the sampling time of the received signal;
(3) performing complex accumulation operations 305, 306, … 307, and 308 on the signals output by the delay units of each stage;
(4) carrying out complex multiplication operation on the accumulated signals and signals entering at the current moment in sequence, wherein the complex multiplication operation is realized by four real number multipliers 309, 310, 311 and 312 and one real number adder 313 and 314;
(5) smoothly accumulating the multiplication results, wherein the operation process is to shift the front N numbers backwards, when the Nth number is shifted out of the sliding filter, the vacated first number is supplemented by a newly input value, and at the moment, the N values are accumulated and averaged to obtain the current filtering result;
(6) and obtaining corresponding argument values by looking up a table in a memory table in which corresponding argument values are stored in advance according to the real part numerical value and the imaginary part numerical value of the complex number as addresses, wherein the argument values are frequency difference values to be detected, so that the operation speed is greatly improved.
Since the frequency discriminator mainly satisfies the odd symmetry condition in the application of the automatic frequency control loop technology, the frequency difference of the signal can be corrected, therefore, the operation steps shown in the above fig. 3 are further modified and simplified by the present invention, and a more practical simplified maximum likelihood discriminator in the automatic frequency control loop can be obtained, and the schematic block diagram of the hardware structure thereof is shown in fig. 4. The system comprises the following hardware devices: conjugate operator 301 receiving in-phase term i (k) and quadrature term q (k) of the baseband signals demodulated by the if respectively, to perform a conjugate operation of negating imaginary signal q (k) therein; the two output signals of the conjugate operator 301 are respectively connected to the following delay 302, and the stage number of the sequentially connected multi-stage delays 303, … 304 is determined by the maximum correlation length M between the received signals after the delay 302. A plurality of groups of accumulators 305, 306, 307, 308 and a complex multiplier 318 are provided, so that two output signals of each stage of delayer respectively perform complex accumulation operation with the output signal of the delayer of the next stage, and the accumulated sum and the sampling signal value at the current moment are sent to the complex multiplier 318 for complex multiplication operation and imaginary part operation, wherein the complex multiplication operation and the imaginary part operation are completed by two real multipliers 309 and 310 and a real adder 313; an N-length sliding filter 319 is also provided to smoothly accumulate the imaginary result obtained by the above-mentioned complex multiplication, and to average the N values to obtain the error voltage value fed to the loop filter.
The signal processing steps of the frequency discriminator shown in fig. 4 are substantially the same as those of the frequency discriminator shown in fig. 3, and the input signal is also set to rkI (k) + jq (k), representing a complex representation of the received signal, where i (k) is its real part and q (k) is its imaginary part; the physical significance of the input signal is respectively in the multi-phase shift keying MPSK signalThe in-phase and quadrature baseband digital signals after frequency demodulation have residual frequency difference.
(1) The received signal is sent to the conjugate operation unit 301, and the specific operation method is as follows: the real part i (k) signal remains unchanged, while the imaginary part signal q (k) is inverted;
(2) the received signal after passing through the conjugate arithmetic unit 301 is sent to a plurality of delay units 302, 303, … 304 connected in sequence, the number of stages of the delay units is determined by the maximum correlation length M, and the delay time T is the sampling time of the received signal;
(3) performing complex accumulation operations 305, 306, … 307, and 308 on the signals output by the delay units of each stage;
(4) carrying out complex multiplication and imaginary part taking operation on the accumulated signals and signals entering at the current moment in sequence; the complex multiplication and imaginary part taking operation is implemented by two real multipliers 309, 310 and a real adder 311;
(5) and smoothly accumulating the obtained imaginary part results, wherein the operation process is to shift the front N numbers backwards, when the Nth number is shifted out of the sliding filter, the vacated first number is supplemented by a new input value, and at the moment, the N values are accumulated and averaged to obtain an error voltage value sent to the loop filter.
Comparing fig. 3 and fig. 4, the present invention provides a frequency discrimination signal processing method based on the maximum likelihood frequency difference estimation, and provides a hardware structure implementation schematic block diagram of signal processing and a new and more simplified hardware structure implementation schematic block diagram of a frequency discriminator applicable to an afc loop according to the simplified method.
The invention has been simulated in the cossa simulation environment of Synopsys, and has been experimentally implemented in a spread spectrum receiver developed by the applicant, which has performance approaching the CRLB (cramer) lower bound on open loop frequency difference estimation. The formula for the lower bound of CRLB (cramer) is shown below: <math> <mrow> <msubsup> <mi>σ</mi> <mi>Δf</mi> <mn>2</mn> </msubsup> <mo>=</mo> <mfrac> <mn>3</mn> <mrow> <mn>2</mn> <msup> <mi>π</mi> <mn>2</mn> </msup> <mi>T</mi> </mrow> </mfrac> <mo>·</mo> <mfrac> <mn>1</mn> <mrow> <mi>SNR</mi> <mo>·</mo> <mrow> <mo>(</mo> <msup> <mi>N</mi> <mn>2</mn> </msup> <mo>-</mo> <mn>1</mn> <mo>)</mo> </mrow> </mrow> </mfrac> </mrow> </math>
wherein sigmaΔfThe variance is estimated for the frequency difference, T represents the sampling time of the received signal, N represents the number of signal processes, and SNR is the signal-to-noise ratio of the signal. When N is 10, 20, 30, SNR is 7dB, and T is 1/16,000s, the CRLB (kramerol) lower bound at which the estimation accuracy can be calculated is: sigmaΔf＝85Hz、31Hz、16Hz。
To verify whether the accuracy of the simplified maximum likelihood frequency difference estimation can reach the lower limit of cramer, N is 10, 20, 30, SNR is 7dB, T is 1/16,000s, fdThe simulation was performed under an additive gaussian channel at 500Hz, and the results are shown in table 5.1, table 5.2, and table 5.3, respectively:
TABLE 5.1 estimation accuracy with different M's, N10
| M |
| 1 | 2 | 3 | 4 | 5 | 6 | |
| Estimation accuracy σΔf(HZ) | 100 | 68 | 55 | 51 | 45 | 40 |
Table 5.2 estimation accuracy with M different from N20
| M |
| 1 | 2 | 3 | 5 | 6 | 8 | 10 | 12 | 14 | |
| Estimation accuracy σΔf(Hz) | 65 | 40 | 33 | 22 | 21 | 19 | 18 | 17 | 17 |
Table 5.3 estimation accuracy with different M, N30
| M |
| 1 | 2 | 4 | 6 | 8 | 10 | 12 | 14 | 15 | 16 | 18 | |
| Estimation accuracy σΔf(Hz) | 42 | 26 | 18 | 15 | 14 | 13 | 12 | 12 | 12 | 11 |
As can be seen from the above three tables, the selection and estimation accuracy of M are in a certain relationship. When M > N/2, the estimation method of the present invention has little effect on improving the amount of computation, which illustrates the feasibility of the present invention to simplify the maximum likelihood estimation, and M may be selected to be N/2. In addition, as can be seen from the tables: the accuracy of the estimates exceeds the CR (cramer) bound at different N. This is because the accumulation range of the accumulator is enlarged, which is actually equivalent to increasing the value of N, resulting in improved estimation accuracy, while when M is equal to 1, it is actually reduced to cross product automatic frequency control.
Since the simplified estimator may have good performance after selecting suitable M, N parameters, but requires a higher signal-to-noise ratio, and when applied in the afc loop, it can just eliminate this effect, which makes the invention shorter than the capture time of cross product afc when applied in the afc loop with the same signal-to-noise ratio. Through simulation, when M is equal to N/2, the capture time of the simplified estimator is doubled compared with the cross product automatic frequency control. Therefore, the frequency discriminator can better embody the excellent performance in the application of the automatic frequency control loop by utilizing the characteristic that the phase-locked loop can improve the signal-to-noise ratio, and has better application prospect in the automatic frequency control loop.
Claims (9)
1. A simplified frequency discrimination signal processing method of maximum likelihood frequency difference is characterized in that: let the input signal be rkI (k) + jq (k), representing a complex representation of the received signal, where i (k) is its real part and q (k) is its imaginary part; the physical significance of the input signal is that the input signal is two paths of baseband digital signals of an in-phase term and an orthogonal term after multi-phase shift keying MPSK signal intermediate frequency demodulation, and the baseband digital signals have residual frequency difference; the method at least comprises the following implementation steps:
(1) the received signal is sent to a conjugate arithmetic unit (301), and the specific operation method is as follows: the real part i (k) signal remains unchanged, while the imaginary part signal q (k) is inverted;
(2) the received signal after passing through the conjugate arithmetic unit (301) is sent to a plurality of delay units (302), (303), … (304) connected in sequence, the number of stages of the delay units is determined by the maximum correlation length M, and the delay time T is the sampling time of the received signal;
(3) performing complex accumulation operations (305), (306), … (307), (308) on the signals output by the delay units of each stage;
(4) carrying out complex multiplication and imaginary part taking operation on the accumulated signals and signals entering at the current moment in sequence; the complex multiplication and imaginary part taking operation is realized by two real multipliers (309), (310) and a real adder (311);
(5) smoothly accumulating the multiplication results, wherein the operation process is to shift the front N numbers backwards, when the Nth number is shifted out of the sliding filter, the vacated first number is supplemented by a newly input value, and at the moment, the N values are accumulated and averaged to obtain the current filtering result;
(6) and carrying out corresponding processing on the obtained complex result value to obtain the required frequency difference value.
2. The simplified method of frequency discrimination signal processing of maximum likelihood frequency differences as set forth in claim 1, wherein: the signal processing method is carried out according to the following formula: <math> <mrow> <mover> <msub> <mi>f</mi> <mi>d</mi> </msub> <mo>^</mo> </mover> <mo>=</mo> <mfrac> <mn>1</mn> <mrow> <mi>πT</mi> <mrow> <mo>(</mo> <mi>M</mi> <mo>+</mo> <mn>1</mn> <mo>)</mo> </mrow> </mrow> </mfrac> <mi>arg</mi> <mo>{</mo> <munderover> <mi>Σ</mi> <mrow> <mi>k</mi> <mo>=</mo> <mn>1</mn> </mrow> <mi>M</mi> </munderover> <munderover> <mi>Σ</mi> <mrow> <mi>i</mi> <mo>=</mo> <mn>1</mn> </mrow> <mi>N</mi> </munderover> <msub> <mi>r</mi> <mi>i</mi> </msub> <msubsup> <mi>r</mi> <mrow> <mi>i</mi> <mo>-</mo> <mn>1</mn> </mrow> <mo>*</mo> </msubsup> <mo>}</mo> </mrow> </math> wherein T represents the acquisition of the received signalSample period, N represents the number of received symbols participating in signal processing, rkRepresenting the complex representation of the kth received signal and M representing the maximum correlation length between the received signals. arg [.]Showing the argument operation.
3. The simplified method of frequency discrimination signal processing of maximum likelihood frequency differences as set forth in claim 1, wherein: the step (6) may be to obtain the corresponding argument value by looking up a table in a memory table in which corresponding argument values are stored in advance, based on the real and imaginary values of the obtained complex result value as addresses, where the argument value is the frequency difference value to be detected.
4. A frequency discriminator using a simplified frequency discrimination signal processing method of maximum likelihood frequency difference, characterized by: the following hardware devices are included: conjugate operator for receiving in-phase term I (k) and quadrature term Q (k) of baseband branch signals demodulated by intermediate frequency respectively, so as to perform conjugate operation of negating imaginary part signal Q (k) therein; two paths of output signals of the conjugate arithmetic unit are respectively connected with a subsequent delayer, and a multistage delayer is sequentially connected behind the delayer; a plurality of groups of accumulators and a complex multiplier are arranged so as to carry out complex accumulation operation on two paths of output signals of each stage of delayer and the output signal of the delayer at the next stage respectively, and the accumulated sum and the sampling signal value at the current moment are sent to the complex multiplier to carry out complex multiplication operation; the device is also provided with an N-length sliding filter and a read-only memory for storing a calculation argument module and a corresponding frequency difference thereof, so as to smoothly accumulate the results of the complex multiplication to obtain the current filtering result of averaging N accumulated values, and then the obtained complex result value is used as an address according to the numerical values of the real part and the imaginary part of the complex number to obtain the corresponding argument value by looking up a table in a memory table in which the corresponding argument value is stored in advance, wherein the argument value is the frequency difference value to be detected.
5. The frequency discriminator using the simplified frequency discrimination signal processing method of maximum likelihood frequency difference as set forth in claim 4, wherein: the number of stages of the sequentially connected multi-stage delays is determined by the maximum correlation length M between the received signals.
6. The frequency discriminator using the simplified frequency discrimination signal processing method of maximum likelihood frequency difference as set forth in claim 4, wherein: the complex multiplier comprises four real multipliers and two real adders.
7. A frequency discriminator for use in an automatic frequency control loop, using a simplified method of processing a frequency discriminated signal using maximum likelihood frequency differences, characterized by: the following hardware devices are included: conjugate operator for receiving in-phase term I (k) and quadrature term Q (k) of baseband signal demodulated by intermediate frequency, respectively, to perform conjugate operation of negating imaginary signal Q (k) therein; two paths of output signals of the conjugate arithmetic unit are respectively connected with a subsequent delayer, and a multistage delayer is sequentially connected behind the delayer; a plurality of groups of accumulators and a complex multiplier are arranged so as to carry out complex accumulation operation on two paths of output signals of each stage of delayer and the output signal of the delayer at the next stage respectively, and the accumulated sum and the sampling signal value at the current moment are sent to the complex multiplier to carry out complex multiplication operation and imaginary part taking operation; and an N-length sliding filter is also arranged to smoothly accumulate the imaginary part result obtained by the complex multiplication, and N values are accumulated and averaged to obtain an error voltage value sent to the loop filter.
8. The frequency discriminator using a simplified maximum likelihood frequency difference signal processing method, as set forth in claim 7, applied in an automatic frequency control loop, wherein: the number of stages of the sequentially connected multi-stage delays is determined by the maximum correlation length M between the received signals.
9. The frequency discriminator using a simplified maximum likelihood frequency difference signal processing method, as set forth in claim 7, applied in an automatic frequency control loop, wherein: the complex multiplier comprises two real multipliers and a real adder to complete the operation of taking the imaginary part by the complex multiplication.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1592288B (en) * | 2003-08-14 | 2010-05-26 | Lg电子株式会社 | Automatic frequency control device and mehtod of QPSK modulation system |
| CN101569103B (en) * | 2006-12-27 | 2015-08-19 | 艾利森电话股份有限公司 | The method of frequency synthesizer and the output signal by this synthesizer generation expected frequency |
| CN109031188A (en) * | 2018-06-14 | 2018-12-18 | 中国人民解放军战略支援部队信息工程大学 | A kind of narrow-band radiated source frequency difference estimation method and device based on Monte Carlo |
-
2000
- 2000-07-20 CN CNB001214136A patent/CN1177410C/en not_active Expired - Lifetime
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1592288B (en) * | 2003-08-14 | 2010-05-26 | Lg电子株式会社 | Automatic frequency control device and mehtod of QPSK modulation system |
| CN101569103B (en) * | 2006-12-27 | 2015-08-19 | 艾利森电话股份有限公司 | The method of frequency synthesizer and the output signal by this synthesizer generation expected frequency |
| CN109031188A (en) * | 2018-06-14 | 2018-12-18 | 中国人民解放军战略支援部队信息工程大学 | A kind of narrow-band radiated source frequency difference estimation method and device based on Monte Carlo |
| CN109031188B (en) * | 2018-06-14 | 2021-01-29 | 中国人民解放军战略支援部队信息工程大学 | Monte Carlo-based narrow-band radiation source frequency difference estimation method and device |
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