CN1332477A - Isolated capacitor trench top medium for self-aligning device - Google Patents
Isolated capacitor trench top medium for self-aligning device Download PDFInfo
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- CN1332477A CN1332477A CN00104064.2A CN00104064A CN1332477A CN 1332477 A CN1332477 A CN 1332477A CN 00104064 A CN00104064 A CN 00104064A CN 1332477 A CN1332477 A CN 1332477A
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- 239000000758 substrate Substances 0.000 claims abstract description 56
- 239000004065 semiconductor Substances 0.000 claims abstract description 40
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- 229920002120 photoresistant polymer Polymers 0.000 claims description 26
- 239000000463 material Substances 0.000 claims description 21
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- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 3
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 239000011248 coating agent Substances 0.000 claims description 2
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Abstract
An semiconductor device including substrates has at least a pair of deep channels in the substrate. The neck straps are lined in at least partial walls of the deep channels, and the deep channels are filled with some stuffing. The buried strips extend across the stuffing in the deep channels and the deep channels on the neck straps. The isolating areas are arranged between the ddep channels. Medium area covers the buried strip in various deep channels.
Description
The application relates to the U.S. Patent application No.09/233887 that is entitled as " with the improvement technology of the self aligned burying strip of storage deep trench " that proposed on January 20th, 1999, classifies its disclosed whole contents as reference herein.
The present invention relates to semiconductor device.Or rather, the present invention relates to dynamic random access memory (DRAM) device.
People are just making the more and more semiconductor device such as the separate memory unit of number on single chip.As a result, size of devices is constantly dwindled.Dwindling of device size increased the difficulty of guaranteeing suitable aligning on the functional areas that meet the demands of semiconductor device structure.
For example, Fig. 1 shows a kind of embedding isolation node groove (MINT) unit.MINT unit shown in Figure 1 comprises a plane carrying device.Device shown in Figure 1 comprises deep-trench capacitor 1, is used for defining the shallow channel isolation area 2 in source region, bit line contact (CB) 3, word line (WL) 5 are grid, gate oxide 7 and N+ source/ drain region 9 and 11 of carrying device.In structure shown in Figure 1, burying strip 12 is connected to deep-trench capacitor storage channel node 1 source/leakage the diffusion region 11 of carrying device.In MINT, the resistance of MINT burying strip can be the deep trench 1 of memory cell and the overlapping function between the shallow channel isolation area 2.
The present invention is considered as overlapping function between deep trench and the active area with MINT burying strip resistance, makes the shallow trench isolation pattern be self-aligned to deep trench, thereby guarantees that burying strip makes required whole groove width.
According to purpose and the advantage of these and other, the invention provides a kind of semiconductor device that comprises substrate.In substrate, be mounted with a pair of deep trench at least.Neck ring serves as a contrast at least on the part wall of each deep trench.Groove contains the packing material of conduction.Each groove on each trench filling of the whole leap of burying strip and each neck ring and extending.Isolated area is placed between each deep trench.Dielectric area covers each burying strip in each deep trench.
Each situation of the present invention also provide make the active area that is self-aligned to deep trench and shallow trench isolation from technology.This technology is included in the substrate and makes at least one pair of adjacent deep trench by first dielectric layer on the substrate surface.On the partial sidewall at least of each deep trench, make the medium neck ring.Deep trench is filled.Make the top surface of deep trench filler recessed.Part deep trench neck ring is corroded.Deposit bar material on the deep trench filler and in the recessed deep trench neck ring.Deposit second dielectric layer on the exposed surface of bar material, substrate and first dielectric layer.This structure is flattened, thereby remove part second dielectric layer, second dielectric layer only is retained in the deep trench.The deposit photoresist layer.Photoresist is carried out graphically, so that part second dielectric layer and part first dielectric layer in the exposure deep trench, making at least, the reserve part photoresist covers deep trench.Optionally remove part first dielectric layer between each groove.Part second dielectric layer in the groove and the part substrate between each groove are optionally removed.In the interval that is produced by removing part first dielectric layer and part second dielectric layer, deposit the 3rd dielectric layer.Then the 3rd dielectric layer is flattened.Remove the remainder of first dielectric layer.
Other situation of the present invention provides a kind of usefulness semiconductor device that above-mentioned technology is made.
From following detailed description, person skilled in the art will easily understand other purpose of the present invention and advantage, wherein only describe most preferred embodiment of the present invention with the method for the desired optimal mode of explanation enforcement the present invention simply.As understandable, the present invention can have other different embodiment, and its some details can be revised aspect tangible at each and do not surmount the present invention.Therefore, accompanying drawing and description are considered to be exemplary and not restrictive.
When considering in conjunction with the accompanying drawings, will more be expressly understood above-mentioned purpose of the present invention and advantage, wherein:
Fig. 1 is the profile of the example of the DRAM cellular construction known;
Fig. 2 is the vertical view of the embodiment of DRAM cellular construction, shows the overlapping better and relatively poor example of deep trench and active area;
Fig. 3 is the overlapping relatively poor profile of deep trench and active area; And
Fig. 4-the 15th, the embodiment of semiconductor device according to the invention structure is at the profile in each stage of process implementing example according to the present invention.
Along with dimensions of semiconductor devices reduce and same space in the increase of number of the device of packing into because aiming at of the device portions that the crowded and device of device and size have reduced may go wrong.For example, in some memory cell, deep trench and active area figure may misalignment.A problem that causes thus is that the resistance of burying strip is the function of deep trench-active area lap.Therefore, the misalignment that deep trench-active area is overlapping may change the resistance of burying strip, thereby the variation that causes the burying strip series resistance that the foozle of misalignment causes increases.
Fig. 2 shows the vertical view of part semiconductor device architecture, show a plurality of deep trench, and it is overlapping to show deep trench-active area.Fig. 2 shows deep trench 14, grid conductor 16, active area 18 and diffusion and contacts (CB) district 20.Fig. 2 also shows two overlapping examples of deep trench-active area.Deep trench-active area overlay region 22 shows between active area and the deep trench lap preferably.On the other hand, deep trench-active area 24 is more undesirable.
Fig. 3 shows the profile of the relatively poor example of deep trench-active area overlapping 32.Fig. 3 show the filling that respectively has relevant neck ring district 28 deep trench 26.Shallow channel isolation area 30 is covered with the zone between deep trench 26 and the deep trench.
The present invention makes the active area figure be self-aligned to deep trench to guarantee the technology of the whole groove width that the burying strip making is required by means of providing, and guarantees the overlapping solution of deep trench-active area preferably and provide.According to technology of the present invention,, can be used for making deep-trench capacitor and shallow channel isolation area based on MINT with the mask layer of groove top oxide region as shallow channel isolation area.Technology according to the present invention can also be used to making other semiconductor device.
Structure of the present invention according to shown in Fig. 4-15 can provide substrate 34.Can on top surface, make dielectric layer 36.According to an example, this dielectric layer is a nitride.Exactly, can be silicon nitride SiN as the nitride of dielectric layer 36.Though not shown, in dielectric layer 36, can comprise the extra medium thin layer such as silicon dioxide.After making has the substrate 34 of the dielectric layer 36 that is arranged on its top surface, can be with the photoetching and the dry etching technology such as reactive ion etching (RIE) of standard, make by dielectric layer 36 and be deep into deep trench 38 in the substrate 34.
After making deep trench 38, can on the part surface 42 of each deep trench 38, make neck ring 40.This neck ring can be made by the dielectric material of silicon dioxide and so on.
Can make neck ring with the method for trench wall being carried out oxidation.This neck ring is produced on the upper area of each deep trench 38 usually, makes neck ring extend to the top of deep trench 38 when making always.In other words, the backing material of the wall 42 of formation deep trench 38 can be oxidized to form neck ring 40.
After forming neck ring zone 40, fill deep trench with electric conducting material.Fig. 6 shows an example of the deep trench that is filled.Can at first fill deep trench with desirable material.The examples of material that can be used for filling deep trench comprises various semi-conducting materials.For example, polysilicon can be used as the deep trench filler.
After filling deep trench, can the upper surface of structure shown in Figure 6 be flattened, so that remove any deep trench filler of the upper surface that may be deposited on structure.Can make the recessed one-tenth of deep trench filler be lower than the deep trench window at substrate top surface place then.Can carry out that this is recessed with the dry etching technology of RIE and so on.In other words, can make the recessed one-tenth of deep trench filler be lower than the interface of substrate 34 and dielectric layer 36.Fig. 6 shows recessed deep trench filler 44.
Filling deep trench and making trench filling recessed after desirable degree, can isotropically erode neck ring 40, making the top surface of neck ring be lower than the top surface of trench filling from the sidewall of the exposure of groove.Can carry out the corrosion of neck ring 40 with the wet etching technology.Fig. 7 shows recessed neck ring structure 40.
Make neck ring structure 40 recessed after, can in each deep trench, make burying strip.According to the present invention, dark burying strip can be made into the whole deep trench that extends across.Burying strip can be made by semi-conducting material.According to an embodiment, this burying strip can be made by silicon.
Any suitable technology can be used for making burying strip.For example can adopt chemical vapor deposition method.According to an embodiment, can adopt low pressure chemical vapor deposition (LP CVD) to make burying strip.
Burying strip can be made into covering groove filler 44 and neck ring structure 40.In one embodiment of the invention, after deposit burying strip material, can make this material recessed.Fig. 8 shows the example that is produced on the burying strip 46 on trench filling 44 and the recessed neck ring 40 after wafer surface and trenched side-wall have isotropically been removed bar shaped silicon.
After making burying strip structure 46, though not shown, can at dielectric layer 36, lining on the surface of the wall of deep trench above the surface of the dielectric layer 36 of deep trench top window, the bar shaped 46 and bar shaped, make lining 48.The present invention not necessarily will comprise lining.This lining is optional structure.This lining can be made by dielectric material.According to an example, this lining is made up of the LPCVD nitride that thickness is about 2-10nm.A kind of specific nitride that can be used for lining is silicon nitride SiN.In addition, forming the thin thermal oxide layer that thickness is about 2-10nm before the deposit lining, may be desirable.
After making lining structure 48, can be on lining deposit dielectric material 50.If the present invention do not comprise lining, then can be on the structure identical with the structure of above-mentioned deposit lining dielectric layer deposited.Can adopt any suitable medium.According to an example, can form dielectric layer 50 with oxide.An example of operable oxide is a silicon dioxide.
Fig. 9 shows the structure that comprises lining 48 and dielectric area 50.
After dielectric layer deposited 50, can remove the part medium 50 on the above-mentioned dielectric area 36 with the flatening method such as dielectric area 50 being carried out chemico-mechanical polishing (CMP).In this screed step, if structure comprises lining, then the lining district at dielectric area 36 tops also may be eliminated.Figure 10 shows the structure that leveling dielectric area 50 obtains.As from Figure 10 as seen, the part dielectric area 50 that stays is arranged in the window of deep trench and deep trench top dielectric area 36.These dielectric area 52 can form the groove top area at each place, deep trench top.At dielectric material 50 is under the situation of oxide, and zone 52 can be called groove top oxide (TTO).
Removing part dielectric area 50 with after producing groove top area 52, can be on the entire upper surface of structure deposit photoresist 54.After the deposit photoresist, can carry out graphically photoresist, so that structurally be formed with source region and shallow trench isolation pattern.Figure 11 shows the example of structural figure photoresist 54.Photoresist shown in Figure 11 is by graphically, so that the dielectric area 36 between each groove top area 52 of expose portion and the deep trench.Traditional photoetching process can be used for photoresist is carried out graphically to form mask.
After on deep trench and other following square structure, making required mask graph 54, can corrode owing to removing the structural region that the part photoresist exposes.Usually adopt reactive ion etching.This corrosion can comprise the gas of supplying with fluorine, carbon and oxygen.The example of these gases can comprise CF
4, CHF
3, Ar, O
2, CO, C
2F
6, C
4F
6And/or C
3F
8
Can in a plurality of steps, carry out corrosion process.For example, first corrosion can be used for only corroding part dielectric area 36 and corrosive medium 52 parts not.This corrosion can be thought with respect to medium 52 corrosive medium 36 optionally.Below, dielectric layer 36 zone to the removing that can be corroded of small part substrate.This corrosion also can think to have selectivity with respect to photoresist.Figure 12 shows the zone 56 of the deep trench that produces adjacent to this corrosion.
The structure that obtains can be thought the semiconductor device each several part of having represented line 58 to separate now.These parts are array 60 and supporting structure 62.Represent a part of supporting structure by the zone 56 that corrosion produces.This supporting structure can comprise conventional transistor and shallow channel isolation area.
Can carry out second corrosion now, so that the corrosion silicon substrate.This second corrosion is selective to the expose portion of trench top bilge construction 52.As shown in figure 13, substrate can be corroded to the height that is lower than strip structure 46 and is lower than 40 tops, neck ring district.Zone between the deep trench and supporting structure window 56 can be corroded to identical height.As an alternative, these two zones also can be corroded to different height.As shown in figure 13, when the corrosion substrate, also can be corroded to small part trench top portion zone 52.This second corrosion can be thought with respect to medium 52 and photoresist 54 optionally to the corrosion of silicon, and can be to use such as Cl
2, HCl, HBr and/or BCl
3And so on the dry etching of supply gas.
After corrosive medium district 36, substrate and groove top area 52, can remove residual photoresist 54 from the upper surface of structure.After corrosive medium district 36, substrate and groove top area 52, can also the zone 64 in deposition materials.Zone 64 isolated areas that can form between the deep trench, normally shallow isolated area.The material of filling isolated area 64 also can be used for filling supporting structure groove 56.Can while fill area 56 and 64.
The material that is deposited in the zone 64 can be a dielectric material.According to an example, the dielectric material that is deposited in the zone 64 is the oxide of silica and so on.This dielectric material forms shallow channel isolation area.With after forming zone 64, can flatten the upper surface of structure at the deposit medium, so that remove the dielectric material district of the outside, space that forms isolated area.Can flatten with CMP.
After filling isolated area 64, can remove dielectric area 36 from the upper surface of substrate.To the leveling that the dielectric material of filling isolated area 64 carries out, also can remove part groove top area 52 and dielectric area 36.This screed step may be useful for the copline top surface that obtains groove top region 52 and isolated area 64.This screed step can also help to make top and the groove top area 52 and isolated area 64 coplines of supporting structure 56.Figure 14 shows the embodiment of the device architecture in this stage in the technology.
After making structure shown in Figure 14, transistor and other device can made at least one deep trench and on the supporting structure.Be produced on structural device architecture shown in Figure 15 and can comprise the grid conductor region.What be commonly referred to metal 0 (M0) is included in diffusion region and middle part to the lining district that contacts of grid conductor and ground floor interconnection wiring, also can be produced on deep trench and/or the supporting structure with standard process techniques.
According to a certain embodiments, the present invention also provide a kind of the shallow trench isolation that is self-aligned to deep trench from be manufactured with the technology in source region.This technology comprises provides the substrate that has nitride layer on the surface.By nitride, in substrate, make at least one pair of adjacent deep trench.
On the partial sidewall at least of each groove, make oxide collar.Use the polysilicon filling groove.Make the top surface of trench filling recessed.Part groove neck ring is corroded.At deposited oxide bar material on the trench filling and on the recessed groove neck ring.Can be on the surface that is exposed of the nitride layer on bar material, substrate and the substrate deposit lining.On lining, or if the present invention does not comprise lining then on the structure of deposit lining, the deposited oxide layer.Total is flattened, so that partial oxide layer and part lining on the removing lining only are retained in the groove oxide skin(coating).If structure does not comprise lining, then only remove the partial oxide layer.
Deposit photoresist structurally.Photoresist is carried out graphically,, make to the small part photoresist and still cover deep trench so that expose partial oxide layer in the groove and the nitride layer on the substrate.Part nitride layer on the substrate between the groove is carried out selective clearing.Partial oxide layer in the groove and the part substrate between the groove are carried out selective clearing.By removing between the groove on the substrate and in the interval that nitride layer produced in the partial oxide layer in the groove deposited oxide.Then this oxide is flattened.Removing is retained in the nitride on the substrate surface.On at least one deep trench, make transistor device.
The present invention also comprises the semiconductor device of making of above-mentioned technology.Can make semiconductor device according to the invention according to above-mentioned technology.As an alternative, also can make semiconductor device according to the invention with other technology.
Semiconductor device according to the invention comprises substrate.In substrate, arrange a pair of deep trench at least.As mentioned above, each deep trench can be parallel or substantially parallel.In each deep trench, settle trench filling.Between each groove, can arrange isolated area.
The present invention can comprise many to deep trench.Each to deep trench as mentioned above.The platy structure of burying can be arranged in each in each relevant substrate of deep trench.
The neck ring district serves as a contrast at least on the part wall of each deep trench.This neck ring can be arranged near each deep trench of each deep trench top.Neck ring can be made by dielectric material.This dielectric material can be an oxide.An example of the dielectric material that can adopt is silicon dioxide SiO
2
Whole each deep trench that extends across on each deep trench filler and each neck ring of burying strip.Dielectric area can cover each burying strip in each deep trench.Lining can be arranged between each bar shaped and each dielectric area.
Can at least one deep trench, make transistor device and interconnection structure.
Supporting structure can be produced in the substrate away from deep trench.Can fill the supporting structure isolated groove with dielectric material.This dielectric material can be an oxide.An example of the oxide that can adopt is silicon dioxide SiO
2
In Figure 15, array area is illustrated as zone 60, and supporting structure is illustrated as zone 61.Each the regional material that comprises semiconductor device according to the invention can be as top about as described in the technology of the present invention.
An advantage of the invention is that needn't depend on AA figure aspect aims at the strictness of deep trench figure aspect.As long as part A A figure covers deep trench, just can provide bar shaped.In addition, according to the present invention, owing to the strict overlapping tolerance that has increased between AA aspect and the deep trench aspect, so can make the littler deep trench of diameter.
According to the present invention, compare according to art methods and structure, owing to the favorable conductive path is arranged in order to ensure entering the deep trench reservior capacitor by bar shaped from active area, active area photoresist figure only need cover the edge of the trench top bilge construction on the deep trench, so can allow bigger misalignment.According to the present invention, different with the embodiment shown in Fig. 2 and 3, shallow trench isolation is from can be only between back-to-back groove, is divided into strip width therefore in the DRAM unit shown in Fig. 2 and 3.And the present invention can also help to eliminate the sensitiveness that burying strip resistance covers active area-deep trench with the method that is associated with source region and deep trench figure.
Foregoing description of the present invention has illustrated the present invention.In addition, the disclosure has only been described most preferred embodiment of the present invention, but as mentioned above, it should be understood that, the present invention can be used in various other combinations, correction and the environment, and changes in the suitable design scope of the present invention of the skills or knowledge with above-mentioned explanation and/or correlation technique that can represent herein or revise.Above-mentioned each embodiment is used for explain implementing optimal mode of the present invention and is used for making the one skilled in the art with the desired various corrections of special applications of the present invention, to utilize the present invention in these or other embodiment.Therefore, this description is not to be used for limiting the present invention to form disclosed herein.Should think that also claims are used for comprising each flexible embodiment.
Claims (28)
1. semiconductor device, it comprises:
Substrate;
At least one pair of deep trench in the substrate;
Lining is at the neck ring to the small part wall of each deep trench;
Deep trench filler in each deep trench;
On each deep trench filler and each neck ring, cross over the burying strip that each deep trench is extended fully;
Isolated area between the deep trench; And
The dielectric area of each burying strip of covering in each deep trench.
2. according to the semiconductor device of claim 1, wherein the isolated area between active area on each groove and the paired groove is self-aligned to deep trench.
3. according to the semiconductor device of claim 1, also comprise the transistor device that is produced on each deep trench.
4. according to the semiconductor device of claim 1, also comprise respectively have neck ring, trench filling, burying strip and a dielectric area many to deep trench and each is to the isolated area between the groove.
5. according to the semiconductor device of claim 1, also comprise the lining between each bar shaped and each dielectric area.
6. according to the semiconductor device of claim 1, also comprise the supporting structure in the substrate, this supporting structure comprises near the isolated groove the deep trench paired in the substrate, and this supporting structure groove is filled.
7. according to the semiconductor device of claim 6, supporting structure isolated groove SiO wherein
2Fill.
8. according to the semiconductor device of claim 6, also comprise the transistor device that is produced on the part supporting structure groove.
9. according to the semiconductor device of claim 1, also comprise the buried plate structure relevant to deep trench with each.
10. according to the semiconductor device of claim 1, neck ring wherein is arranged near the top of each deep trench, is made by dielectric material.
11. according to the semiconductor device of claim 1, neck ring wherein is by SiO
2Make.
12. according to the semiconductor device of claim 1, groove is wherein filled with polysilicon.
13. according to the semiconductor device of claim 1, bar shaped is wherein made by polysilicon.
14. according to the semiconductor device of claim 1, lining is wherein made by dielectric material.
15. according to the semiconductor device of claim 14, lining is wherein made by silicon nitride.
16. according to the semiconductor device of claim 1, isolated area wherein is a shallow channel isolation area.
17. according to the semiconductor device of claim 14, isolated area SiO wherein
2Fill.
18. according to the semiconductor device of claim 1, dielectric area wherein is an oxide.
19. according to the semiconductor device of claim 1, wherein each deep trench is parallel or substantially parallel.
20. according to the semiconductor device of claim 1, semiconductor device wherein is DRAM.
21. a making be self-aligned to the active area of deep trench and shallow trench isolation from technology, this technology comprises:
In substrate, make at least one pair of adjacent deep trench by first dielectric layer on the substrate surface;
On the partial sidewall at least of each deep trench, make the medium neck ring;
Fill deep trench;
Make the top surface of trench filling recessed;
Part groove neck ring is corroded;
Deposit bar material on trench filling and in the recessed groove neck ring;
Deposit second dielectric layer on the exposed surface of bar material, substrate and first dielectric layer;
This structure is flattened, thereby remove part second dielectric layer, make second dielectric layer only be retained in the deep trench;
The deposit photoresist layer;
Photoresist is carried out graphically, so that part second dielectric layer and part first dielectric layer in the exposure deep trench, making at least, the reserve part photoresist covers deep trench;
Optionally remove part first dielectric layer between each groove;
Optionally remove the part substrate between each groove;
By removing in the interval that part first dielectric layer and part second dielectric layer produced, deposit the 3rd dielectric layer, and the 3rd dielectric layer flattened; And
Remove the remainder of first dielectric layer.
22., also be included in the step of making buried plate in the substrate relevant with paired deep trench according to the technology of claim 21.
23., also be included in the step of making transistor device at least one deep trench according to the technology of claim 21.
24., wherein corrode the top surface of neck ring with wet corrosion technique according to the technology of claim 21.
25., wherein make neck ring with the low pressure chemical vapor deposition method according to the technology of claim 21.
26. according to the technology of claim 21, also be included in deposit lining on the surface of exposure of bar material, substrate and first dielectric layer, second dielectric layer wherein is deposited on the lining, and removes part lining and part second dielectric layer in flattening course.
27. a semiconductor device of making of following technology, this technology comprises:
In substrate, make at least one pair of adjacent deep trench by first dielectric layer on the substrate surface;
On the partial sidewall at least of each groove, make the medium neck ring;
Filling groove;
Make the top surface of trench filling recessed;
Part groove neck ring is corroded;
At deposit bar material on the trench filling and on the recessed groove neck ring;
Deposit second dielectric layer on the exposed surface of bar material, substrate and first dielectric layer;
This structure is flattened, thereby remove part second dielectric layer, make second dielectric layer only be retained in the groove;
The deposit photoresist layer;
Photoresist is carried out graphically, so that part second dielectric layer and first dielectric layer in the exposure groove, making at least, the reserve part photoresist covers deep trench;
Optionally remove part first dielectric layer between each groove;
Optionally remove the part substrate between each groove;
By removing deposit the 3rd dielectric layer in the interval that part first dielectric layer and part second dielectric layer produced, and the 3rd dielectric layer is flattened; And
Remove the remainder of first dielectric layer.
28. a making be self-aligned to the active area of deep trench and shallow trench isolation from technology, this technology comprises:
The substrate that has nitride layer from the teeth outwards is provided;
By nitride and substrate, make at least one pair of adjacent deep trench;
On the partial sidewall at least of each groove, make oxide collar;
Filling groove;
Make the top surface of trench filling recessed;
Part groove neck ring is corroded;
At deposit bar material on the trench filling and on the recessed groove neck ring;
Deposited oxide layer on the exposed surface of the nitride layer on bar material, substrate and the substrate;
This structure is flattened,, make oxide skin(coating) only be retained in the groove so that remove the partial oxide layer;
Deposit photoresist on this structure;
Photoresist is carried out graphically, so that partial oxide layer in the exposure groove and the nitride layer on the substrate, making at least, the reserve part photoresist covers deep trench;
Optionally remove the part nitride layer on the substrate between each groove;
Optionally remove the part substrate between each groove;
In by the interval that nitride layer produced on the substrate of removing between each groove, and in the partial oxide layer in each groove, deposited oxide, and oxide flattened;
Removing remains in the nitride on the substrate surface; And
On a deep trench, make transistor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB001040642A CN1156008C (en) | 2000-03-16 | 2000-03-16 | Isolated capacitor trench top medium for self-aligning device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB001040642A CN1156008C (en) | 2000-03-16 | 2000-03-16 | Isolated capacitor trench top medium for self-aligning device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1332477A true CN1332477A (en) | 2002-01-23 |
| CN1156008C CN1156008C (en) | 2004-06-30 |
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ID=4577194
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB001040642A Expired - Fee Related CN1156008C (en) | 2000-03-16 | 2000-03-16 | Isolated capacitor trench top medium for self-aligning device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1156008C (en) |
-
2000
- 2000-03-16 CN CNB001040642A patent/CN1156008C/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| CN1156008C (en) | 2004-06-30 |
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