CN1332288C - Computer device CPU time-pulse speed real-time adjusting method - Google Patents
Computer device CPU time-pulse speed real-time adjusting method Download PDFInfo
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- CN1332288C CN1332288C CNB2004100150607A CN200410015060A CN1332288C CN 1332288 C CN1332288 C CN 1332288C CN B2004100150607 A CNB2004100150607 A CN B2004100150607A CN 200410015060 A CN200410015060 A CN 200410015060A CN 1332288 C CN1332288 C CN 1332288C
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Abstract
The present invention relates to a method for adjusting the time pulse speed of a central processing unit of a computer device in real time; the time pulse speed adjustment function of the central processing unit is activated by a computer system basic input/output system of the computer device. The present invention is characterized in that a micro controller detects whether a time pulse speed adjustment event signal is generated; when the micro controller detect that the time pulse speed adjustment event signal exists, the micro controller generates a system management signal to the computer system basic input/output system (BIOS) of the computer device; the computer system basic input/output system activates the time pulse speed adjustment function of the central processing unit through a time pulse speed adjustment message value MSR provided by the central processing unit so that the central processing unit operates at low time pulse speed.
Description
Technical field
The present invention is about a kind of real-time method of adjustment of central processing unit clock pulse speed of computer apparatus, particularly about a kind of method that activates the clock pulse speed adjustment function of this central processing unit by the computer system ROM-BIOS.
Background technology
Notebook computer or portable computer generally use in all trades and professions, and this notebook computer makes the function of notebook computer more powerful in conjunction with miscellaneous equipment (for example mobile communication equipment, wireless network etc.) again.Because notebook computer focuses on portable characteristic, so can be different aspect many behaviour's part characteristics and hardware design with general desktop computer.
Typical notebook computer comprises that a CPU (central processing unit) is arranged, computer system ROM-BIOS (System Basic Input Output System, SYS-BIOS), internal memory, the data storage facility, north and south bridge chip group (North Bridge/South Bridge), display interface, bus, keyboard controller (KeyboardController, assembly such as KBC), wherein include in this keyboard controller a built-in micro controller (EmbeddedMicro-controller) and keyboard ROM-BIOS (Keyboard Basic Input Output System, KB-BIOS), the interface circuit of internal memory and other specific function.The working power of this portable computer is supplied by battery, and the battery status of this battery can be detected by the battery status detecting interface of keyboard controller.
Under the situation of no external power supply, the electrical power for operation of notebook computer need rely on battery and supply, and is one of important topic for notebook computer so how to design the framework with electricity-saving function.Moreover, because notebook computer is focused on the design of compact volume, thus aspect radiating efficiency, tend to relatively poor, so heat dissipation problem also is the important consideration point of notebook computer when designing.In the present known practice, for power consumption that reduces central processing unit and the heat generation that reduces this central processing unit, the general practice is to reduce the clock pulse speed of central processing unit, clock pulse speed and power consumption are linear, so, can reach and reduce power consumption and reduce heat as long as central processing unit works under the lower clock pulse speed.
Moreover, in the notebook computer of lower-order, may be for the central processing unit (Desktop CPU) that adopts desktop computer of considering of cost, the heat radiation degree of the central processing unit of desktop computer and power consumption degree all aim at notebook computer than some and that the central processing unit (Mobile CPU) that designs comes is poor, and power consumption is also bigger, but price is comparatively cheap, so when the product of this type of design, it is an indispensable function that clock pulse speed adjustment (CPU Throttling) function of central processing unit then becomes.Clock pulse speed by central processing unit is adjusted, and can reduce the temperature of central processing unit on the one hand, also can reduce the power consumption of central processing unit on the one hand.
In the currently used technology, in order to reach the function that aforementioned central processing unit clock pulse speed is adjusted, its framework mostly is to get in touch with central processing unit by the north and south bridge chip group in the computer system (North Bridge/South Bridge) with the embedded micro controller (Embedded) in the keyboard controller (Keyboard Controller).When the micro controller of this keyboard controller detects clock pulse speed adjustment event conditions, promptly produce a clock pulse and adjust signal stopping clock signal pin position (STOP CLOCK PIN) and indicating for example 50% ratio to this central processing unit by north and south bridge chip group in the computer system and central processing unit.This expression central processing unit during this period of time only can receive the clock pulse speed of half, and this moment, central processing unit was promptly carried out the function that clock pulse speed is adjusted, to reduce the temperature and the power consumption of central processing unit.
Yet,, had some shortcomings to get in touch by north and south bridge chip group in the computer system and central processing unit in the conventional art that reaches the adjustment of clock pulse speed.For example the clock pulse speed adjustment of central processing unit is not done optimization or design when not good when north and south bridge chip group, the central processing unit clock pulse speed of chipset is adjusted function may cause some unpredictable mistakes.Moreover fixing north and south bridge chip group clock pulse speed adjustment cycle (cycle) can produce noise on other nextport hardware component NextPort, if this frequency just be people's ear can uppick scope this noise effect heal and become obvious.
Therefore, adjust function, demand that then ought more can be realistic if can design a kind of clock pulse speed that need can not realize central processing unit by the north and south bridge chip group support in the computer system.Moreover, if can be with detecting real-time, adjust the control of central processing unit clock pulse speed in real time, then more can make the clock pulse speed of central processing unit adjust function and more become perfect.
Summary of the invention
Fundamental purpose of the present invention promptly provides a kind of method of clock pulse speed adjustment of central processing unit, and it can realize that the clock pulse speed of central processing unit is adjusted function under the framework that need not support by the north and south bridge chip group in the computer system.
Whether sometimes the technology used in the present invention means are to detect rapid pulse degree adjustment event signal generation by the micro controller of keyboard controller, when detecting clock pulse speed adjustment event signal, produce the computer system ROM-BIOS (BIOS) of a system management signal by this micro controller to this computer apparatus, this computer system ROM-BIOS is adjusted the clock pulse speed adjustment function that message numerical value MSR activates this central processing unit by the clock pulse speed that this central processing unit provided again, makes this central processing unit with lower clock pulse speed running.
Via the technology used in the present invention means, can be so that the present invention be when the clock pulse speed that realizes central processing unit is adjusted function, need not support by the north and south bridge chip group in the computer system, so can simplify this computer system and transmit at signal, and the real-time clock pulse speed that can realize opening or close central processing unit is adjusted function, can solve simultaneously north and south bridge and the adjustment of central processing unit clock pulse speed and support the bad situation that maybe may produce unpredictable mistake, also can solve generation because of north and south bridge chip group cycle noise when central processing unit carries out clock pulse speed adjustment function.
Description of drawings
Fig. 1 shows the computer system functional block diagram that the real-time method of adjustment of central processing unit clock pulse speed of computer apparatus of the present invention is cooperated;
Signal schematic representation when Fig. 2 shows the present invention in commission the clock pulse speed of central processor is adjusted in real time between associated component;
Fig. 3 shows the control flow chart of the real-time method of adjustment of central processing unit clock pulse speed of computer apparatus of the present invention.
Embodiment
At first consult shown in Figure 1ly, it shows the computer system functional block diagram that the real-time method of adjustment of central processing unit clock pulse speed of computer apparatus of the present invention is cooperated.This computer apparatus 1 includes a CPU (central processing unit) 11, its system bus 12 is connected with one first bridge 13 (also be called main bridge Host Bridge or be called north bridge North Bridge), and a primary memory 14 is connected in this system bus 12 via this first bridge 13.First bridge 13 also is connected with a computer system ROM-BIOS 15 (System BasicInput/Output System is called for short System BIOS).
One pci bus 16 (Peripheral Component Interconnect) is connected in this first bridge 13, and can link various PCI devices 17 on this pci bus 16.One second bridge 18 (being called south bridge South Bridge again) is connected in this pci bus 16, and then connects an expansion bus (Extended Bus), and for example isa bus 19.
One keyboard controller 2 is connected in this isa bus 19.Mainly include an embedded micro controller 21 in this keyboard controller 2, can connect a key board unit 22.This micro controller 21 also is connected with a keyboard ROM-BIOS 23 (Keyboard Basic Input/Output System, Keyboard BIOS).
This computer apparatus 1 is if a notebook computer, and a battery 3 (for example present intelligent battery Smart Battery that uses always) is connected to this micro controller 21 via the System Management Bus (not shown) of a battery detecting interface 31 and this keyboard controller 2 inside.
Moreover, one temperature sensor 4 is configured in the CPU (central processing unit) 11 of this computer apparatus 1, in order to detecting the practical operation temperature of this CPU (central processing unit) 11, and deliver to the System Management Bus of this keyboard controller 2 via the analog temperature signal that an analog-to-digital converter 41 will sense.
This keyboard controller 2 includes the isa bus 19 that a main interface (Host Interface) is connected in this computer apparatus 1, with as carrying out the interface of data transmission with this CPU (central processing unit) 11.This keyboard controller 2 can produce the CPU (central processing unit) 11 of a system management signal SMI (System Management Interrupt) to this computer apparatus 1 via System Management Controller.When the executive system management function, after this keyboard controller 2 deposits a numerical value buffer of an inside in, can produce this system management signal SMI then to CPU (central processing unit) 11.CPU (central processing unit) 11 can respond this system management signal SMI according to being stored in the system management sign indicating number (System Management Code) in its primary memory 14 in advance and handle the execution action of the numerical value representative in these keyboard controller 2 existing buffers then.
Consult shown in Figure 2, the signal schematic representation when it shows the present invention in commission the clock pulse speed of central processor is adjusted in real time between associated component.When the micro controller in the keyboard controller 2 21 detects clock pulse speed adjustment event signal (Throttling Event), for example the operating temperature of CPU (central processing unit) 11 surpasses predetermined threshold value or battery powered mode (Battery mode) etc., and this micro controller 21 can produce the computer system ROM-BIOS 15 of a system management signal SMI notice computer apparatus 1.
When the ROM-BIOS 15 of computer system receive system management signal smi signal that this micro controller 21 is sent here after, the inside clock pulse speed that this computer system ROM-BIOS 15 is promptly provided by central processing unit 11 is adjusted the clock pulse speed that message numerical value MSR opens central processing unit and is adjusted function.With Intel P4 Northwood central processing unit is example, it is 19A that its inner clock pulse speed is adjusted message numerical value MSR, so system's ROM-BIOS 15 can make central processing unit 11 reach the function that clock pulse speed is adjusted directly by reading message numerical value (RDMSR) and writing the MSR message numerical value that this central processing unit 11 is changed in these two instructions of message numerical value (WRMSR).
When the clock pulse speed adjustment function of this central processing unit 11 was unlocked, central processing unit 11 can operate with lower clock pulse speed, and then reached the power consumption that reduces central processing unit 11 and slow down the function that temperature rises.Because among the present invention, computer system ROM-BIOS BIOS is that the inside clock pulse speed that provides by central processing unit is adjusted the open and close that MSR reaches clock pulse speed adjustment function, so all other type central processing units of supporting inner clock pulse speed to adjust function all can adopt technology of the present invention.
Consult shown in Figure 3ly, it shows the control flow chart that the speed of central processing unit of the present invention is adjusted in real time, cooperate simultaneously now aforementioned circuit figure to control flow of the present invention do an explanation as after.
At first, after computer apparatus 1 was finished system's active program (step 100), whether sometimes the micro controller 21 of keyboard controller 2 promptly continued detecting rapid pulse degree adjustment event signal (step 101).As previously mentioned, this clock pulse speed adjusts that the temperature that incident for example can include central processing unit 11 rises to a certain default threshold value, the situations such as (Battery mode) that switches to battery powered mode, all can produce this clock pulse speed and adjust event signal, and deliver to keyboard controller 2.
When the micro controller 21 of keyboard controller 2 has detected any clock pulse speed adjustment event signal generation, this micro controller 21 can produce a system management signal smi signal (step 102), and this system management signal smi signal is sent to the ROM-BIOS 15 (step 103) of this computer system.
After the ROM-BIOS 15 of computer system is received the system management signal smi signal that this micro controller 21 sent here, the inside clock pulse speed that this computer system ROM-BIOS 15 is promptly provided by central processing unit 11 is adjusted the clock pulse speed adjustment function (step 104) that message numerical value MSR opens central processing unit 11, to adjust the work time pulse speed of this central processing unit 11.That is when the clock pulse speed adjustment function of this central processing unit 11 was unlocked, central processing unit 11 can operate with lower clock pulse speed, and then reached power consumption that reduces central processing unit 11 and the rising that slows down temperature.
Continue to exist if this clock pulse speed is adjusted event signal, then this central processing unit 11 promptly is under the low clock pulse speed always and operates.And when this clock pulse speed is adjusted the event signal termination (step 105), then this central processing unit 11 can be replied again under the original normal clock pulse speed and be operated.
This computer system ROM-BIOS 15 (POST) during computer apparatus is in start, can be for some time the SMI request of being sent of micro controller 21 in can't services key disk controller 2, computer system ROM-BIOS 15 can be taked the mode of poll (Polling) during this section, initiatively inquire the state of micro controller 21 clock pulse speed adjustment at that time incident, but such state time is very short, can influence the real-time of the functional operation of clock pulse speed adjustment hardly.
In addition, when this computer system ROM-BIOS 15 at computer apparatus by the S3 sleep pattern to (Resume from S3) between waking, also can be for some time the SMI request of being sent of micro controller 21 in can't services key disk controller 2.This S3 sleep pattern is a kind of slower pattern of delayed recovery of waking up.Under this pattern, except Installed System Memory, other all data about central processing unit, high-speed cache and chipset all can be lost.Hardware can the reserved memory data and store some central processing unit and the configuration of L2 high-speed cache in.System's ROM-BIOS 15 also can be taked the mode of poll (Polling) during this section, initiatively inquire the state of micro controller 21 clock pulse speed adjustment at that time incident, but such state time is very short, almost also can not influence the real-time of the functional operation of clock pulse speed adjustment.
Claims (7)
1. the real-time method of adjustment of central processing unit clock pulse speed of a computer apparatus, the computer system ROM-BIOS by this computer apparatus activates the clock pulse speed of this central processing unit and adjusts function, and it is characterized in that: this method comprises the following steps:
(a) computer apparatus carries out system's active program;
Sometimes whether (b) detecting by a micro controller, rapid pulse degree adjustment event signal takes place;
(c) when detecting clock pulse speed adjustment event signal, produce a system management signal by this micro controller;
The system management signal that (d) will produce is sent to the computer system ROM-BIOS of this computer apparatus;
(e) after this computer system ROM-BIOS receives this system management signal, promptly adjust the clock pulse speed adjustment function that message numerical value MSR activates this central processing unit, make this central processing unit with lower clock pulse speed running by the clock pulse speed that this central processing unit provided.
2. the real-time method of adjustment of central processing unit clock pulse speed of computer apparatus according to claim 1, it is characterized in that: when the temperature that the generation that this clock pulse speed is adjusted event signal includes central processing unit rises to a certain default threshold value, promptly produce this clock pulse speed and adjust event signal by this micro controller.
3. the real-time method of adjustment of central processing unit clock pulse speed of computer apparatus according to claim 1, it is characterized in that: the generation that this clock pulse speed is adjusted event signal includes when this computer apparatus switches to battery powered mode, promptly produces this clock pulse speed by this micro controller and adjusts event signal.
4. the real-time method of adjustment of central processing unit clock pulse speed of computer apparatus according to claim 1, it is characterized in that: this micro controller is the embedded micro controller of the keyboard controller of this computer apparatus.
5. the real-time method of adjustment of central processing unit clock pulse speed of computer apparatus according to claim 1, it is characterized in that: this computer system ROM-BIOS reads message numerical value MSR and writes the message numerical value MSR that this central processing unit is changed in two instructions of message numerical value MSR by this central processing unit, makes central processing unit reach the function that clock pulse speed is adjusted.
6. the real-time method of adjustment of central processing unit clock pulse speed of computer apparatus according to claim 1, it is characterized in that: in this step (a), carry out in computer apparatus during the start of system's active program, this computer system ROM-BIOS also comprises the step of initiatively inquiring the state of micro controller clock pulse speed adjustment at that time incident with polling mode.
7. the real-time method of adjustment of central processing unit clock pulse speed of computer apparatus according to claim 1, it is characterized in that: between waking, this computer system ROM-BIOS also comprises the step of initiatively inquiring the state of micro controller clock pulse speed adjustment at that time incident with polling mode to this computer apparatus by the S3 sleep pattern.
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| Application Number | Priority Date | Filing Date | Title |
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| CNB2004100150607A CN1332288C (en) | 2004-01-09 | 2004-01-09 | Computer device CPU time-pulse speed real-time adjusting method |
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| CNB2004100150607A CN1332288C (en) | 2004-01-09 | 2004-01-09 | Computer device CPU time-pulse speed real-time adjusting method |
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| CN1332288C true CN1332288C (en) | 2007-08-15 |
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| CN103064484B (en) * | 2011-10-24 | 2016-04-13 | 神讯电脑(昆山)有限公司 | Electronic system and preheat method and apparatus |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1168501A (en) * | 1996-01-17 | 1997-12-24 | 德克萨斯仪器股份有限公司 | Method and system for controlling computer operation in response to central processing unit operating characteristics |
| WO2001033322A2 (en) * | 1999-11-05 | 2001-05-10 | Intel Corporation | Sleep state transitioning |
| CN1462925A (en) * | 2002-05-31 | 2003-12-24 | 广达电脑股份有限公司 | Dynamic method for adjusting consumption power of computer system |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1168501A (en) * | 1996-01-17 | 1997-12-24 | 德克萨斯仪器股份有限公司 | Method and system for controlling computer operation in response to central processing unit operating characteristics |
| WO2001033322A2 (en) * | 1999-11-05 | 2001-05-10 | Intel Corporation | Sleep state transitioning |
| CN1462925A (en) * | 2002-05-31 | 2003-12-24 | 广达电脑股份有限公司 | Dynamic method for adjusting consumption power of computer system |
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