CN1329994C - Deep channel type capacity and structure of single-transistor static random access internal storing unit - Google Patents
Deep channel type capacity and structure of single-transistor static random access internal storing unit Download PDFInfo
- Publication number
- CN1329994C CN1329994C CNB2004100079749A CN200410007974A CN1329994C CN 1329994 C CN1329994 C CN 1329994C CN B2004100079749 A CNB2004100079749 A CN B2004100079749A CN 200410007974 A CN200410007974 A CN 200410007974A CN 1329994 C CN1329994 C CN 1329994C
- Authority
- CN
- China
- Prior art keywords
- trap
- ion
- type
- deep
- channel capacitor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 230000003068 static effect Effects 0.000 title description 13
- 239000003990 capacitor Substances 0.000 claims abstract description 44
- 239000004065 semiconductor Substances 0.000 claims abstract description 21
- 230000015654 memory Effects 0.000 claims abstract description 19
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 18
- 229920005591 polysilicon Polymers 0.000 claims abstract description 18
- 238000002347 injection Methods 0.000 claims abstract description 14
- 239000007924 injection Substances 0.000 claims abstract description 14
- 150000002500 ions Chemical class 0.000 claims description 47
- 239000000758 substrate Substances 0.000 claims description 31
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 11
- 230000004888 barrier function Effects 0.000 claims description 11
- 238000003973 irrigation Methods 0.000 claims description 9
- 230000002262 irrigation Effects 0.000 claims description 9
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 9
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 5
- 238000002955 isolation Methods 0.000 claims 1
- 230000005611 electricity Effects 0.000 abstract description 4
- 239000010410 layer Substances 0.000 description 45
- 238000000034 method Methods 0.000 description 26
- 229920002120 photoresistant polymer Polymers 0.000 description 11
- 229910052785 arsenic Inorganic materials 0.000 description 9
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 9
- 239000011521 glass Substances 0.000 description 8
- 238000009413 insulation Methods 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 239000011229 interlayer Substances 0.000 description 4
- 238000003860 storage Methods 0.000 description 4
- 238000005530 etching Methods 0.000 description 3
- 238000002513 implantation Methods 0.000 description 3
- RZVAJINKPMORJF-UHFFFAOYSA-N Acetaminophen Chemical compound CC(=O)NC1=CC=C(O)C=C1 RZVAJINKPMORJF-UHFFFAOYSA-N 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 239000005297 pyrex Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 241000167880 Hirundinidae Species 0.000 description 1
- 239000005388 borosilicate glass Substances 0.000 description 1
- 230000001413 cellular effect Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000006698 induction Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Images
Abstract
The present invention relates to a deep channel capacity and memory unit structure, which comprises a first conduction type semiconductor basement with a main surface, a second conduction type ion injection well with a well junction depth, which is arranged on the main surface of the semiconductor basement, a grid dielectric electricity layer arranged on the ion injection well, a grid arranged on the grid dielectric electricity layer, a first conduction type heavily-doped region arranged in the ion injection well on one side of the grid, a first conduction type lightly-doped region arranged in the ion injection well on the other side which is opposite to the grid and the first conduction type heavily-doped region, and a deep channel capacitor which is vertical to the main surface, is formed in the semiconductor basement and extends downwards to exceed the well junction depth of the ion injection well to a preset depth. The deep channel capacitor comprises an ion outwards diffusing well which is formed on the lower part of the channel capacitor and is communicated and connected with the ion injection well. The deep channel capacitor comprises a polysilicon electrode, and the dielectric electricity layer of the capacitor and an insulating layer on the upper end of the channel are isolated in an electric property way with the first conduction type lightly-doped region, the ion injection well, and the outwards diffusing well.
Description
Technical field
The present invention refers to a kind of deep trenches formula single-transistor random access memory (1T-RAM) assembly and method for making thereof especially about a kind of deep trenches formula (deep-trench) semiconductor memory cellular construction and method for making thereof.According to preferred embodiment of the present invention, the outdiffusion trap (out diffusion well) that the utilization of deep trenches formula single-transistor random access memory assembly is formed at the channel capacitor bottom injects trap (implantation ionwell) perforation binding with ion, obtains higher capacitance (Cs) and low-leakage current (leakage) characteristic thus.
Background technology
The random access memory that general computer system is used can be divided into dynamically and static random access memory, its difference is that position of DRAM (Dynamic Random Access Memory) only uses a transistor, need periodically to replenish power supply (refresh), data can not run off in the internal memory to keep, 4 or 6 transistors (4T/6T) composition are used in each position of static random access memory (SRAM), do not need periodically to replenish power supply, speed is very fast, and price is also higher.Main storage in the computer generally all is to use DRAM, and high-speed cache (cache memory) then is to adopt SRAM.
Along with scientific and technological progress, Portable small-sized electronic product such as mobile phone, PDA(Personal Digital Assistant) etc. are also used by masses more and more at large, these electronic products are subject to need the arrange in pairs or groups system single chip embedded memory device of high density and efficiency low-voltage of battery and volume, therefore develop single-transistor static random access memory (1T-SRAM) assembly that as known to the sector person.This class single-transistor static random access memory assembly and tradition are that by six static random access memories that transistor constituted (six-transistor SRAM) are different it has higher component density, preferable operation usefulness, more power saving and the circuit design simplified, and can utilize pure logic (logic) processing procedure to make or utilize to embed (embedded) internal memory processing procedure and make.
Single-transistor static random access memory (1T-SRAM) technology uses the electric capacity of horizontal to constitute the memory bits unit, act on similarly to standard six layer transistor SRAMs, but only accounts for half die area of pact, and storage density is higher about four times than standard SRAM.The practice is electric capacity to be converted near an angle of 90 degrees embed in the groove or hole that is etched on the silicon, thereby has reduced the storage element size.But, must do some change to making processing procedure:increase by one time photomask, and add new etching and implantation step, the relevant prior art of so that form the hole that can embed electric capacity 2/3 volume in order to make up storage element. can " DRAM has part and is made in capacitance structure and method of operating (DRAM cell having a capacitor structurefabricated partially in a cavity and method for operating same) thereof in the hole with reference to No. the 6573548th, all United States Patent (USP) of MoSys company (Monolithic System Technology) No. 6028804 " method and the device (Method and apparatus for 1T-SRAM compatiblememory) of the compatible internal memory of 1T-SRAM " and United States Patent (USP).
Yet existing single-transistor static random access memory (1T-SRAM) is even use its unit memory cell area occupied of state-of-the-art process technique still to reach 0.5～0.6 μ m
2, and the processing procedure cost still exceeds about 4% with respect to the standard logic processing procedure.In addition, existing single-transistor static random access memory (1T-SRAM) has only a spot of capacitance (about 3～7fF) of increasing.Moreover the poor insulativity between adjacent two electric capacity also is existing single-transistor static random access memory (1T-SRAM) major defect.Hence one can see that, and these single-transistor static random access memory (1T-SRAM) technology still have the space of further improvement.
Summary of the invention
In view of the above, main purpose of the present invention is to provide a kind of deep trenches formula single-transistor static random access memory (1T-SRAM) assembly and method for making thereof.
According to preferred embodiment of the present invention, the present invention discloses a kind of deep channel capacitor memory cell architectures, includes one first conductivity type (first conductivity type) Semiconductor substrate, has a first type surface (main surface); One second conductivity type (second conductivity type) ion injects trap, has a trap and connects the face degree of depth (well junction depth), is located on this first type surface of this Semiconductor substrate; One gate dielectric is located at this ion and is injected on the trap; One grid is located on this gate dielectric; One first conductivity type heavy doping (heavily doped) district, this ion of being located at grid one side injects trap; One first conductivity type light dope (lightly doped) district, this ion of being located at the grid opposite side opposite with this first conductivity type heavily doped region injects trap; An and deep channel capacitor, vertically this first type surface is formed at the trap that also deeply surpasses this ion injection trap in this Semiconductor substrate downwards and connects the face degree of depth to a desired depth, for example 3 to 5 microns dark, wherein this deep channel capacitor includes an ion outdiffusion trap (ion outdiffusion well), it is formed at the bottom of this channel capacitor, and inject trap with this ion and connect and link (merge), wherein this deep channel capacitor includes a polysilicon electrode in addition, and it is by a capacitance dielectric layer (capacitor dielectric) and irrigation canals and ditches upper end insulating barriers (trench top insulationlayer) and this first conductivity type light doping section, this ion injects trap and this outdiffusion trap is electrically isolated.
According to preferred embodiment of the present invention, the ion outdiffusion trap that the utilization of deep trenches formula single-transistor static random access memory assembly is formed at the channel capacitor bottom injects trap (implantation ion well) perforation binding with the ion that is formed at semiconductor substrate surface, obtains higher capacitance (Cs) and low-leakage current (leakage) characteristic thus.
Description of drawings
Fig. 1 to Fig. 9 shows the generalized section of making deep trenches formula memory subassembly according to preferred embodiment of the present invention.
The figure number explanation
10 Semiconductor substrate, 11 surfaces, 12 lining silicon oxide layers
14 lining silicon nitride layers, 15 deep trenches, 16 deep trenches
20 N type traps, 21 arsenic silex glasss, 25 flush type N
+Doped region
32 capacitance dielectric layers, 34 doped polysilicon layers, 45 fossaperturates
46 swallows, 52 dielectric layers, 54 photoresist layers
55 openings, 60 shallow-channel insulation openings, 62 high-density silicon oxide skin(coating)s
72 grid oxic horizons, 81 grids, 82 grids
83 grids, 84 grids, 90 interlayer dielectric layers
100 layings, 101 P
+Source/drain 102 P type lightly doped drains
105 insulating barriers, 120 deep channel capacitors, 140 deep channel capacitors
201 share contact plunger 202 bit line connectors
Embodiment
At first, see also Fig. 9, the present invention includes one first conductivity type (first conductivity type) Semiconductor substrate 10 about a kind of deep channel capacitor memory cell architectures, has a first type surface (main surface) 11; One second conductivity type (second conductivity type) ion injects trap 20, has a trap and connects the face degree of depth (well junction depth), is located on this first type surface 11 of this Semiconductor substrate 10; One gate dielectric 72 is located at this ion and is injected on the trap 20; One grid 81 is located on this gate dielectric 72; One first conductivity type heavy doping (heavily doped) district 101, this ion of being located at grid 81 1 sides injects trap 20; One first conductivity type light dope (lightly doped) district 102 is located at this ion injection trap 20 of the opposite opposite side of grid 81 and this first conductivity type heavily doped region 101; An and deep channel capacitor 120, vertically this first type surface 11 is formed at the trap that also deeply surpasses this ion injection trap 20 in this Semiconductor substrate 10 downwards and connects the face degree of depth to a desired depth, for example 3 to 5 microns dark, wherein this deep channel capacitor 120 includes an ion outdiffusion trap (ion outdiffusion well) 25, it is formed at the bottom of this channel capacitor 120, and inject trap 20 with this ion and connect and link (merge), wherein this deep channel capacitor 120 includes a polysilicon electrode 34 in addition, and it is by a capacitance dielectric layer (capacitor dielectric) 32 and one irrigation canals and ditches upper end insulating barriers (trenchtop insulation layer) 105 and this first conductivity type light doping section 102, this ion injects trap 20 and this outdiffusion trap 25 is electrically isolated.
See also Fig. 1 to Fig. 9, Fig. 1 to Fig. 9 shows the generalized section of making advanced deep trenches formula (deep-trench) memory subassembly according to preferred embodiment of the present invention.As shown in Figure 1, at first provide a substrate 10, for example P type doped silicon substrate is formed with a N type trap 20 in it.The trap of N type trap 20 connects the face degree of depth and is about 0.5 to 1.5 micron (micrometer), is preferably about 1 micron.Then, utilize prior art, for example photoetching (lithographic process) and dry ecthing are passed N type trap 20 and are formed and be about 3 to 5 microns two adjacent deep trenches (deep trench) 15 and 16 about (being preferably 3.5 microns) from the surface 11 of P type substrate 10 deeply in deep-cutting downwards along a surface 11 of substrate 10.The technology of digging out deep trenches in silicon substrate 10 is that the sector person knows, can utilize photoresist and be deposited on laying 100 on the surface of silicon, for example serve as a contrast silicon oxide layer 12 and lining silicon nitride layer 14, as etch shield, (reactive ion etching, RIE) processing procedure carries out it in the complex reaction ion(ic) etching.
Then, as shown in Figure 2, high concentration N is carried out in the deep trenches 15 of the degree of depth on about 4000 to 6000 Izod right sides and 16 surperficial sidewalls and bottom under distance substrate 10 surfaces
+Mix, (arsenic silicate glass ASG), drives in (therma ldrive-in) with hot processing procedure to for example first deposited arsenic silex glass subsequently, or directly deposits the polysilicon layer of high-concentration dopant.According to preferred embodiment of the present invention, prior to deep trenches 15 and 16 surperficial sidewalls and bottom deposit one deck arsenic silex glass 21, in deep trenches 15 and 16, insert photoresist layer (figure does not show) then, this photoresist layer of etch-back is to the predetermined degree of depth, for example apart from the substrate 10 surperficial degree of depth on about 4000 to 6000 Izod right sides down, remove the arsenic silex glass 21 that is not covered again by this photoresist layer, after removing photoresist layer, drive in processing procedure with heat N type admixture is diffused in the substrate 10 in the deep trenches 15 that contacts with arsenic silex glass 21 and 16 by arsenic silex glass 21, form an ion outdiffusion trap (ion out diffusion well) thus or be called flush type (buried) N
+Doped region 25.At last, arsenic silex glass 21 is removed.As previously mentioned, in other preferred embodiment of the present invention, arsenic silex glass 21 can also be replaced by heavily doped polysilicon layer, at this moment, forms flush type N
+Behind the doped region 25, heavily doped polysilicon layer can be removed, and it is kept somewhere in deep trenches 15 and 16.By finding out especially among the figure, the present invention is formed on the flush type N of deep trenches 15 and 16 bottoms
+ Doped region 25 is to link up mutually with N type trap 20.
As shown in Figure 3, then on laying 100 and deep trenches 15 and 16 inwalls, form a capacitance dielectric layer 32, silica-silicon-nitride and silicon oxide (ONO) dielectric layer for example, but be not limited thereto.In deep trenches 15 and 16, fill up N doped polysilicon layer 34 subsequently.
As shown in Figure 4, then etch-back doped polysilicon layer 34 is lower than substrate 10 surfaces desired depth down to deep trenches 15 and 16, and for example 100 to 400 dusts are preferably 200 to 300 dusts.Subsequently, remove the capacitance dielectric layer 32 that comes out in the wet etching mode again.At this moment, respectively form fossaperturate 45 and 46 in deep trenches 15 and 16.At this moment, roughly finish the making of deep channel capacitor 120 and 140.
As shown in Figure 5, then carry out logic shallow-channel insulation module (logic STI module) processing procedure.According to preferred embodiment of the present invention, at first on substrate 10, deposit a dielectric layer 52, for example (borosilicate glass BSG), and fills up fossaperturate 45 and 46 to Pyrex.Then on dielectric layer 52 with gold-tinted program defining photoresist layer 54, it has an opening 55, definition shallow-channel insulation zone.In other embodiments, between dielectric layer 52 and the photoresist layer 54 one deck anti-reflecting layer can be arranged, but it is not an emphasis of the present invention.Then, utilize photoresist layer 54 and dielectric layer 52 as etch shield again, doped polysilicon layer 34 and capacitance dielectric layer 32 via the 55 downward etching dielectric layers 52 of the opening in the photoresist layer 54, laying 100, substrate 10, part, remove remaining photoresist layer 54 and dielectric layer 52 again, promptly form shallow-channel insulation opening 60, as shown in Figure 6.
Then, as shown in Figure 7, carry out a high density plasma enhanced chemical vapor deposition (high-densityplasma chemical vapor deposition, HDPCVD) processing procedure, deposition one high-density silicon oxide (HDP oxide) layer 62 on substrate 10, and fill up shallow-channel insulation opening 60.(chemical mechanical polishing, CMP) processing procedure utilize laying 100 to stop layer for grinding, and make substrate 10 flattening surfaces to carry out a cmp again.Remaining laying 100 is removed, and carries out the standard logic processing procedure then, goes up the grid oxic horizon 72 of growing up and making new advances in the thermal oxidation mode in substrate 10 surfaces that expose, and its thickness is about 10 to 100 dusts.
As shown in Figure 8, follow deposit spathic silicon layer on grid oxic horizon 72, and polysilicon layer is defined as grid structure 81,82,83 and 84 with existing gold-tinted and etch process.And then be that ion injects shielding and carries out P type lightly doped drain (P-type lightlydoped drain/source abbreviates PLDD as) 102 processing procedures with grid structure 81,82,83 and 84, finish after the making of sidewall, utilize again one suitably shielding carry out P
+Source/drain 101 heavy doping ion are injected, and so promptly finish the logic processing procedure of transistor part.Wherein by the P raceway groove of control grid 81 belows can access deep channel capacitor 120 data, and by the P raceway groove of control grid 84 belows can access deep channel capacitor 140 data.Then, and deposition one interlayer dielectric layer on Semiconductor substrate 10 (inter layer dielectric, ILD) 90, it can be Pyrex, boron-phosphorosilicate glass, silicon dioxide or the like.
At last, as shown in Figure 9, then utilize gold-tinted and etch process in interlayer dielectric layer 90, to form contact openings (contact opening), in contact openings, insert conductive material then, for example the tungsten metal forms so respectively and shares contact plunger (share contact) 201, and it passes the insulating barrier 105 of polysilicon electrode 34 tops that are positioned at deep channel capacitor 120 and 140 and is electrically connected with the polysilicon electrode 34 of deep channel capacitor 120 and 140, and bit line connector 202, itself and P
+Source/drain 101 is electrically connected.During operation, provide a grid voltage to give grid 81, the horizontal P raceway groove of grid 81 belows is opened, and give P through bit line connector 202 inputs one bit-line voltage
+Source/drain 101 is pressed on polysilicon electrode 34 via connector 201 inputs one negative electricity, simultaneously thus at P type lightly doped drain (PLDD) 102 and flush type (buried) N
+Induction forms vertical P raceway groove between the doped region 25, and under these conditions, the hole is via P
+The horizontal P raceway groove of source/drain 101, grid 81 belows, P type lightly doped drain (PLDD) 102, vertical P raceway groove, and arrive flush type N
+ Doped region 25.
The above only is preferred embodiment of the present invention, and all equalizations of being done according to the present patent application claim change and modify, and all should belong to the covering scope of patent of the present invention.
Claims (14)
1, a kind of deep channel capacitor memory cell architectures is characterized in that, includes:
One first conductive-type semiconductor substrate has a first type surface;
One second conduction type ion injects trap, has a trap and connects the face degree of depth, is located on this first type surface of this Semiconductor substrate;
One gate dielectric is located at this ion and is injected on the trap;
One grid is located on this gate dielectric;
One first conductivity type heavily doped region, this ion of being located at this grid one side injects trap;
One first conductivity type light doping section, this ion of being located at this grid opposite side opposite with this first conductivity type heavily doped region injects trap; And
One deep channel capacitor, vertically this first type surface is formed at this trap that also deeply surpasses this ion injection trap in this Semiconductor substrate downwards and connects the face degree of depth to a desired depth, wherein this deep channel capacitor includes an ion outdiffusion trap, it is formed at the bottom of this channel capacitor, and inject trap with this ion and connect and link, wherein this deep channel capacitor includes a polysilicon electrode in addition, and it is by a capacitance dielectric layer and irrigation canals and ditches upper end insulating barrier and this first conductivity type light doping section, this ion inject trap and this outdiffusion trap is electrically isolated.
2, deep channel capacitor memory cell architectures as claimed in claim 1 is characterized in that, this first conductivity type is the P type, and this second conductivity type is the N type.
3, deep channel capacitor memory cell architectures as claimed in claim 1 is characterized in that, the upper end of this ion outdiffusion trap is apart from these first type surface 4000 to 6000 dusts of this Semiconductor substrate.
4, deep channel capacitor memory cell architectures as claimed in claim 1 is characterized in that, this deep channel capacitor is formed at the interior degree of depth of this Semiconductor substrate greater than 3 microns.
5, deep channel capacitor memory cell architectures as claimed in claim 1 is characterized in that, this capacitance dielectric layer is silica-silicon-nitride and silicon oxide dielectric layer.
6, deep channel capacitor memory cell architectures as claimed in claim 1 is characterized in that, this irrigation canals and ditches upper end insulating barrier is a silicon oxide layer.
7, deep channel capacitor memory cell architectures as claimed in claim 6 is characterized in that, the thickness of this irrigation canals and ditches upper end insulating barrier is 100 to 400 dusts.
8, a kind of deep trenches formula single-transistor sram cell is characterized in that, includes:
One PMOS transistor, being formed at a N type ion injects on the trap, wherein this N type ion injection trap injects with ion and is formed at a P type semiconductor substrate, wherein this PMOS transistor includes a grid and is located at this N type ion and injects on trap, and by a gate dielectric and this N type ion injection trap electrical isolation, one P type heavy doping drain/source, this N type ion of being located at this grid one side injects trap and P type lightly doped drain/source electrode, and this N ion of being located at this grid opposite side opposite with this P type heavy doping drain/source injects trap; And
One deep channel capacitor, be formed at the transistorized side of this PMOS in this Semiconductor substrate, and the trap that deeply surpasses this ion injection trap downwards connects the face degree of depth to a desired depth, wherein this deep channel capacitor includes a N type ion outdiffusion trap, it is formed at the bottom of this channel capacitor, and inject trap with this N type ion and connect and link, wherein this deep channel capacitor includes a polysilicon electrode in addition, and it injects trap by a capacitance dielectric layer and this P type lightly doped drain/source electrode, this N type ion and this N type outdiffusion trap is electrically isolated.
9, deep trenches formula single-transistor sram cell as claimed in claim 8 is characterized in that, this deep trenches formula single-transistor sram cell includes irrigation canals and ditches upper end insulating barrier in addition and is located at this polysilicon electrode top.
10, deep trenches formula single-transistor sram cell as claimed in claim 9 is characterized in that, a contact plunger passes this irrigation canals and ditches upper end insulating barrier and this polysilicon electrode electrical ties.
11, deep trenches formula single-transistor sram cell as claimed in claim 9 is characterized in that, this irrigation canals and ditches upper end insulating barrier is a silicon oxide layer.
12, deep trenches formula single-transistor sram cell as claimed in claim 11 is characterized in that, the thickness of this irrigation canals and ditches upper end insulating barrier is 100 to 400 dusts.
13, deep trenches formula single-transistor sram cell as claimed in claim 8 is characterized in that, this capacitance dielectric layer is silica-silicon-nitride and silicon oxide dielectric layer.
14, deep trenches formula single-transistor sram cell as claimed in claim 8 is characterized in that, this deep channel capacitor is formed at this interior desired depth of this Semiconductor substrate greater than 3 microns.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100079749A CN1329994C (en) | 2004-03-23 | 2004-03-23 | Deep channel type capacity and structure of single-transistor static random access internal storing unit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100079749A CN1329994C (en) | 2004-03-23 | 2004-03-23 | Deep channel type capacity and structure of single-transistor static random access internal storing unit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1674291A CN1674291A (en) | 2005-09-28 |
| CN1329994C true CN1329994C (en) | 2007-08-01 |
Family
ID=35046673
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2004100079749A Expired - Lifetime CN1329994C (en) | 2004-03-23 | 2004-03-23 | Deep channel type capacity and structure of single-transistor static random access internal storing unit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1329994C (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7902608B2 (en) * | 2009-05-28 | 2011-03-08 | International Business Machines Corporation | Integrated circuit device with deep trench isolation regions for all inter-well and intra-well isolation and with a shared contact to a junction between adjacent device diffusion regions and an underlying floating well section |
| CN101908488B (en) * | 2009-06-08 | 2012-11-21 | 尼克森微电子股份有限公司 | Ditching type metal-oxide semiconductor assembly manufacturing method |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6479852B1 (en) * | 2001-10-03 | 2002-11-12 | Promos Technologies Inc. | Memory cell having a deep trench capacitor and a vertical channel |
| CN1379913A (en) * | 1999-04-30 | 2002-11-13 | 西门子公司 | Static random access memory (SRAM) |
| US6507511B1 (en) * | 2001-10-02 | 2003-01-14 | International Business Machines Corporation | Secure and dense SRAM cells in EDRAM technology |
-
2004
- 2004-03-23 CN CNB2004100079749A patent/CN1329994C/en not_active Expired - Lifetime
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1379913A (en) * | 1999-04-30 | 2002-11-13 | 西门子公司 | Static random access memory (SRAM) |
| US6507511B1 (en) * | 2001-10-02 | 2003-01-14 | International Business Machines Corporation | Secure and dense SRAM cells in EDRAM technology |
| US6479852B1 (en) * | 2001-10-03 | 2002-11-12 | Promos Technologies Inc. | Memory cell having a deep trench capacitor and a vertical channel |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1674291A (en) | 2005-09-28 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7019350B2 (en) | Trench device structure with single-side buried strap and method for fabricating the same | |
| KR100403066B1 (en) | Improved vertical mosfet | |
| KR100338462B1 (en) | Device manufacturing method comprising self-amplifying dynamic MOS transistor memory cells | |
| KR100641943B1 (en) | Vertical device formed adjacent to a wordline sidewall and method for semiconductor chips | |
| US6391705B1 (en) | Fabrication method of high-density semiconductor memory cell structure having a trench | |
| US6552382B1 (en) | Scalable vertical DRAM cell structure and its manufacturing methods | |
| US7923325B2 (en) | Deep trench device with single sided connecting structure and fabrication method thereof | |
| CN1213857A (en) | Reducing oxidation stress in fabrication of devices | |
| CN1213167A (en) | Reducing oxidation stress in fabrication of device | |
| US7211483B2 (en) | Memory device with vertical transistors and deep trench capacitors and method of fabricating the same | |
| US6414347B1 (en) | Vertical MOSFET | |
| KR950008791B1 (en) | Method of making a trench capacitor and dram memory cell | |
| US7094659B2 (en) | Method of forming deep trench capacitors | |
| US20050184326A1 (en) | Deep-trench 1t-sram with buried out diffusion well merged with an ion implantation well | |
| US20050045936A1 (en) | Dynamic random access memory cell layout and fabrication method thereof | |
| CN100495686C (en) | Capacitor contact structure and technique for dynamic random access memory | |
| US6902982B2 (en) | Trench capacitor and process for preventing parasitic leakage | |
| US6953961B2 (en) | DRAM structure and fabricating method thereof | |
| CN1329994C (en) | Deep channel type capacity and structure of single-transistor static random access internal storing unit | |
| CN101656254B (en) | Dynamic random access memory structure and manufacturing method thereof | |
| US7638391B2 (en) | Semiconductor memory device and fabrication method thereof | |
| CN1307722C (en) | Dynamic RAS with slit capacitor and its mfg. method | |
| CN1216863A (en) | Vertical transistor | |
| CN100388419C (en) | Trench capacitors with buried isolation layer and methods for manufacturing the same | |
| US7993985B2 (en) | Method for forming a semiconductor device with a single-sided buried strap |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term |
Granted publication date: 20070801 |