CN1329986C - ESD Protection Components for Integrated Circuit Inputs - Google Patents

Abstract

The invention provides an electrostatic discharge protection element as an electrostatic discharge protection element of an integrated circuit with an input connecting pad , which comprises a pull-up device, such as a Metal Oxide Semiconductor (MOS) transistor, which is responsible for ND and PD electrostatic discharge modes and is connected between a working voltage and a grounding voltage of the integrated circuit. A protection device, such as a field oxide device, has an input terminal connected to the input pad and an output terminal connected to the ground voltage, wherein the output terminal of the protection device in the substrate is shared with the pull-up operation device (share), and is used for passing an electrostatic discharge (ESD) current from the input pad to the pull-up operation device when the ground voltage is floating.

Description

ESD Protection Components for Integrated Circuit Inputs

(1) Technical field

The present invention relates to an integrated circuit component, and more particularly to a component for protecting the integrated circuit from electrostatic discharges introduced from the input terminals.

(2) Background technology

There has long been a problem with semiconductor integrated circuits being damaged by electrostatic discharge introduced from any external connection pin. A common solution to this problem is to guide the current to the ground terminal on the terminal pad when electrostatic discharge invades the chip components, so as not to flow into the internal circuit and cause damage.

One of the conventional layouts for such vias is shown in FIG. 1 . A pull-up transistor 105 has one input terminal connected to the pad 101 of the integrated circuit, and the other two input terminals are connected to the operating voltage V _DD of the chip. A pull-down transistor 106 has one input terminal connected to the pad 101 and the other two input terminals connected to the ground voltage Vss of the chip. One end of the resistor 107 is connected to the pull-up transistor 105 , the pad 101 , and the disconnect transistor 106 , and the other end is connected to the input stage of the integrated circuit. And a second-stage transistor 103 has one input terminal connected to the input stage, and the other two input terminals connected to the ground voltage Vss of the chip.

Another conventional layout, especially for high voltage components, is shown in Figure 2. A field oxygen device (Field Oxide Device, FOD) 102 has an input terminal connected to a pad 101 of the integrated circuit, and another input terminal connected to the ground voltage Vss of the chip. One end of the resistor 104 is connected to the pad 101 and the field oxygen element 102 , and the other end is connected to the input stage of the integrated circuit. And a second-stage transistor 103 has one input terminal connected to the input stage, and the other two input terminals connected to the ground voltage Vss of the chip. In consideration of the ESD protection performance, the layout area required by the FOD type ESD device is smaller than that of the Metal Oxide Semiconductor (MOS) type ESD device.

However, the FOD type ESD device also has some disadvantages. First of all, FOD needs a long channel to avoid the risk of leakage in normal operation mode, but the long channel design will lead to too slow start-up speed in ESD mode, which will cause ESD failure. Secondly, when the protection mechanism of FOD is driven by n+/p junction breakdown, a large amount of heat will be generated at its cylindrical junction, which will reduce the protection ability (level) of electrostatic discharge. Third, the performance of the FOD formed by the LOCOS process is better than that formed by the shallow trench isolation (STI) (Shallow Trench Isolation) process. Unfortunately, STI is widely used in submicron or deep submicron technology, so the performance of FOD is bound to decrease. In addition, when using FOD in the ESD protection device, there is no ESD protection device with a pull-up action corresponding to the MOS type protection device, so that it is impossible to effectively use the FOD type protection device to implement the ND mode (by the input terminal Negative electrostatic discharge to the V _DD terminal, V _DD terminal is grounded during the test) and PD mode (positive electrostatic discharge from the input terminal to the V _DD terminal, the V _DD terminal is grounded during the test) electrostatic discharge test.

(3) Contents of the invention

In view of the above-mentioned background of the invention, one of the objectives of the present invention is to provide a protective element for integrated circuits; a structure is used to establish an effective and shortest circuit path, so that the original FOD type electrostatic discharge element is not good for ND and PD electrostatic discharge Test mode performance improved.

Another object of the present invention is to provide a protection device that takes into account enhanced ND and PD electrostatic discharge modes and a smaller layout area.

Another object of the present invention is to provide a FOD-type protection element, which increases the effective area of the junction by adding a polysilicon block structure to the FOD element, and these polysilicon block structures can further avoid junction overheating and bad start-up efficacy.

According to the purpose described above, the present invention provides a kind of electrostatic discharge (Electro-Static Discharge, ESD) protection element of an integrated circuit with an input pad (pad) in a substrate, comprising: a pull-up action (Pull-up) device, such as a MOS transistor, for ND and PD electrostatic discharge modes, and connected between an operating voltage and a ground voltage of the integrated circuit; a protection device, such as a field oxygen element, has an input terminal Connected to the input pad and an output terminal connected to the ground voltage, wherein the output terminal of the protection device located in the substrate is shared with the pull-up action device, and is used for when the ground voltage is floating (floating), from the input The pad passes an electrostatic discharge current to the pull-up action device.

(4) Description of drawings

FIG. 1 is a schematic diagram of an equivalent circuit of a traditional electrostatic discharge protection component.

FIG. 2 is another schematic diagram of an equivalent circuit of a conventional ESD protection device.

FIG. 3 is a schematic diagram of an equivalent circuit for illustrating the FOD type electrostatic discharge protection device of the present invention.

FIG. 4 is a schematic layout diagram of an embodiment of a FOD type electrostatic discharge protection device according to the present invention.

FIG. 5 is a schematic layout diagram of another embodiment of a FOD type electrostatic discharge protection device according to the present invention.

(5) specific implementation

When the present invention is described in detail with the following embodiments, those familiar with the art should recognize that the present invention allows several modifications and substitutions without departing from the scope of the proposed patent. The structure or method used to disclose is not limited to a specific protection device, but also includes other equivalent semiconductor protection devices, and the illustrations are also used to illustrate preferred embodiments, not to limit the scope of the present invention.

Different parts of the semiconductor protection device of the present invention are not drawn to scale. Certain dimensions have been exaggerated compared to other relevant dimensions to provide a clearer description and understanding of the invention. Additionally, although the embodiments drawn here are shown in two dimensions with width and depth at different stages, it should be clearly understood that the area shown is only a portion of the protective element, which may contain many Arranged elements. In contrast, in the manufacture of actual components, illustrated regions have three-dimensional length, width and height.

The present invention provides an electrostatic discharge (Electro-Static Discharge, ESD) protection element of an integrated circuit with an input pad in a substrate, including a field oxygen element having an input terminal connected to the input pad , and an output terminal connected to a ground voltage of the integrated circuit. A semiconductor element, such as a MOS transistor, has a first terminal connected to an operating voltage, and a second terminal connected to the ground voltage with a second terminal shared with the output terminal of the field oxygen element in the substrate, so as to be connected to the ground voltage when the ground voltage floats When floating, an electrostatic discharge current passes through the semiconductor element from the input pad through the field oxygen element.

FIG. 3 is a schematic diagram of an equivalent circuit for illustrating the FOD type electrostatic discharge protection device of the present invention. A field oxygen element (Field Oxide Device, FOD) 2 has an input terminal, such as a collector terminal, connected to the pad 1 of the integrated circuit, and another input terminal, such as an emitter terminal, connected to the ground of the chip Voltage Vss. The field oxygen element 2 serving as the first protection element can be manufactured by LOCOS or STI process. In addition, in the present invention, the collector terminal of the field oxygen element 2 is used as a pin protection for high voltage input, which has a high breakdown voltage interface. One end of the resistor 5 is connected to the pad 1 and the field oxygen element 2 , and the other end is connected to the input stage of the integrated circuit. And a second-stage transistor 4, such as an n-type MOS, has an input terminal, such as a collector terminal, connected to the input stage, and the other two input terminals, such as an emitter terminal and a control base terminal, are connected to the chip. Ground voltage Vss. In a preferred embodiment, the second-stage transistor 4 is applied to a high-voltage element of an integrated circuit, and its channel length is approximately equal to that of the field oxygen element 2 .

One of the keys of the present invention, an nMOS transistor 3 has one end, such as a collector terminal, connected to an operating voltage VDD, and the other two input terminals, such as an emitter terminal and a control base, are connected to the ground of the chip Voltage Vss. In this preferred embodiment, the channel length of the nMOS transistor 3 is smaller than the channel length of the second-stage transistor 4 or the field oxide device 2 . In addition, the base oxide layer of the nMOS transistor 3 is thinner than the base oxide layer of the second-stage transistor 4 . The addition of nMOS transistor 3 has many advantages. Firstly, the nMOS transistor 3 is connected to the working voltage VDD and the ground voltage Vss, and can be regarded as a clamping transistor. In this way, the PD and ND ESD modes of the FOD type ESD protection device can be improved. Furthermore, since the nMOS transistor 3 shares the emitter region (not shown in the figure) with the field oxide device 2 , the layout area of the FOD type electrostatic discharge protection device can be saved.

FIG. 4 is a schematic layout diagram of an embodiment of a FOD type electrostatic discharge protection device according to the present invention. The field oxygen device has a field oxygen region 20 and a collector region 14 in a substrate, and a plurality of contacts 10 are distributed on the collector region 14 . The emitter region 15 in the substrate is shared by the field oxide device and the nMOS transistor of the present invention. The polysilicon base 12 of the nMOS transistor is located between the emitter region 15 and the collector region 16 . Several contact windows 10 are also arranged on the emitter region 15 and the collector region 16 . One of the keys of the present invention is that the nMOS transistor and the field oxygen element can share the common emitter region 15, so that the overall layout area can still be saved under the consideration of strengthening the PD and ND electrostatic discharge modes.

FIG. 5 is a schematic layout diagram of another embodiment of a FOD type electrostatic discharge protection device according to the present invention. 4, except that nMOS transistors are added, several polysilicon square structures 17 are arranged in the active regions on the collector regions 14, 16 and the emitter region 15, and the polysilicon square structures 17 are suitable for FOD type electrostatic discharge protection components. There are many advantages. First, the polysilicon square structure 17 is formed in front of the collector region and the emitter region; therefore, the formation of the collector regions 14, 16 and the emitter region 15 uses the polysilicon square structure 17 as an implantation mask and is completed by a self-alignment process. In this way, many additional junctions can be formed using the polysilicon square structure 17 as an implant mask. These additional junctions can improve poor start-up characteristics caused by STI discontinuities. In addition, the same as the embodiment shown in FIG. 4 , the nMOS transistor and the field oxygen element share the common emitter region 15 , which saves the layout area and enhances the PD and ND ESD modes.

Second, the additional junction can effectively disperse the ESD current in three dimensions, so that the overheating of the junction at the corner of the FOD can be avoided in any ESD mode. The extra junction increases the junction area for ESD currents. In addition, the additional junction can increase the input resistance, thereby reducing the ESD current oscillation phenomenon of the mechanical mode ESD. In the present invention, the size and geometry of the polysilicon square structure 17 are not limited to those shown in FIG. 5 .

The above description is only a preferred embodiment of the present invention, and is not intended to limit the patent scope of the present invention; all other equivalent changes or replacements that do not deviate from the spirit disclosed by the present invention should be included in the following within the scope defined by the claims.

Claims (15)

1. An electrostatic discharge protection element for an integrated circuit with an input pad, characterized in that it comprises: a first semiconductor element connected between an operating voltage and a ground voltage of the integrated circuit, the first semiconductor element at least comprising a metal-oxide-semiconductor element having a source region; a field oxygen element having an input end connected to the input pad and an output end connected to the ground voltage, wherein the output end of the field oxygen element is shared with the source region of the first semiconductor element; and A second semiconductor element has a first gate oxide layer on the substrate thicker than a second gate oxide layer of the metal-oxide-semiconductor element, the semiconductor element has a first terminal connected to the input terminal The pad and a second terminal are connected to the ground voltage. 2 . The electrostatic discharge protection device according to claim 1 , wherein the metal-oxide-semiconductor device has a collector region connected to the operating voltage, and a base terminal connected to the ground voltage. 3 . 3. The electrostatic discharge protection device according to claim 1, wherein the field oxygen device has a collector region as the input terminal and an emitter region as the output terminal. 4 . The electrostatic discharge protection device according to claim 3 , wherein the field oxygen device comprises a plurality of polysilicon structures distributed on the substrate and located above the emitter region and the collector region. 5. An electrostatic discharge protection component for an integrated circuit with an input pad in a substrate, characterized in that it comprises: The field oxygen element has an input terminal connected to the input pad, and an output terminal connected to a ground voltage of the integrated circuit; A first semiconductor element has a first end connected to an operating voltage, and has a second end shared with the output end of the field oxygen element in the substrate; and A second semiconductor element is connected to the input pad and the ground voltage, wherein the first semiconductor element has a gate oxide layer on the substrate that is thinner than the gate oxide layer of the second semiconductor element. 6. The ESD protection device according to claim 5, wherein a plurality of polysilicon structures are distributed on the substrate of the first semiconductor device. 7 . The electrostatic discharge protection device according to claim 6 , wherein the first end is completed by implanting ions into the substrate by using the polysilicon structure as a self-aligned mask. 7 . 8. The ESD protection device according to claim 5, wherein the second end has an emitter region in the substrate, and a plurality of polysilicon structures are distributed on the emitter region. 9. The electrostatic discharge protection device according to claim 5, wherein the field oxygen device at least comprises a plurality of polysilicon structures in an active region on the substrate. 10 . The electrostatic discharge protection device according to claim 9 , wherein the input end is implanted under the active region using the polysilicon structure as a mask. 11 . 11 . The electrostatic discharge protection device according to claim 9 , wherein the output terminal is implanted under the active region using the polysilicon structure as a mask. 12. A field oxygen element type electrostatic discharge protection element of an integrated circuit with an input pad in a substrate, characterized in that it includes: A field oxygen region has a plurality of isolation elements on the substrate; a first base region on the substrate and connected to a ground voltage of the integrated circuit; A second base region is on the substrate outside the first base region, and the second base region has a gate oxide layer thicker than that of the first base region; a first field region is located in the substrate between the field oxygen region and the first base region, and is connected to the ground voltage; a second field region in the substrate outside the field oxygen region, the second field region connected to the input pad; and A third field region is in the substrate outside the first base region, and the third field region is connected to an operating voltage. 13. The field oxygen element type electrostatic discharge protection element as claimed in claim 12, wherein the first field region at least includes an emitter portion of the field oxygen region and a portion of the first base region Emitter part. 14. The field oxygen element type ESD protection device as claimed in claim 12, wherein the second base region is connected to the ground voltage. 15 . The field oxygen device type electrostatic discharge protection device as claimed in claim 12 , wherein a plurality of conductive contacts are located on the first field region, the second field region and the third field region. 15 .

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