CN1324827C

CN1324827C - Method and apparatus for generating test flow

Info

Publication number: CN1324827C
Application number: CNB021267936A
Authority: CN
Inventors: 王新建; 臧大军; 余进
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2002-07-23
Filing date: 2002-07-23
Publication date: 2007-07-04
Anticipated expiration: 2022-07-23
Also published as: CN1471248A

Abstract

The invention discloses a method for generating a test flow. The cell header is generated in a microprocessor according to the flow distribution, and an initial value of cell random data is generated to replace the payload. The payload of the cell is generated by a random function generator inside the cell forwarding port. In this way, the data that needs to be transmitted between the microprocessor and the cell forwarding port is only the cell header and the initial value of the random data of the cell, and their size is less than 1/4 of the entire cell. In this way, the workload of the microprocessor is greatly reduced, and the requirement for the bandwidth between the microprocessor and the cell forwarding port is reduced, so that a test flow with a larger flow rate can be provided at the same time without increasing the hardware , For example: 2.5Gbps test flow and 10Gbps test flow can be provided at the same time with the same test flow generation circuit.

Description

The production method and the device of test stream

Technical field:

The present invention relates to a kind of production method and device that is used for the test stream of communication equipment.

Background technology:

The production method of test information cells is general complete is now generated by software.Software can produce the cell flow that meets certain distribution (as Poisson distribution, Gaussian Profile), comprises header information (priority of source port number, destination slogan, cell) and the cell payload that generates according to random algorithm.The cell structure that generates as shown in Figure 1.

The example that is produced as with 10Gbps and 2.5Gbps test stream, after software generates a complete cell, whole cell is configured among the RAM (dynamic memory), produces the test stream of 10Gbps or 2.5Gbps with 10Gbps or different hardware, the logical versions of 2.5Gbps.Produce schematic diagram such as Fig. 2 of test stream.

Produce hardware, logical circuit such as Fig. 3 of 2.5Gbps test stream, in this test stream generative circuit, microprocessor generates cell, and the function of logic only needs read cell by the mode of cyclic query, and according to the reorganization of circuit-under-test demand and send out.

The hardware circuit of generation 10Gbps test traffic as shown in Figure 4, owing to will produce the flow of 10Gbps, microprocessor and RAM and RAM and FPGA (being used for transmitting the logical circuit of cell) if between flow bandwidth 4 times of 2.5Gbps flow just, because the frequency of clock is certain, just need to place the requirement that 4 block RAMs satisfy bandwidth.

The above-mentioned test stream generation method formula of prior art implements simply, and the work that key data miscarriage is given birth to is finished by software, and hardware only is responsible for sending data according to the flow port of 10Gbps or according to the flow port of 2.5Gbps, but it has following shortcoming:

1, software work amount big (it is big to be actually the microprocessor work amount) not only will produce header information and also will produce cell payload (also claiming the cell body), and the efficient that causes generating cell is lower, and the time that produces test stream is longer.

2, in this way, the data flow of 10Gbps produces with the generation of 2.5Gbps data flow needs different hardware, logical versions to support.

3, in order to support the test stream of 10Gbps, need support by 4 block RAMs.

4, the bandwidth ratio that needs between microprocessor and RAM and RAM and the FPGA is bigger, first payload because first header of not only will delivering a letter between them also will be delivered a letter.

When test streams such as needs generation 5G, 20G, there is above-mentioned shortcoming equally.

Summary of the invention:

The purpose of this invention is to provide a kind of production method and device of testing stream, improve the cell formation efficiency, reduce the requirement that centering turns over the journey bandwidth, under the situation that does not increase bandwidth, can generate more high-speed data-flow.

For achieving the above object, the present invention proposes a kind of production method of testing stream, it is characterized in that comprising the steps: A) microprocessor produces header and cell random data initial value information according to the flow distribution rule of cell; B) according to time slot allocation header and cell random data initial value information distribution are arrived one or more ports; C) the logical foundation cell random data initial value information of each port uses inner randomizer to produce the cell payload, and forms complete cell by header and cell payload.

The present invention also proposes a kind of generation device of testing stream, it is characterized in that comprising as lower device: the microprocessor that A) is used for producing according to the flow distribution rule of cell header and cell random data initial value information; B) be used for transmitting ports according to one or more cells of time slot allocation reception header and cell random data initial value information; C) be used for using inner randomizer to produce the cell payload according to cell random data initial value information, and header and cell payload formed the port logic circuit of complete cell, described port logic circuit and cell are transmitted port and are linked to each other or directly be arranged in the forwarding port.

Owing to adopted above scheme, separated the position that header and cell payload produce: header uses software to produce in microprocessor according to flow distribution, and produces a cell random data initial value and replace payload.The payload of cell is transmitted port inside at cell and is produced by randomizer.To transmit the data that need to transmit between the port be header and cell random data initial value for microprocessor and cell like this, they size less than 1/4 of whole cell.Like this, just significantly reduce the workload of microprocessor, improved the cell formation efficiency; Reduced requirement to bandwidth between microprocessor and the cell forwarding port, thereby realized under the situation that does not increase bandwidth, can provide the test stream of bigger flow simultaneously, for example: just can provide 2.5Gbps test stream and 10Gbps test stream simultaneously with same test stream generative circuit.

Description of drawings:

Fig. 1 is the cell structure schematic diagram.

Fig. 2 is the process schematic diagram that produces test stream in the prior art.

Fig. 3 is hardware, the logical circuit schematic diagram that produces 2.5Gbps test stream in the prior art.

Fig. 4 is the hardware circuit schematic diagram that produces the 10Gbps test traffic in the prior art.

Fig. 5 is that the present invention tests stream generation schematic diagram.

Fig. 6 is 10Gbps of the present invention and 2.5Gbps compatibility test stream generative circuit schematic diagram.

Embodiment:

Also the present invention is described in further detail in conjunction with the accompanying drawings below by specific embodiment.

See Fig. 5, the generative process that the present invention tests stream is as follows: header uses software to produce in microprocessor according to flow distribution, and the cell random data initial value that produces a 32bits replaces the cell payload.According to time slot allocation a header and cell random data initial value information distribution to 4 a 2.5Gbps port, the logical foundation cell random data initial value of each port uses inner randomizer to produce the cell payload information, has just formed the test stream of a 10Gbps.

Because the payload of cell produces by randomizer in FPGA inside, to be configured to the data that data among the RAM and FPGA inquire in RAM be header and cell random data initial value to microprocessor like this, their size is less than 1/4 of whole cell, so in the common test flow generator, FPGA inquires about the time slot of a cell in RAM, can transmit 4 headers and cell payload in this patent.

Because the present cell characteristic information that generates (header and seed) size has improved 4 times less than original 1/4 so upgrade the common way of time ratio of RAM.In FPGA inquiry RAM information, inquired about the time slot of a cell originally and can inquire about 4 cell characteristic informations now.These 4 header information are assigned to 4 parts of FPGA inside by the principle of time slot distribution, each part all has a randomizer, the seed that obtains according to oneself generates the cell payload, form cell with header, according to the difference of institute's test cross draping, cell is recombinated again to the cell structure requirement.Each part can produce the test stream of a 2.5Gbps flow, and 4 ports just can generate the test stream of 10Gbps flow.

Owing to only transmit header and cell random data initial value information between little processing and RAM and RAM and the FPGA, shared data volume is less than transmitting 1/4 of cell flow, so support the data bandwidth of a block RAM that only needs of the flow of 10Gbps just can meet the demands.

The present invention is particularly suitable for the generation of 10Gbps test stream, but can be suitable for equally the generation of 5G, 20G or higher test stream, and all has the following advantages:

1, because microprocessor only produces header and cell random data initial value information, so The workload of little processing reduces greatly, and also only literary composition is original to generate and dispose the used time of RAM content 1/4.

2, between microprocessor and RAM and RAM and the FPGA because transmit cell head and cell Random data initial value information rather than transmit whole cell is so bandwidth requirement only is original 1/4.

3, because above-mentioned the 2nd advantage when supporting the 10Gbps flow, only needs a block RAM Data/address bus just meet the demands.

The emulation of the present invention's process, and in experimental project, use, be proven reliably feasible.

Claims

1, a kind of generation method of test flow, it is characterized in that comprising the steps: A) microprocessor produces cell header and cell random data initial value information according to the flow distribution law of cell; B) distributes cell according to time slot The header and the initial value information of cell random data are distributed to one or more cell forwarding ports; C) the logic of each cell forwarding port uses the internal random function generator to generate the cell payload according to the initial value information of cell random data, and A complete cell is composed of a cell header and a cell payload.

2. The method for generating a test flow as claimed in claim 1, characterized in that: after each cell forwarding port forms a complete cell, the cells of a plurality of cell forwarding ports are recombined to form a cell whose flow rate is higher than that of the original cell cell.

3. The method for generating a test flow as claimed in claim 1 or 2, characterized in that: there are four cell forwarding ports, each cell forwarding port generates a test flow of 2.5Gbps flow, and forms a 10Gbps flow after reorganization the test flow.

4. The generation method of test flow as claimed in claim 1 or 2, characterized in that: after step A) and before step B), the generated cell header and initial value information of cell random data are configured in dynamic in memory.

5, a kind of generation device of test flow, it is characterized in that comprising following device: A) be used for the microprocessor that produces cell header and cell random data initial value information according to the traffic distribution law of cell; B) be used for according to time One or more cell forwarding ports for receiving the cell header and the initial value information of the random data of the cell; C) for using the internal random function generator to generate the payload of the cell according to the initial value information of the random data of the cell, and The cell header and the cell payload form a complete port logic circuit of the cell, and the port logic circuit is connected to the cell forwarding port or directly arranged in the forwarding port.

6. The method for generating test streams according to claim 5, further comprising a cell recombination device for recombining cells of multiple ports into a cell with a flow rate higher than that of the original cell.

7. The method for generating test streams as claimed in claim 5 or 6, characterized in that: there are four cell forwarding ports, and each cell forwarding port generates a test stream of 2.5Gbps traffic, which forms 10Gbps traffic after reorganization the test flow.

8. The method for generating a test flow as claimed in claim 5 or 6, characterized in that: a dynamic memory is also provided between the microprocessor and the cell forwarding port, for initializing the generated cell header and cell random data Value information is configured into it.