CN1324320C - Multi-pack d.c signal conversion digital signal device - Google Patents
Multi-pack d.c signal conversion digital signal device Download PDFInfo
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- CN1324320C CN1324320C CNB2004100335783A CN200410033578A CN1324320C CN 1324320 C CN1324320 C CN 1324320C CN B2004100335783 A CNB2004100335783 A CN B2004100335783A CN 200410033578 A CN200410033578 A CN 200410033578A CN 1324320 C CN1324320 C CN 1324320C
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- 230000007704 transition Effects 0.000 claims description 38
- 230000005669 field effect Effects 0.000 claims description 5
- 229910044991 metal oxide Inorganic materials 0.000 claims description 3
- 150000004706 metal oxides Chemical class 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 claims description 3
- 238000004088 simulation Methods 0.000 claims description 2
- 238000009966 trimming Methods 0.000 description 8
- 230000008859 change Effects 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 5
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Abstract
The present invention relates to a device for converting multi-pack direct current signals into digital signals, which comprises a first voltage selecting zone block, a reverser, a second voltage selecting zone block and a voltage converting zone block, wherein one end of the first voltage selecting zone block is connected with an analog voltage end, and the other end is connected with one end of the reverser; the input end of the reverser is connected with a signal input end, one end of the reverser is connected with the first voltage selecting zone block, and the other end is connected with one end of the second voltage selecting zone block; the other end of the second voltage selecting zone block is connected with the ground; one input end of the voltage converting zone block is connected with the output end of the reverser, one end of the voltage converting zone block is connected with a digital voltage end, and the other end is connected with the ground. The device can be also used for reducing chip area and saving power consumption besides adjusting different voltage converting state range so as to convert direct current signals into digital signals for output.
Description
Technical field
The present invention is about a kind of direct current signal conversion digital signal device; Particularly relevant for a kind of device of adjusting many groups direct current signal conversion digital signal of different voltage transition scopes.
Background technology
In the design of CD-ROM drive chip, need the different DC voltage position standard (for example: 0.5V, 1.5V and 2.5V) of input chip is done conversion according to product specification, to distinguish noble potential or electronegative potential.For example, the DC voltage of 0.5V and 1.5V is converted to the electronegative potential of numeral, and the DC voltage of 2.5V is converted to the noble potential of numeral.With reference to shown in Figure 1, traditional technology is to utilize a comparer to change, and it will be between the reference voltage V between 1.5V and the 2.5V
RFrom the negative terminal input of comparer, and another DC input voitage V
D, then import by the anode of comparer.Because it is 1.2V that chip internal has a supply power, as the DC input voitage V of comparer
DLess than reference voltage V
RThe time, output voltage V
OBe 0V, and work as the DC input voitage V of comparer
DGreater than reference voltage V
RThe time, output voltage V then
OBe 1.2V, its DC input voitage V
DAnd output voltage V
OGraph of a relation as shown in Figure 2.But in this technology, because reference voltage V
RNeed all to remain at any time the state of conducting, therefore the consumption that can produce extra electric current and static power.In addition, in an IC chip (Chip), the shared chip area of comparator circuit is bigger, and this also will make the integrated level of chip reduce.
With reference to shown in Figure 3, be the known technology of another kind, it utilizes the method that changes voltage level (levelshift) with the aanalogvoltage AV in the CD-ROM drive chip
DD(for example: 3.3V) convert digital voltage DV to
DD(for example: 1.2V) reach above-mentioned purpose, wherein the source electrode of PMOS transistor MP1 and MP2 is connected to the aanalogvoltage AV in the chip respectively
DD(3.3V) and digital voltage DV
DD(1.2V), at DC input voitage V
DVoltage (for example: in the time of 0.7V), then transistor MP1 is that conducting and MN1 are not on-state, and therefore, the output voltage of input stage reverser (promptly being made of transistor MP1 and MN1) is AV between 0V and critical voltage
DD, and as the input voltage of output stage reverser (promptly being constituted by transistor MP2 and MN2).At this moment, aanalogvoltage AV
DDIs conducting state for transistor MP2 for not conducting but to MN2, and therefore, the output voltage of output stage reverser is 0V.In like manner, as DC input voitage V
DVoltage during greater than the critical voltage (about 0.7V) of MN1, then transistor not conducting of MP1 and MN1 is a conducting state, therefore, the output voltage of input stage reverser is 0V, and as the input voltage of output stage reverser.0V is conducting for transistor MP2, but is not on-state to MN2, and therefore, the output voltage of output stage reverser is digital voltage DV
DDFig. 4 is the DC input voitage V of the method for change voltage level known among Fig. 3
DWith output voltage V
OGraph of a relation.
Change in the known technology of voltage level (level shift), in above-mentioned utilization because utilize the existing aanalogvoltage AV of chip internal
DDAnd digital voltage DV
DDSo, need not as utilizing additional circuit to produce a reference voltage in the comparer, thereby simplified the design of chip and dwindled the usable floor area of chip.But PMOS among Fig. 3 and nmos pass transistor can only be used for distinguishing and be higher than (AV
DD-V
Tp) and be lower than V
TnVoltage, wherein V
TpWith V
TnCritical voltage (Threshold Voltage) for transistor MP1 and MN1.So if DC input voitage V
DDrop on (V
Tn) and (AV
DD-V
Tp) between the time, may make that then transistor MP1 and MN1 all produce the situation of conducting; And if adjust the DC voltage that wherein transistorized size cooperates input reluctantly, then the PMOS of input stage and nmos pass transistor can consume relatively large static power.
Summary of the invention
In the foregoing invention background, many shortcomings that method produced of traditional change voltage level, the objective of the invention is to propose a kind of many group direct current signal conversion digital signal devices, it is characterized in that avoiding using the design of comparer, with consumption that significantly reduces static power and the usable floor area that dwindles chip.In view of the above, fundamental purpose of the present invention promptly utilizing voltage to select block, produces different voltage transition scopes, thereby can distinguish different direct current signal inputs, and converts thereof into corresponding digital signal.
A preferred embodiment of the present invention is to provide a kind of many group direct current signal conversion digital signal devices.Wherein comprising one first voltage selects block, a reverser, one second voltage to select a block and a voltage transitions block.First voltage selects block and this second voltage to select block interval big or small during a flash when the transition in order to control this input signal, make reverser receive and have several not input signals of coordination standard, do not have input signal and fall within the operation situation that instantaneous interval influences this reverser, output to the voltage transitions block then to produce corresponding digital signal output.
Description of drawings
Fig. 1 is a comparer synoptic diagram;
Fig. 2 is the input of a comparer and the graph of a relation of output voltage;
Fig. 3 is the circuit structure diagram of the method for a known change voltage level;
Fig. 4 is the input of circuit structure of method of a known change voltage level and the graph of a relation of output voltage;
Fig. 5 is the block schematic diagram of direct current signal conversion digital signal device according to a preferred embodiment of the present invention; And
Fig. 6 is the circuit structure icon intention of direct current signal conversion digital signal device according to a preferred embodiment of the present invention; And
Fig. 7 adds the circuit structure icon intention of voltage waveform trimming block for the direct current signal conversion digital signal device according to another preferred embodiment of the present invention.
Symbol description among the figure:
100 direct current signal conversion digital signal devices
110 first voltages are selected block
120 reversers
130 second voltage transitions blocks
140 voltage transitions blocks
150 voltage waveforms trimming block
Embodiment
As shown in Figure 5, be many groups direct current signal conversion digital signal schematic representation of apparatus according to the construction of a preferred embodiment of the present invention institute.In Fig. 5, organize direct current signal conversion digital signal device 100 more and comprise one first voltage selection block 110, a reverser 120, one second voltage selection block 130 and a voltage transitions block 140.First voltage selects an end of block 110 to connect an aanalogvoltage (AV
DD), and the other end connects reverser 120.The input end of reverser 120 connects input signal (V
I), and an end of reverser 120 is selected the block 110 except that connecting first voltage, the other end then connects the end that second voltage is selected block 130.Second voltage selects the other end of block 130 then to connect earth point.One input end of voltage transitions block 140 connects the output terminal of reverser 120, and an end of voltage transitions block 140 removes and connects a digital voltage (DV
DD) outside, the other end then connects earth point.In many group direct current signal conversion digital signal devices 100 of the present invention, first and second voltage selects block (110,130) in order to compression input signal (V
I) extremely minimum in the instantaneous interval of transition, to prevent input signal (V
I) fall within this interval, cause a large amount of current losses.
According to above-mentioned device, as the input signal V of reverser 120
IVoltage between 0V and a critical voltage (specification requirement of the big or small visual practical application of this critical voltage, select block 110,130 to decide by first and second voltage, this partly will further specify in Fig. 6 again) between the time, can make first voltage select block 110 to form conducting and the 130 not conductings of second voltage selection block, then can select block 110 with aanalogvoltage AV by first voltage
DDVia the output of the output terminal of reverser 120, and as the input voltage of voltage transitions block 140.At this moment, as aanalogvoltage AV
DDDigital voltage (DV greater than voltage transitions block 140
DD) time, voltage transitions block 140 (for example: digital signal 0V) is output as an electronegative potential.In the time of conversely, as the input signal V of reverser 120
IVoltage during greater than critical voltage, can make wins presses and selects block 110 not conductings and second voltage selects block 130 to form conductings, then reverser 120 can form a ground state.At this moment, voltage transitions block 140 is output as the digital signal of a noble potential, i.e. digital voltage (DV
DD).Therefore, the output terminal of voltage transitions block 140 of the present invention can be output as noble potential or a digital signal (V is changed and exported to electronegative potential according to reverser 120
O).
For illustrating further, please refer to Fig. 6, it is the electrical block diagram of a specific embodiment of many group direct current signal conversion digital signal devices of the present invention, its purpose is at many groups of different direct-flow input signals, make its transition scope (or being called instantaneous district) when conversion digital signal (for example: 2V) effectively be controlled at particular value, and can further be compressed to minimum, to prevent the consumption of static power.First voltage selects block 110 (MP3) to be made up of a PMOS (P-type mos field-effect transistor), reverser 120 is by a PMOS, be that a P-type mos field-effect transistor (MP4) and a NMOS (N type metal oxide semiconductor field-effect transistor) (MN3) form, second voltage selects block 130 to be made up of two nmos pass transistors (MN4 and MN5), and voltage transitions block 140 is then formed by a CMOS transistor CMOS (MP2 and MN2).
Continue as shown in Figure 6, as input signal (V
I) voltage be 0.5V, digital voltage (DV
DD) be 1.2V and aanalogvoltage (AV
DD) when being 3.3V, because of V
IThe critical voltage value (be about 2.1V) of magnitude of voltage after less than transistor MN3, MN4 and MN5 serial connection, so transistor MN3, MN4 and MN5 are not on-state, but for transistor MP3 and MP4, owing to AV
DDWith V
IVoltage difference be about 2.6V, be higher than the critical voltage value (being about 1.2-1.4V) after transistor MP3 and the MP4 serial connection, so MP3 and MP4 transistor after being connected in series are conducting state.Therefore, aanalogvoltage AV
DDThe electric current of end can flow to the output terminal of reverser 120, with AV
DDVoltage is as the input voltage of voltage transitions block 140.Afterwards, because transistor MP2 is a not on-state, transistor MN2 then is a conducting state, and therefore, voltage transitions block 140 obtains digital output signal V
OBe 0V.In like manner, as input signal V
IVoltage when being 1.5V, selecting the transistor (MN4, MN5) of block 130 and the formed critical voltage of another transistor (MN3) because of second voltage is 2.1V, so operation situation is same as described above, so its voltage transitions block 140 obtains digital signal V
OStill be 0V.
As input signal (V
I) voltage be increased to 2.5V, digital voltage (DV
DD) be 1.2V and aanalogvoltage (AV
DD) when being 3.3V, because of V
IThe critical voltage value (2.1V) of magnitude of voltage after greater than transistor MN3, MN4 and MN5 serial connection, so transistor MN3, MN4 and MN5 are conducting state, and for transistor MP3 and MP4, owing to AV
DDWith V
IThe critical voltage value (about 1.2V-1.4V) of voltage difference (being 3.3V-2.5V=0.8V) after less than MP3 and MP4 serial connection, so MP3 and MP4 transistor then are not on-state.Because the conducting meeting of transistor MN3, MN4 and MN5 makes second to select block to form ground state, so make that the input voltage of voltage transitions block 140 is 0V.Afterwards, because transistor MP2 is a conducting state, transistor MN2 then is a not on-state, therefore, and the output signal V of voltage transitions block 140
OBe 1.2V.In like manner, as applied signal voltage V
IDuring for 3V, its voltage transitions block 140 obtains digital output signal V
OStill be 1.2V.
To emphasize that at this first voltage selection block 110 of the present invention and second voltage selection block 130 can be according to AV
DDAnd V
IMagnitude of voltage come design voltage to select number of elements in the block so that make the input signal V of different size
ICan convert the corresponding high levle or the digital signal of low level to.For example, work as AV
DDDuring for 4.2V, and wish V equally
IIn the time of more than 2V, converting the digital signal output of high levle to, then can select block 110 to form first voltage with the PMOS of 2 serial connections.According to previous circuit behaviour mode, work as V
IDuring less than 2.1V, the second selection block is a not on-state, and the first selection block is conducting, and therefore, the output signal of voltage transitions block 140 is 0V.Work as V
IDuring greater than 2.1V, it is conducting state that second voltage is selected block 130, and first voltage selects block 110 to be not conducting, therefore, and the output signal V of voltage transitions block 140
OBe digital signal 1.2V.So, work as AV
DDDuring rising, then can be via selecting the PMOS quantity in the block 110 to select V to first voltage
IValue.
In like manner, if will be with higher V
IVoltage could conversion digital signal noble potential the time, then can select to increase by second voltage and select the NMOS quantity in the block 130 to reach.For example, work as AV
DDDuring for 4.2V, and wish V
IIn the time of more than 3V, could changing the digital signal output of a high levle, then can select block to form with second with the NMOS of 3 serial connections.According to previous circuit behaviour mode, work as V
IWhen 2.8V (i.e. 4 NMOS form voltage drops), it be not on-state that second voltage is selected block 130, and first voltage to select block 110 be conducting, therefore, the output signal V of voltage transitions block 140
OBe 0V.Work as V
IDuring greater than 2.8V, it is conducting state that second voltage is selected 130 of blocks, and first voltage selects block 110 then to be not conducting, therefore, and the output signal V of voltage transitions block 140
OBe digital signal 1.2V.Via above-mentioned, the present invention can be according to V
IAnd AV
DDThe variation of magnitude of voltage selects the MOS quantity in first block and second block to reach the purpose that converts digital signal output to.So need not to utilize extra circuit to produce reference voltage.
As shown in Figure 4, through the output waveform after simulation and the digital signal conversion, all can very precipitous (sharp) in voltage turn-on conversion place, make that the actual transfer point of input voltage is difficult for grasping.Therefore, for making the voltage transitions waveform can steepen, the present invention proposes another tool preferred embodiment, as shown in Figure 7, it adds voltage waveform trimming block 150 between reverser 120 and voltage transitions block 140, wherein voltage waveform trimming block 150 is formed by the formed reverser serial connection of even number cmos circuit.The input end of voltage waveform trimming block 150 is connected with reverser 120, and output terminal then is connected with the input end of voltage transitions block 140, and the one end connects aanalogvoltage AV
DD, the other end then connects earth point.As aanalogvoltage AV
DDBehind waveform trimming block 150, can make the output waveform of the digital signal of conversion can be more precipitous.In the time of as if the cmos circuit in the voltage waveform trimming block 150 the more, then can make output waveform near ideal waveform.
In the embodiments of the invention, utilize the voltage of forming by several PMOS and nmos pass transistor to select block, thus inner aanalogvoltage (for example: 3.3V or 4.2V) can be utilized, so need not to utilize extra circuit to produce reference voltage.Afterwards, utilize voltage waveform trimming block 150 that signal output waveform is repaired.At last, utilize the voltage transitions block to convert input signal to corresponding digital signal.In this design, utilize the design rule of CMOS (Complementary Metal Oxide Semiconductor) transistor (CMOS) to come layout, thereby avoid the use of comparer, so but the shared area of chip of the design of facilitating chip and reduction means, and make the consumption of operand power significantly reduce.In addition, because of analog DC signal AV
DD(for example: 3.3V or 4.2V) for cmos circuit, belonged to high voltage, so and AV
DDThe element that connects all need use the structure of high voltage devices.
When many group direct current signal conversion digital signal devices of the present invention embed (embedded) in the CD-ROM drive chip, can do conversion to the different DC voltage position standard (for example: 0.5V, 1.5V and 2.5V) of input chip, to distinguish noble potential or electronegative potential, to export a digital signal DV
DD
The above is specific embodiments of the invention only, is not in order to limit claim of the present invention; All other do not break away from the equivalence of being finished under the disclosed spirit and changes or modification, all should be included in the described claim.
Claims (11)
1. the device of the direct current signal of group more than kind conversion digital signal is characterized in that, comprising:
One first voltage is selected block, and this first voltage selects an end of block to connect an aanalogvoltage;
One reverser, the input end of this reverser connects input signal, and this input signal has several not coordination standards, and the other end of this reverser connects above-mentioned first voltage and selects block;
One second voltage is selected block, and this second voltage selects an end of block to connect above-mentioned reverser, and other end ground connection; And
One voltage transitions block, the input end of this voltage transitions block connects the output terminal of above-mentioned reverser, and an end of this voltage transitions block connects a digital voltage, and other end ground connection, and produce digital signal output;
Wherein above-mentioned first voltage selects block and above-mentioned second voltage to select block in order to control this input signal interval size during a flash when the transition, this instantaneous interval running that influences above-mentioned reverser.
2. the device of many group direct current signal conversion digital signals as claimed in claim 1, the first wherein above-mentioned voltage selects block to be made up of at least one three-terminal element.
3. the device of many group direct current signal conversion digital signals as claimed in claim 2, wherein this three-terminal element is a P-type mos field-effect transistor.
4. the device of many group direct current signal conversion digital signals as claimed in claim 1, the second wherein above-mentioned voltage selects block to be made up of at least one three-terminal element.
5. the device of many group direct current signal conversion digital signals as claimed in claim 4, wherein this three-terminal element is a N type metal oxide semiconductor field-effect transistor.
6. the device of many group direct current signal conversion digital signals as claimed in claim 2, wherein this three-terminal element is and is higher than 3.3V or the above voltage component of 4.2V.
7. the device of many group direct current signal conversion digital signals as claimed in claim 1, wherein this reverser is a voltage component that is higher than more than 3.3V or the 4.2V.
8. the device of many group direct current signal conversion digital signals as claimed in claim 1, wherein this voltage transitions block is a cmos circuit structure.
9. the device of many group direct current signal conversion digital signals as claimed in claim 1, wherein also comprise voltage waveform finishing block, the input end of this voltage waveform finishing block is connected with the output terminal of above-mentioned reverser, the output terminal of this voltage waveform finishing block then is connected with the input end of above-mentioned voltage transitions block, one end of this voltage waveform finishing block connects the simulation direct current signal, and other end ground connection.
10. the device of many group direct current signal conversion digital signals as claimed in claim 9, wherein above-mentioned voltage waveform finishing block is made up of the even number reverser.
11. being, the device of many group direct current signal conversion digital signals as claimed in claim 10, wherein above-mentioned even number reverser be higher than 3.3V or the above voltage component of 4.2V.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100335783A CN1324320C (en) | 2004-04-07 | 2004-04-07 | Multi-pack d.c signal conversion digital signal device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100335783A CN1324320C (en) | 2004-04-07 | 2004-04-07 | Multi-pack d.c signal conversion digital signal device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1564004A CN1564004A (en) | 2005-01-12 |
| CN1324320C true CN1324320C (en) | 2007-07-04 |
Family
ID=34481349
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2004100335783A Expired - Lifetime CN1324320C (en) | 2004-04-07 | 2004-04-07 | Multi-pack d.c signal conversion digital signal device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1324320C (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4415883A (en) * | 1978-09-01 | 1983-11-15 | Siemens Aktiengesellschaft | Circuit arrangement for converting digital signals in particular PCM signals, into corresponding analog signals with a R-2R chain network |
| JPH0915272A (en) * | 1995-06-30 | 1997-01-17 | Shinko Seisakusho Co Ltd | Voltage measuring circuit |
| US5619204A (en) * | 1995-02-27 | 1997-04-08 | Analog Devices, Incorporated | Analog-to-digital converter with optional low-power mode |
| US6465789B1 (en) * | 1999-05-19 | 2002-10-15 | Canon Kabushiki Kaisha | Signal processing apparatus |
-
2004
- 2004-04-07 CN CNB2004100335783A patent/CN1324320C/en not_active Expired - Lifetime
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4415883A (en) * | 1978-09-01 | 1983-11-15 | Siemens Aktiengesellschaft | Circuit arrangement for converting digital signals in particular PCM signals, into corresponding analog signals with a R-2R chain network |
| US5619204A (en) * | 1995-02-27 | 1997-04-08 | Analog Devices, Incorporated | Analog-to-digital converter with optional low-power mode |
| JPH0915272A (en) * | 1995-06-30 | 1997-01-17 | Shinko Seisakusho Co Ltd | Voltage measuring circuit |
| US6465789B1 (en) * | 1999-05-19 | 2002-10-15 | Canon Kabushiki Kaisha | Signal processing apparatus |
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| Publication number | Publication date |
|---|---|
| CN1564004A (en) | 2005-01-12 |
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