CN1315193C - Inclined active area semiconductor assembly structure of integrated circuit - Google Patents
Inclined active area semiconductor assembly structure of integrated circuit Download PDFInfo
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- CN1315193C CN1315193C CNB031434231A CN03143423A CN1315193C CN 1315193 C CN1315193 C CN 1315193C CN B031434231 A CNB031434231 A CN B031434231A CN 03143423 A CN03143423 A CN 03143423A CN 1315193 C CN1315193 C CN 1315193C
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Abstract
The present invention relates to a semiconductor assembly which is characterized in that the present invention comprises a gate oxidizing layer positioned on a substrate, a gate electrode positioned on the gate oxidizing layer, titled active areas which are respectively positioned at both sides of the gate electrode in the substrate, contact windows assembled in each corresponding titled active areas, and oxide line spacers OLS which are assembled at the side of each corresponding contact window for widening contact areas and used as the contact structure of storage cells or storage nodes.
Description
Technical field
The present invention relates to the improvement structure of a kind of semiconductor dynamic random access holder (DRAM), particularly a kind of dynamic randon access holder with oblique active region (titled active area).
Background technology
Dynamic randon access holder (dynamic random access memory; DRAM) be a kind of main volatility (volatile) holder.Storage element (cell) is made of capacitor and transistor usually, transistorized doped region or title active region (active area) are connected with an end of electric capacity, the other end of electric capacity then is connected with reference potential, therefore, make the manufacture craft that the DRAM memory cell has comprised transistor AND gate electric capacity.General typical dynamic randon access holder is to make mos field effect transistor (MOSFET) and capacitor on semi-conductive substrate, and the charge-storage electrode (storage node) that utilizes contact hole to connect capacitor is done electrically to contact with the source electrode of mos field effect transistor.Contact with the electrical of source area by capacitor, digital information is stored in capacitor and above-mentioned transistor, bit line, the word line array of mat obtained stored numerical data.Contact with the electrical of source area by capacitor, digital data storage obtains the numerical data of capacitor in capacitor and mat mos field effect transistor, bit line (bit line), word line (word line) array.General plate capacitor is the most frequently used capacitance structure, in order to increase the density of assembly, the DRAM technology is tended to size is reduced, because the reduction of size, relative capacity area also descends and causes the minimizing of electric capacity storage capacity, makes refreshing (refresh) frequency and also can increase electric capacity.In order to solve the above problems and then to have developed ditching type electric capacity storage data and stacking-type electric capacity, ditching type electric capacity has the phenomenon of leakage current sometimes.
Fig. 1 is traditional array type contact hole active region structure.Prior art utilizes ion implantation technique (ion implantation) to produce active region or the steelyard slepsydra utmost point and source region (the source and drain) of array type in substrate.Afterwards, utilize etching and deposition technique to form self-aligned contacts (self-aligned contact; SAC) conductivity is bolted among the dielectric layer, can utilize CVD to be deposited on polysilicon refilling and enter among the contact perforation, again etch-back or grinding and form above-mentioned polysilicon bolt.The live width permission (CD Variation) of the live width permission of capacitor top electrode (line width tolerance) and bit line contact, relevant with the mis-alignment scope (mis-align spec) of photoetching making technology.Along with the lasting reduction of live width, it is more and more little that the requirement of spacing also becomes, and so will make the isolation of bit line contact and crown capacitor top electrode, becomes the problem of overslaugh manufacture craft yield (yield).On the other hand, peripheral circuit is darker than the bit line contact hole of central circuit, has also deepened the problem on the manufacture craft.Based on Progress in technique, the structure of Fig. 1 is restricted, and therefore is necessary to propose a new structure.
Summary of the invention
As mentioned above, how to break through the limit of prior art, widening memory cell contact structures and storage electrode contact structures is technical problem to be solved by this invention, for this reason, the purpose of this invention is to provide a kind of semiconductor assembly structure, be used in particular for the memory cell contact structures in the dynamic randon access holder with oblique active region (titled active area).
Another object of the present invention provides a semiconductor assembly structure with oblique active region (titled active area), is used in particular for the storage electrode contact structures in the dynamic randon access holder.
The solution of the present invention is as follows:
According to semiconductor assembly structure of the present invention, its characteristics are to comprise: gate oxide is positioned on the substrate; Grid is positioned on the above-mentioned gate oxide; Oblique active region (titled active area) is positioned at these grid both sides among this substrate; Contact hole (contact window) is disposed at and states on the oblique active region (titled active area) on corresponding; Oxidation linear gap wall (Oxideline spacer; OLS), be disposed at the side of corresponding this contact hole (contact window), use as memory cell (cell) or storage electrode (storage node) contact structures to widen contact area.Wherein above-mentioned oblique active region (titled active area) comprises two ends and is connected by horizontal part and a rake and is formed.This contact hole (contact window) is disposed at side on this rake.Wherein above-mentioned oxidation linear gap wall (oxide line spacer; OLS) be shaped as linear strip or T shape.Description of drawings
Preferred embodiment of the present invention will be aided with following figure and do more detailed elaboration in comment backward:
Fig. 1 is the prior art constructions schematic diagram.
Oblique active region (the titled active area) structural representation of Fig. 2 dynamic randon access holder of oblique active region (titled active area) for the present invention has.
The contact structure schematic diagram of Fig. 3 dynamic randon access holder of oblique active region (titled active area) for the present invention has.
The schematic diagram of Fig. 4 dynamic randon access reservoir configuration of oblique active region (titled active area) for the present invention has.
Embodiment
The present invention will disclose is a kind of memory cell of the dynamic randon access holder with oblique active region (titled active area) and the contact structures of storage electrode.Manufacture method of the present invention is described below: as a substrate, for example can use a crystal orientation for＜100 with semi-conducting material〉monocrystalline silicon as the substrate of the embodiment of the invention.Subsequently, area of isolation such as shallow trench formula area of isolation (shallow trenchisolation; STI) or oxide in field (FOX) utilize known fabrication techniques among substrate in advance.Then, silicon dioxide layer is formed on the substrate as grid oxic horizon, and this silicon dioxide layer is generally and utilizes thermal oxidation method to form, and the manufacture craft temperature is about and forms about 50 to 200 dusts of thickness between 700 to 1100 ℃.Still see also Fig. 2, grid structure utilizes traditional technology to be patterned on the disk, grid structure can comprise polysilicon layer and be deposited on the silicon dioxide layer, with an embodiment, this polysilicon layer utilizes chemical vapour deposition technique (CVD) to form, and forms grid structure with photoetching and etching technique then.Form doped region or active region (active area) as drain electrode and source electrode with the ion injection mode then.See also Fig. 2, the present invention is characterized in that structure of the present invention is oblique active region (the titled active area) structural representation with dynamic randon access holder of oblique active region (titled active area).Other can be made according to prior art as definition electric capacity or word line (word line).Compared to prior art, active region of the present invention (titled active area) structure 200 adopts two ends to be connected and to be formed with-rake 220 by horizontal part 210.Semiconductor assembly structure of the present invention is characterised in that and comprises: gate oxide is positioned on the substrate, and grid is positioned on the above-mentioned gate oxide.Tiltedly active region (titled activearea) is positioned among this substrate and the both sides of grid.Contact hole (contact window) is disposed on the corresponding above-mentioned oblique active region (titled active area), oxidation linear gap wall (oxide linespacer; OLS) be disposed at the side of corresponding this contact hole (contact window), use as memory cell (cell) or storage electrode (storage node) contact structures to widen contact area.
Be illustrated in figure 3 as the contact structure schematic diagram that the present invention has the dynamic randon access holder of oblique active region (titled active area).Several contact holes (contact window) 300 are disposed on the oblique active region (titled active area) 200.With an embodiment, contact hole (contact window) 300 is disposed at side on the rake 220 of a corresponding oblique active region (titled activearea) 200.Two oxidation linear gap wall (Oxide line spacer; OLS) 310 be disposed at corresponding contact window (Contact window) 300 both sides, to widen contact area (area).Figure 4 shows that the present invention has the schematic diagram of the dynamic randon access reservoir configuration of oblique active region (titled active area).Wherein remove and comprise oblique active region (titled activearea) 200, contact hole (Contact window) 300 and oxidation linear gap wall (Oxide linespacer; OLS) outside 310, comprise grid structure 400 configurations and word line (word line) 410 configurations.
After forming grid structure, can utilize etching and deposition technique formation conductivity to be bolted among the dielectric layer of grid top, can use polysilicon bolt (poly plug) to this embodiment, in preferred embodiment, can utilize CVD to be deposited on polysilicon refilling and enter among the contact perforation, again etch-back or chemical mechanical milling method (CMP) and form above-mentioned polysilicon bolt.With most preferred embodiment, polysilicon of the present invention is polysilicon (doped polysilicon) that mixes or the polysilicon (in-situdoped polysilicon) that mixes synchronously.Above-mentioned dielectric layer can adopt insulating material such as oxide layer, BPSG, PSG or other impartial materials with function as insulating barrier.
Invention with preferred embodiment explanation as above and is familiar with this field skill person, in not breaking away from spiritual scope of the present invention, retouch when doing a little change, but protection scope of the present invention more ought on claim scope of the present invention and etc. same domain decide.
Claims (10)
1. semiconductor assembly structure is characterized in that comprising:
Gate oxide is positioned on the substrate;
Grid is positioned on the above-mentioned gate oxide;
Oblique active region is positioned at these grid both sides among this substrate;
Contact hole is disposed at and states on the oblique active region on corresponding;
Oxidation linear gap wall is disposed at side that should contact hole, uses as the memory cell contact structures to widen contact area.
2. semiconductor assembly structure as claimed in claim 1 is characterized in that, above-mentioned oblique active region comprises two ends and is connected by horizontal part and a rake and formed.
3. semiconductor assembly structure as claimed in claim 2 is characterized in that above-mentioned contact hole is disposed at side on this rake.
4. semiconductor assembly structure as claimed in claim 1 is characterized in that, above-mentioned oxidation linear gap wall be shaped as linear strip.
5. semiconductor assembly structure as claimed in claim 1 is characterized in that, above-mentioned oxidation linear gap wall be shaped as the T shape.
6. semiconductor assembly structure is characterized in that comprising:
Gate oxide is positioned on the substrate;
Grid is positioned on the above-mentioned gate oxide;
Oblique active region is positioned at these grid both sides among this substrate;
Contact hole is disposed at and states on the oblique active region on corresponding;
Oxidation linear gap wall is used as the storage electrode contact structures to widen contact area.
7. semiconductor assembly structure as claimed in claim 6 is characterized in that, above-mentioned oblique active region comprises two ends and is connected by horizontal part and a rake and formed.
8. semiconductor assembly structure as claimed in claim 7 is characterized in that above-mentioned contact hole is disposed at side on this rake.
9. semiconductor assembly structure as claimed in claim 6 is characterized in that, above-mentioned oxidation linear gap wall be shaped as linear strip.
10. semiconductor assembly structure as claimed in claim 6 is characterized in that, above-mentioned oxidation linear gap wall be shaped as the T shape.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB031434231A CN1315193C (en) | 2003-09-30 | 2003-09-30 | Inclined active area semiconductor assembly structure of integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB031434231A CN1315193C (en) | 2003-09-30 | 2003-09-30 | Inclined active area semiconductor assembly structure of integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1604333A CN1604333A (en) | 2005-04-06 |
| CN1315193C true CN1315193C (en) | 2007-05-09 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB031434231A Expired - Lifetime CN1315193C (en) | 2003-09-30 | 2003-09-30 | Inclined active area semiconductor assembly structure of integrated circuit |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5523965A (en) * | 1993-12-27 | 1996-06-04 | Hitachi, Ltd. | Semiconductor memory device and method of manufacturing same |
| US6459113B1 (en) * | 2000-08-10 | 2002-10-01 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor integrated circuit device and method of manufacturing the same, and cell size calculation method for DRAM memory cells |
-
2003
- 2003-09-30 CN CNB031434231A patent/CN1315193C/en not_active Expired - Lifetime
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5523965A (en) * | 1993-12-27 | 1996-06-04 | Hitachi, Ltd. | Semiconductor memory device and method of manufacturing same |
| US6459113B1 (en) * | 2000-08-10 | 2002-10-01 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor integrated circuit device and method of manufacturing the same, and cell size calculation method for DRAM memory cells |
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| Publication number | Publication date |
|---|---|
| CN1604333A (en) | 2005-04-06 |
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Owner name: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING Effective date: 20111205 |
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Effective date of registration: 20111205 Address after: 201203 Shanghai Zhangjiang Road, Zhangjiang High Tech Park of Pudong New Area No. 18 Co-patentee after: Semiconductor Manufacturing International (Beijing) Corp. Patentee after: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) Corp. Address before: 201203 Shanghai Zhangjiang Road, Zhangjiang High Tech Park of Pudong New Area No. 18 Patentee before: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) Corp. |
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Granted publication date: 20070509 |