CN1314115C - Multiple metallic layers inner connecting wire structure - Google Patents
Multiple metallic layers inner connecting wire structure Download PDFInfo
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- CN1314115C CN1314115C CNB2004100462882A CN200410046288A CN1314115C CN 1314115 C CN1314115 C CN 1314115C CN B2004100462882 A CNB2004100462882 A CN B2004100462882A CN 200410046288 A CN200410046288 A CN 200410046288A CN 1314115 C CN1314115 C CN 1314115C
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Abstract
The present invention discloses an internal wire connecting structure of multiple metal layers, which is arranged on a semiconductor substrate with a circuit. The structure comprises a dielectric layer deposited on the semiconductor substrate, a first metal wire layer and a second metal wire layer which are respectively embedded into the dielectric layer, a plurality of first plugs, a plurality of second plugs as well as a third metal wire layer and a fourth metal wire layer which are arranged above the first metal wire layer and the second metal wire layer, wherein the first metal wire layer is in parallel with the second metal wire layer at a distance d; the first plugs are arranged in the dielectric layer, are connected with the first metal wire layer, and are electrically connected with the circuit of the semiconductor substrate; the second plugs are arranged in the dielectric layer, are connected with the second metal wire layer, and are electrically connected with the circuit of the semiconductor substrate; the third metal wire layer and the fourth metal wire layer are connected with the first plugs and the second plugs to form a metal dual-mosaic structure, the third metal wire layer is adjacent to one side of the fourth metal wire layer at a distance which is larger than 1/2 of d of the distance between the first metal wire layer and the second metal wire layer, and the third metal wire layer is in parallel with the fourth metal wire layer at a distance d.
Description
The present invention divides an application for No. the 02107425.9th, Chinese patent application, and the applying date of original application is on March 15th, 2002, and application number is 02107425.9, and denomination of invention be " a multi-metal layer connecting line construction and test the method for dielectric layer between metal layers intensity ".
Technical field
The present invention relates to a kind of semiconductor structure, the multi-metal layer internal connection-wire structure of dielectric layer between metal layers crack (crack) in particularly a kind of prevention semiconductor.
Background technology
In semiconductor wafer, dielectric oxide between common meeting deposition oxide cambium layer in the MOS electric crystal structure is as insulating barrier or protective layer.And wherein be used for the dielectric material of metal interlevel, and then be metal interlevel dielectric oxide layer (Inter Metal Dielectric oxide, IMD oxide), be mainly used in clearance filled (the gap fill) of multiple layer metal interlayer and planarization etc.
And when the main circuit zone forms multi-metal layer intraconnections, also form large-area multi-metal layer structure in the land of above-mentioned periphery (bonding pad).This is formed at outermost multiple layer metal layer, is mainly used in the corresponding lead foot that wire bonder (bonder) is connected in this metal level with metal wire saddle (lead frame).Therefore, outermost metal level is as the interface between internal circuit and outer signal lead foot, to receive such as outer signals such as power supply signal, ground signalling or input/output signals.
Fig. 1 a and Fig. 1 b have illustrated the multi-metal layer internal connection-wire structure of general land.Among Fig. 1 a, have in the circuit silicon substrate 10 that several semiconductor element (not shown) constituted, form the metal level of 12A, 12B, 12C, 12D and 12T, wherein 12T is the top-level metallic (top metal) as the land, the metal interlevel of 12A-12D, isolated with interlayer dielectric layer IMD 10A-10D respectively, and, form the structure of five layers of metal level, four layers of connector by metal plug 14 (metal plug) the conducting metal level that matrix form is arranged.Wherein metal plug group 14 is formed by the interlayer hole (viahole) in the dielectric layer of inserting by metal material between two metal levels usually, main purpose is to make lower metal layer, and is communicated with to form with circuit (not shown) in the below substrate 10 and electrically connects.Referring to Fig. 1 b, wherein 1A and 1B represent two group of five laminar metal plug array respectively, and the stress structure between two groups often can't be supported in the dielectric layer between metal layers zone 16 between two groups of metal plug arrays, and produce the crack 16 among Fig. 1 a.
Yet, this metal interlevel dielectric oxide layer break or the crack can cause the reliability (reliability) of semiconductor chip to descend.When electronic product operated, chip is carried out the high temperature that is produced made the crack increase because of the cold shrinkage and thermal expansion face easily, and then has influence on the stability of chip itself.Since the instability on the crack of chip may be caused electrically, the related undesired even damage of function that makes electronic product.Therefore in the production of IC chip, metal interlevel dielectric vapour slabbing is stitched formed potential risk, the target that all is in the semiconductor manufacturing to make every effort to avoid.
In order to solve the IMD crack, a kind of common mode is to change the IMD material, for example will be with high density plasma enhanced chemical vapor deposition (High Density Plasma Chemical Vapor Deposition, HDPCVD) replace medium-sized air pressure chemical vapour deposition (CVD) (semi-atmospheric pressurechemical vapor deposition, SACVD), to generate the IMD layer of finer and close (compressive).Yet only change the part character of IMD layer material, and can't solve the IMD problem of cracks fully.With 0.25 micron system is example, and the IMD crack usually takes place.After changing material in the above described manner, the IMD crack still takes place.And the position that the IMD crack takes place is relevant with the layout designs of metal plug array (metal via array), and the probability in the layout generation IMD crack of the contact hole array of some form is generally higher.
Summary of the invention
The crack appears for fear of between above-mentioned dielectric layer between metal layers, one object of the present invention is to provide a kind of and can assesses between two groups of neighbour metal double-insert structures, the method of its dielectric layer between metal layers intensity can be assessed the intensity of the metal interlevel dielectric material of selected use.
A further object of the present invention is to provide a kind of multi-metal layer internal connection-wire structure, the metal level that can utilize two groups of neighbour metal double-insert structures apart from one another by design, produce with the crack of avoiding dielectric layer between metal layers.
Another object of the present invention is multi-metal layer internal connection-wire structure, is to allow two groups of neighbour metal double-insert structures keep one more than or equal to 3 microns distance, produces with the crack of avoiding dielectric layer between metal layers.
According to a kind of method of testing dielectric layer between metal layers intensity of the present invention, be suitable between at least two group metal double-insert structures, be that wherein first metal line layer is parallel to second metal line layer prior to first and 1 second metal line layer of the identical live width of formation in the semiconductor substrate.And on first and second metal line layer, define square first area of the same area and second area respectively, and the square length of side approximates the live width of metal wire, and arrange with diagonal way in first and second zone.Then deposit a dielectric layer on first and second metal line layer, and on first and second regional dielectric layer, form n * m first and second connector respectively, form with first and second metal line layer respectively and electrically connect, m and n are natural number, and first and second connector is respectively in equidistant mode, one side by the adjacent matrix that is arranged as n * m in first and second zone.Then form the 3rd metal wire and the 4th metal wire on this dielectric layer, wherein the 3rd and the 4th metal wire is right against this first and second metal wire respectively, respectively to form one group of metal double-insert structure in this first and second zone.Check at last whether first and second interregional dielectric layer has the crack, when the crack produces, represent that this intensity of dielectric layer is lower than standard.
Wherein, the present invention also can repeat to form the metal double-insert structure on the 3rd and the 4th metal wire, forming the above multi-metal layer internal connection-wire structure of two-fold, and checks whether dielectric layer between metal layers therebetween has the crack to produce.
Produce the crack for fear of between dielectric layer between metal layers, the present invention proposes a kind of multi-metal layer internal connection-wire structure, is arranged at one and has at the semiconductor-based end of circuit, and this structure comprises: at least one dielectric layer was deposited on this semiconductor-based end; One first metal line layer and one second metal line layer, be embedded in respectively in this dielectric layer, wherein this first metal line layer is parallel to this second metal line layer with one apart from d, and this first metal line layer and this second metal line layer electrically connect the circuit at this semiconductor-based end; A plurality of first and second connectors are arranged at respectively in this dielectric layer and are connected with this first and second metal line layer, constitute with the circuit at this semiconductor-based end to electrically connect; And one the 3rd metal line layer and one the 4th metal line layer be positioned at this first and second metal line layer top, form the metal double-insert structure respectively respectively and between described first and second connector, wherein, the 3rd metal line layer adjacent to one side of the 4th metal line layer at a distance of this second metal line layer of below adjacent to one side of this first metal line layer distance greater than 1/2d, and the 4th metal line layer with this apart from d, be parallel to the 3rd metal line layer; Wherein the 3rd metal line layer and second metal line layer some intermesh overlapping.
According to the present invention, another kind avoids producing between dielectric layer between metal layers the multi-metal layer internal connection-wire structure in crack, also is arranged at one and has at the semiconductor-based end of circuit, and comprising: at least one dielectric layer was deposited on this semiconductor-based end; One first metal line layer and one second metal line layer are embedded in respectively in this dielectric layer, and wherein first metal line layer is parallel to second metal line layer with more than or equal to 3 microns distance; A plurality of first and second connectors are arranged in this dielectric layer and are connected with first and second metal line layer, constitute with the circuit at the semiconductor-based end to be electrically connected; And one the 3rd metal line layer and one the 4th metal line layer, be positioned at first and second metal line layer top, and form two groups of metal double-insert structures between described first and second connector respectively, wherein the 3rd metal line layer is parallel to the 4th metal line layer with more than or equal to 3 microns distance.
The present invention is a multi-metal layer internal connection-wire structure of avoiding producing between dielectric layer between metal layers the crack, also can repeat to form the metal double-insert structure on the 3rd and the 4th metal wire, to form the above multi-metal layer internal connection-wire structure of two-fold.
For allow above-mentioned purpose of the present invention, feature, and advantage can become apparent, below conjunction with figs. elaborate.
Description of drawings
Fig. 1 a and 1b are depicted as the multi-metal layer internal connection-wire structure in zone, existing land;
Figure 2 shows that top view according to first kind of multi-metal layer metal plug array design in one embodiment of the invention;
Figure 3 shows that top view according to second kind of multi-metal layer metal plug array design in one embodiment of the invention;
Figure 4 shows that top view according to the third multi-metal layer metal plug array design in one embodiment of the invention;
Figure 5 shows that top view according to the 4th kind of multi-metal layer design in one embodiment of the invention;
Fig. 6 a and 6b are depicted as according to a kind of method of testing dielectric layer between metal layers intensity in one embodiment of the invention;
Figure 7 shows that according to a kind of multi-metal layer internal connection-wire structure in one embodiment of the invention;
Figure 8 shows that according to the another kind of multi-metal layer internal connection-wire structure in one embodiment of the invention.
Embodiment
In order to improve dielectric layer between metal layers institute potential fracture, therefore the inventor waits the array structure layout of the metal plug group in four kinds of multi-metal layer intraconnections of design, so as to testing the influence of different metal plug arrays for dielectric layer between metal layers intensity respectively.
Design one
Fig. 2 is the top view of first kind of multi-metal layer metal plug array design.Have one at the semiconductor-based end of circuit, form the two parallel metal line layers 22 and the live width of 24. liang of metal wires and be 50 microns, and adjacent between the two 0.8 micron.Follow smooth covering one dielectric layer, use as isolating.And on metal line layer 22 and 24, select two square metal plug area 2A and the 2B that arrange with diagonal respectively, and in this zone, in dielectric layer, forms the metal plug 21 of equidistant arrangement in the square matrix mode.And in first group of design, its characteristics are the diagonal corners adjacent with 2B at two regional 2A, are the mode of x/2 respectively defines first-class lumbar triangle shape in two zones avoidance regional 23 and 25 with the height.And in delta-shaped region 23 and 25, any metal plug 21 is not set.Wherein, be 10,20,35 and 50 microns with X respectively, form the avoidance triangle of different area size.And can this design up pile up the multi-metal layer internal connection-wire structure that forms the different numbers of plies in regular turn.
Design two
Fig. 3 is the top view of second kind of multi-metal layer metal plug array design.Have one at the semiconductor-based end of circuit, form the two parallel metal line layers 32 and the live width of 34, two metal wires and be 50 microns, and adjacent between the two 0.8 micron.Follow smooth covering one dielectric layer, as isolating usefulness, and on metal line layer 32 and 34, select two square region 3A and the 3B that arrange with diagonal respectively, and in this zone, in dielectric layer, forms the metal plug 31 of arrangement equidistantly in the square matrix mode.And in second group of design, its characteristics are to control metal plug 31 distance h each other, are respectively 0.4,0.7,0.9,1.2,1.5,1.8,2.0 and 3.0 micron, and eight kinds of distances are tested.And can this design up pile up the multi-metal layer internal connection-wire structure that forms the different numbers of plies in regular turn.
Design three
Fig. 4 is the top view of the third multi-metal layer metal plug array design.Have one at the semiconductor-based end of circuit, form the two parallel metal line layers 42 and the live width of 44, two metal wires and be 50 microns, and adjacent between the two 0.8 micron.Follow smooth covering one dielectric layer, use as isolating.And on metal line layer 42 and 44, select two square region 4A and the 4B that arrange with diagonal respectively, and in this zone, in dielectric layer, forms the metal plug 21 of equidistant arrangement in the square matrix mode.And in the 3rd group of design, its characteristics are metal plug 41 and not exclusively fill up 4A and 4B zone, but open calculation by the adjacent end of two metal line layers, in length is in the zone of Y for Z is wide, distance with 0.4 micron at interval is provided with 41 groups of metal plugs with matrix-style, wherein can be by (Z, Y) (micron/micron)=(30/40), (30/50), (20/50), (10/50), (40/40), (30/30), (20/20) and (10/10) etc. take eight groups of zones that metal plug 41 is set.Then pile up in regular turn in this way and form multi-metal layer internal connection-wire structure.
Design four
Fig. 5 is the top view of the 4th kind of multi-metal layer metal plug array design.Have one at the semiconductor-based end of circuit, form the two parallel metal line layers 52 and the live width of 54, two metal wires and be 100 microns, and neighbor distance d between the two.Follow smooth covering one dielectric layer, use as isolating.And select two square region 5A and the 5B that arrange with diagonal on respectively at metal line layer 52 and 54, and in this zone, in dielectric layer, forms the metal plug 51 of equidistant arrangement in the square matrix mode.And in the 4th group of design, its characteristics are to be designed to multiple distance such as 0.8,1.0,1.2,2,3,4,5,6,8,10 and 15 micron apart from d between two metal line layers, widen distance between two metal line layers with understanding, for the influence of dielectric layer between metal layers.
Then referring to table 1, the nine kinds of different metal numbers of plies of the above-mentioned four kinds of designs of oneself employing and the structure of IMD layer material be describeds.
Table 1
| Structure number | ||||||||||
| I | II | III | IV | V | VI | VII | VIII | IX | ||
| The IMD structure | SACVD #+FEIEO * | v | v | v | v | v | ||||
| HDPCVD ％+PEIEOS | v | v | v | v | ||||||
| Multi-metal layer intraconnections piles up the number of plies | 6 layers of metal level/5 layer metal plug | v | v | |||||||
| 5 layers of metal level/4 layer metal plug | v | v | ||||||||
| 4 layers of metal level/3 layer metal plug | v | v | ||||||||
| 3 layers of metal level/2 layer metal plug | v | v | ||||||||
| 2 layers of metal level/1 layer metal plug | v | |||||||||
#: medium-sized air pressure chemical vapour deposition (CVD)
%: high density plasma enhanced chemical vapor deposition
*: tetraethoxy-silicane (plasma enhanced tetraethyl orthosilicate)
With the above-mentioned nine kinds of structures in first table, make respectively, and whether its dielectric layer between metal layers of finishing finished product of practice examining have the crack to produce, and the finished product interpretation of result of various combinations is referring to table 2 with four kinds of designs.
Table 2
| Structure number | |||||||||
| I | II | III | IV | V | VI | VII | VIII | IX | |
| Design one | 35 *** | 0 * | 0 | 0 | X ** | X | 35 | 0 | 0 |
| Design two | 0.7 | 0.7 | 0 | 0 | X | X | 1.5 | 0 | 0 |
| Design three | 10×10 | 20×20 | 0 | 0 | X | X | 10×50 | 0 | 0 |
| Design four | 3 | 3 | 0 | 0 | X | 3 | 1 | 0 | 0 |
*: the complete free from flaw of form of ownership
*: form of ownership all has slight crack
* *: this form is above flawless
By design one result as can be seen, the structure that the number of plies is few (III, IV, VIII, IX) can be by at two adjacent regional 2A and the cushion space that no connector is set 23 and 25 between 2B, and avoids the generation in crack.Yet in sandwich construction, even adopt the formed dielectric layer of HDPCVD+PETEOS, in 6 layers of metal structure, still must keep the x value greater than 35 microns avoidance zone, just can avoid the crack of dielectric layer between metal layers, the scope of show to increase avoiding the zone still has the limitation part for the improvement of different I MD material.
And in design two, mainly widen metal plug distance each other, by the result in second table as can be seen, when adopting the formed dielectric layer of HDPCVD+PETEOS, then need only the distance that keeps between metal plug greater than 0.7 micron, then can avoid the generation in metal crack fully.Yet in the formed dielectric layer of SACVD+PETEOS, only widen the distance between metal plug, still can't improve multiple layer metal layer structure, as structure V and VI, the dielectric medium crack.
In design three, the main distributing position that changes the metal plug group on two metal line layers, can obviously find out, in six layers of structure I, when adopting the formed dielectric layer of HDPCVD+PETEOS, the metal plug distributed areas of metal line layer are less than 10 * 10 microns, and in the structure of five layers of metal level, in the time of must be less than 20 * 20 microns, just can avoid the generation in dielectric layer between metal layers crack.And when adopting SACVD+PETEOS, then sandwich construction V and VI all can't avoid the crack generation.And by the design three in as can be seen, except in the multi-metal layer structure of the low number of plies, the design that the area size that adopts in the design three changes, the stress that bears for dielectric layer between metal layers requires the highest, even adopt the formed dielectric layer of HDPCVD+PETEOS, still the metal plug group in the metal line layer must be dwindled at 20 * 20 microns, even within 10 * 10 microns, must be confined in the quite little area, just can avoid the generation in crack.
And in design four, demonstration is except the structure of the low number of plies is unaffected, when no matter other were HDPCVD+PETEOS or SACVD+PETEOS, as long as the distance between two metal line layers is widened to more than 3 microns, then dielectric layer between metal layers all can be avoided the generation in crack effectively.
Therefore, according to above-mentioned experimental result, inventor etc. provide a kind of method of testing dielectric layer between metal layers intensity, and are illustrated method flow referring to Fig. 6 a and Fig. 6 b according to the spirit of design three.
Fig. 6 a and 6b are depicted as according to a kind of method of testing dielectric layer between metal layers intensity in one embodiment of the invention, form first and second metal line layer 62A and the 62B of 50 microns of live widths in semiconductor substrate 60, wherein two metal line layers parallel to each other on.Then, on first and second metal line layer 62A and 62B, define first area 6A and second area 6B respectively, wherein first and second regional 6A and 6B are square, and its length of side promptly equals 50 microns of the live widths of metal wire, and first area and this second area 6A and 6B arrange with diagonal way.
Still, then on metal line layer 62A and 62B and matrix 60, deposit a dielectric material, to form smooth dielectric layer 60A referring to Fig. 6 a.And on the dielectric layer on first and second regional 6A and the 6B, form n * m first and second connector 61 respectively, form with first and second metal line layer 62A and 62B respectively and electrically connect, m and n are natural number and can be identical or differently, as form 9 * 9=81 metal plug.And first and second connector is arranged as the matrix of n * m respectively in equidistant mode by the summit at first and second regional 6A and 6B diagonal angle.
In a preferred embodiment of the present invention, can select three groups of areas such as I, II and III in first and second regional 6A and 6B referring to Fig. 6 b, wherein I is that 10 * 10 microns, II are 20 * 20 microns, III then is 50 * 50 microns, and is identical with first and second regional gross area.Select one of I, II, three groups of areas of III,, form metal plug group 61 so as in dielectric layer 60A.
Then, on dielectric layer 60A, form the 3rd metal line layer 64A and the 4th metal line layer 64B, wherein the 3rd and the 4th metal wire 64A and 64B are right against this first and second metal wire respectively, with in this first and second regional dielectric layer, form two groups of metal double-insert structures that [metal level 64A+ metal plug 61] and [metal level 64B+ metal plug 61] are formed respectively.
The above-mentioned first, second, third and the 4th metal line layer can adopt aluminum metal layer or copper metal layer.And above-mentioned metal plug can adopt copper metal, aluminum metal or tungsten metal.And dielectric layer can adopt the methylic Si oxide of low dielectric radio, but the present invention is not as limit.
Above-mentioned metal double-insert structure construction multilayer according to need to form multi-metal layer internal connection-wire structure, is a three-layer metal layer structure as person among Fig. 6 a.After this structure is finished, can be by in light microscope or two groups of metal double-insert structures of electron microscopy, whether dielectric layer between metal layers has the crack to produce.When the crack produces, represent that this intensity of dielectric layer is lower than standard, does not meet needs.
Because the method for the test dielectric layer between metal layers intensity of the invention described above can be selected different diagonal areas in first and second zone, with the metal plug group's of construction different distributions multi-metal layer internal connection-wire structure.And compare under same metal live width and same metal connector area the stress influence that dielectric layer between metal layers is suffered.Because diagonal structure is the most obvious to the stress of dielectric layer between metal layers, therefore, can obtain fast about the intensity data of dielectric layer at metal interlevel by the method for the invention described above.
And for fear of the crack of dielectric layer between metal layers, the present invention also proposes a kind of multi-metal layer internal connection-wire structure, and is illustrated with Fig. 7.Figure 7 shows that according to a kind of multi-metal layer internal connection-wire structure in one embodiment of the invention, have one at the semiconductor-based end 70 of circuit, deposit a dielectric layer 70A, and the first metal line layer 72A and the second metal line layer 72B, lay respectively in the substrate 70, be embedded among this dielectric layer 70A, wherein first metal line layer is parallel to this second metal line layer with one apart from d.And many first metal plug 71A are arranged at and are connected with this first metal line layer 72A among the dielectric layer 70A, constitute with circuit in this semiconductor-based end to electrically connect.And many second connector 71B are arranged at and are connected with the second metal line layer 72B in this dielectric layer 70, constitute with the circuit at this semiconductor-based end to electrically connect.And the 3rd metal line layer 74A and the 4th metal line layer 74B then are positioned at this first and second metal line layer top, and form the metal double-insert structure between first and second connector 71A and 71B.Wherein, the 3rd metal line layer 74A adjacent to one side 74B of the 4th metal line layer at a distance of this second metal line layer of below adjacent to one side of this first metal line layer distance greater than 1/2d, the d and the 4th metal line layer 74B still keeps at a distance is parallel to the 3rd metal line layer 74A.
In a preferred embodiment, above-mentioned alternating expression metal double-insert structure construction multilayer according to need is to form multi-metal layer internal connection-wire structure.And above-mentioned first second, third and the 4th metal line layer 72A, 72B, 74A and the 74B can adopt aluminum metal layer or copper metal layer.And above-mentioned metal plug 71A and 71B can adopt copper metal, aluminum metal or tungsten metal.And dielectric layer can adopt the methylic Si oxide of low dielectric radio, but the present invention is not as limit.
And above-mentioned multiple internal connecting lines structure, first and second metal plug 71A and 71B can be arranged in cornerwise square region of first and second metal line layer, and it is evenly distributed more to can be matrix form.
Alternating expression design according to metal interlevel of the present invention, its advantage is in two groups of metal double-insert structures, continuous dielectric layer between metal layers passage can not appear, as shown in Figure 7, dielectric layer between metal layers has been split into fragment, therefore eliminated the powerful stress that multiple layer metal produced, the dielectric layer between metal layers of effectively avoiding produces the crack.
And, another kind of multi-metal layer internal connection-wire structure proposed more among the present invention according to aforementioned four groups of experimental results that design, be illustrated referring to Fig. 8.In Fig. 8, have one at the semiconductor-based end 80 of circuit, deposit a dielectric layer 80A, and the first metal line layer 82A and the second metal line layer 82B, lay respectively in the substrate 80, be embedded among this dielectric layer 80A, wherein first metal line layer keeps the distance more than or equal to 3 microns to be parallel to this second metal line layer.And many first metal plug 81A are arranged at and are connected with this first metal line layer 82A among the dielectric layer 80A, constitute with circuit in this semiconductor-based end to electrically connect.And many second connector 81B are arranged at and are connected with the second metal line layer 82B in this dielectric layer 80, constitute with the circuit at this semiconductor-based end to electrically connect.And the 3rd metal line layer 84A and the 4th metal line layer 84B, then be positioned at directly over this first and second metal line layer, and form the metal double-insert structure between first and second connector 81A and 81B, and the parallel distance between the 3rd and the 4th metal line layer, identical with first and second metal wire interfloor distance.
In a preferred embodiment, above-mentioned alternating expression metal double-insert structure construction multilayer according to need is to form multi-metal layer internal connection-wire structure.And the above-mentioned first, second, third and the 4th metal line layer 82A, 82B, 84A and 84B can adopt aluminum metal layer or copper metal layer.And above-mentioned metal plug 81A and 81B can adopt copper metal, aluminum metal or tungsten metal.And dielectric layer can adopt the methylic Si oxide of low dielectric radio, but the present invention is not as limit.
Because experimental result according to aforementioned four groups of designs, find to need only two groups of interstructural distances of metal double-insert more than or equal to 3 microns, can effectively lower the stress of dielectric layer between metal layers, and the maintenance dielectric layer between metal layers is complete, therefore the multi-metal layer internal connection-wire structure that the invention described above proposed can effectively avoid the dielectric layer between metal layers structure to be subjected to the destruction of two metal line layers.
Though the present invention discloses as above by preferred embodiment; right its is not in order to limit the present invention; those of ordinary skill in the industry; without departing from the spirit and scope of the present invention; can make certain variation and retouching, so protection scope of the present invention should be as the criterion with the scope that claims were defined.
Claims (8)
1. a multi-metal layer internal connection-wire structure is arranged at one and has at the semiconductor-based end of circuit, it is characterized in that this structure comprises:
At least one dielectric layer was deposited on this semiconductor-based end;
One first metal line layer and one second metal line layer, be embedded in respectively in this dielectric layer, wherein this first metal line layer is parallel to this second metal line layer with one apart from d, and this first metal line layer and this second metal line layer electrically connect the circuit at this semiconductor-based end;
A plurality of first connectors are arranged in this dielectric layer and are connected with this first metal line layer, constitute with the circuit at this semiconductor-based end to electrically connect;
A plurality of second connectors are arranged in this dielectric layer and are connected with this second metal line layer, constitute with the circuit at this semiconductor-based end to electrically connect; And
One the 3rd metal line layer and one the 4th metal line layer, be positioned at this first and second metal line layer top, form the metal double-insert structure respectively and between described first and second connector, wherein, the 3rd metal line layer adjacent to one side of the 4th metal line layer at a distance of this second metal line layer of below adjacent to one side of this first metal line layer distance greater than 1/2d, and the 4th metal line layer with this apart from d, be parallel to the 3rd metal line layer;
Wherein the 3rd metal line layer and second metal line layer some intermesh overlapping.
2. multi-metal layer internal connection-wire structure as claimed in claim 1 is characterized in that, also is included on the 3rd and the 4th metal line layer, repeats to form at least one this metal double-insert structure again.
3. multi-metal layer internal connection-wire structure as claimed in claim 1 is characterized in that the first, second, third and the 4th metal line layer in the described metal double-insert structure is aluminum metal layer or copper metal layer.
4. multi-metal layer internal connection-wire structure as claimed in claim 1 is characterized in that first and second connector in the described metal double-insert structure is copper metal, aluminum metal or tungsten metal.
5. multi-metal layer internal connection-wire structure as claimed in claim 1, it is characterized in that also comprising respectively on described first and second metal line layer a first area and a second area, wherein this first and second zone is a rectangle, and a length of side of rectangle equals the live width of this metal wire, and this first area and this second area are arranged with diagonal way, and described first and second connector is for being arranged in respectively in this first and second zone.
6. multi-metal layer internal connection-wire structure as claimed in claim 5 is characterized in that described first and second connector respectively with equidistant matrix-style, is covered with this first and second zone.
7. multi-metal layer internal connection-wire structure as claimed in claim 1, it is characterized in that described apart from d more than or equal to 3 microns.
8. multi-metal layer internal connection-wire structure as claimed in claim 1 is characterized in that the methylic Si oxide of described dielectric layer for low dielectric radio.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB021074259A CN1176488C (en) | 2002-03-15 | 2002-03-15 | Connecting lines structure in multiple metal layers and method for testing intensity of dielectric layer between metal layers |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB021074259A Division CN1176488C (en) | 2002-03-15 | 2002-03-15 | Connecting lines structure in multiple metal layers and method for testing intensity of dielectric layer between metal layers |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1571152A CN1571152A (en) | 2005-01-26 |
| CN1314115C true CN1314115C (en) | 2007-05-02 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB021074259A Expired - Lifetime CN1176488C (en) | 2002-03-15 | 2002-03-15 | Connecting lines structure in multiple metal layers and method for testing intensity of dielectric layer between metal layers |
| CNB2004100462882A Expired - Lifetime CN1314115C (en) | 2002-03-15 | 2002-03-15 | Multiple metallic layers inner connecting wire structure |
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| CNB021074259A Expired - Lifetime CN1176488C (en) | 2002-03-15 | 2002-03-15 | Connecting lines structure in multiple metal layers and method for testing intensity of dielectric layer between metal layers |
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Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7155686B2 (en) * | 2004-03-09 | 2006-12-26 | Taiwan Semiconductor Manufacturing Co., Ltd. | Placement and routing method to reduce Joule heating |
| US8946890B2 (en) * | 2010-10-20 | 2015-02-03 | Marvell World Trade Ltd. | Power/ground layout for chips |
| CN103187400B (en) * | 2011-12-31 | 2016-02-17 | 中芯国际集成电路制造(上海)有限公司 | Silicon through hole detection architecture and detection method |
| CN110544683B (en) * | 2018-05-29 | 2021-03-19 | 澜起科技股份有限公司 | Laminated structure for detecting defects of intermetallic dielectric layer and test method |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5187119A (en) * | 1991-02-11 | 1993-02-16 | The Boeing Company | Multichip module and integrated circuit substrates having planarized patterned surfaces |
| US5399533A (en) * | 1993-12-01 | 1995-03-21 | Vlsi Technology, Inc. | Method improving integrated circuit planarization during etchback |
| EP0825645A1 (en) * | 1996-08-08 | 1998-02-25 | Siemens Aktiengesellschaft | Gapfill and planarization process for shallow trench isolation |
-
2002
- 2002-03-15 CN CNB021074259A patent/CN1176488C/en not_active Expired - Lifetime
- 2002-03-15 CN CNB2004100462882A patent/CN1314115C/en not_active Expired - Lifetime
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5187119A (en) * | 1991-02-11 | 1993-02-16 | The Boeing Company | Multichip module and integrated circuit substrates having planarized patterned surfaces |
| US5399533A (en) * | 1993-12-01 | 1995-03-21 | Vlsi Technology, Inc. | Method improving integrated circuit planarization during etchback |
| EP0825645A1 (en) * | 1996-08-08 | 1998-02-25 | Siemens Aktiengesellschaft | Gapfill and planarization process for shallow trench isolation |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1571152A (en) | 2005-01-26 |
| CN1176488C (en) | 2004-11-17 |
| CN1445832A (en) | 2003-10-01 |
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