CN1311355C - Spare circuit for raising system performance - Google Patents
Spare circuit for raising system performance Download PDFInfo
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- CN1311355C CN1311355C CNB2004100363158A CN200410036315A CN1311355C CN 1311355 C CN1311355 C CN 1311355C CN B2004100363158 A CNB2004100363158 A CN B2004100363158A CN 200410036315 A CN200410036315 A CN 200410036315A CN 1311355 C CN1311355 C CN 1311355C
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Abstract
The present invention discloses a spare circuit for raising system performance, which is mainly composed of a control circuit, a selection circuit and a spare circuit, wherein the control circuit can receive command signals sent out by a CPU and can also control the selection circuit according to the connection states of hardware facilities, such as jump devices, selection switches, etc.; the selection circuit outputs register chip selecting signals under the combined action of the control circuit and the CPU and selects different spare registers in the spare circuit. The circuit has the advantages of simple structure, software and hardware selection control ways, high system reliability and stability due to the addition of the backup circuit and the selection circuit; short system maintenance time and high system work efficiency, and can be widely suitable for the existing large-scale control systems.
Description
Technical field
The present invention relates to a kind of fallback circuit, specifically, relate to a kind ofly can realize the control circuit freely selected different spare units.
Background technology
In recent years, raising along with development of electronic technology and chip fabrication technique level, present electronic system becomes increasingly complex, function from strength to strength, but the parts that use are fewer and feweri, and the integrated function of single chip gets more and more the also corresponding increase of the data of storage, therefore, the damage of a chip may cause the paralysis of total system.For the work reliably and with long-term of assurance system, when system design to critical component, back up design as system start-up program storage, data backup device etc., perhaps to the critical data separate storage, in case when a number formulary according to or device when being damaged, the opposing party's data or device can be remedied, thereby effectively guarantee the reliability and stability of system works, and the use of such a backup design in large scale system can get more and more.
Summary of the invention
In order to improve the control performance of existing system, guarantee the reliability and stability of its work, the invention provides a kind of novel fallback circuit, this circuit structure is simple, can realize selection to different spare units in the fallback circuit by hardware setting and software setting.
For solving the problems of the technologies described above, the present invention is achieved by the following technical programs:
A kind of fallback circuit that improves system performance comprises control circuit and fallback circuit, includes two back-up registers in the described fallback circuit at least, is connected with one and selects circuit between described control circuit and fallback circuit; Wherein, include a line control machine in described control circuit, the input end of described line control machine receives CPU and sends control signal or receive high/low level signal by hardware configuration, and output terminal links to each other with the gating control end of described selection circuit; In described selection circuit, include gate circuit, the input end of described gate circuit links to each other with the chip selection signal end of CPU, the gating control end connects the output terminal of described line control machine, under the acting in conjunction of control circuit and CPU, export corresponding back-up registers chip selection signal, select back-up registers different in the described fallback circuit.
As a preferred embodiment of the present invention, in described control circuit, include a line control machine, 1 pin of described line control machine links to each other with the control signal end of direct supply and CPU respectively, 2 pin one tunnel directly connect described selection circuit, another Lu Jingyi phase inverter links to each other 3 pin ground connection with selecting circuit.
As another preferred embodiment of the present invention, described selection circuit includes at least two NAND gate circuit, the gating end of one of them Sheffer stroke gate links to each other with the output terminal of described phase inverter, the gating end of another Sheffer stroke gate directly links to each other with 2 pin of line control machine, and the input end of described Sheffer stroke gate links to each other with the different chip selection signal ends of CPU.
As further qualification to above-mentioned preferred embodiment, described selection circuit includes three NAND gate circuit, wherein, the gating end of first Sheffer stroke gate links to each other with the output terminal of described phase inverter, the gating end of two other Sheffer stroke gate directly links to each other with 2 pin of line control machine, the input end of described first, second Sheffer stroke gate links to each other with the chip selection signal end of CPU, the input end of the 3rd Sheffer stroke gate links to each other with another chip selection signal end of CPU, and the output terminal of described Sheffer stroke gate links to each other with the sheet choosing end of three register die in the fallback circuit respectively.
Described selection circuit can adopt one four tunnel Sheffer stroke gate chip to realize; Described line control machine can adopt a jumper wire device or selector switch to realize.
Compared with prior art, advantage of the present invention and good effect are: the present invention is made up of control circuit, selection circuit and fallback circuit three parts.Wherein, control circuit both can receive the command signal that CPU sends, and can realize according to the connection status of hardware facilities such as jumper wire device or selector switch again selecting the control of circuit; Described selection circuit output register chip selection signal under the acting in conjunction of control circuit and CPU is realized the selection to different back-up registers in the fallback circuit.This circuit structure is simple, have software and hardware and select control mode for two kinds, and by increasing fallback circuit and selecting circuit effectively to strengthen system reliability and stability, shortened the maintenance time of system, the work efficiency of system is improved, can be widely used in the present extensive control system.
Description of drawings
Fig. 1 is the system chart of fallback circuit of the present invention;
Fig. 2 is the concrete circuit connection diagram of control circuit among the present invention;
Fig. 3 is a concrete circuit connection diagram of selecting circuit among the present invention;
Fig. 4 is the concrete circuit connection diagram of fallback circuit among the present invention.
Embodiment
The present invention will be further described in detail below in conjunction with the drawings and specific embodiments.
Fig. 1 is the system chart of fallback circuit of the present invention, and it is made up of control circuit, selection circuit and fallback circuit three parts.Wherein, control circuit both can receive the command signal that CPU sends, and can realize according to the connection status of hardware facilities such as jumper wire device or selector switch again selecting the control of circuit; The high-low level signal that described selection circuit reception control circuit sends, and under the acting in conjunction of CPU, send corresponding chip selection signal, realize selection to different registers in the fallback circuit.The major function of described fallback circuit is to finish the backup of system's middle part sub-unit and data, it has various ways, such as the backup (data that a plurality of memory chip stores are identical) of storage chip and the backup (identical data storage is in different spaces) of data etc., the increase of fallback circuit mainly is in order to improve the reliability and stability of total system work.Fallback circuit of the present invention adopts three register die, respectively the start-up routine and the application program of storage system.Wherein, the selection of start-up routine is needed hardware controls, the selection of application programs needs software control, and its physical circuit connects referring to Fig. 2 to shown in Figure 4.
Fig. 2 is a control circuit unit of the present invention, it includes a jumper wire device JMB01 and a phase inverter NB25,1 pin of described jumper wire device on the one hand with+3.3V direct supply, receive the control signal GPIO_SEL_SERIAL that CPU sends on the other hand, 2 pin are directly exported the Boot_Nand signal on the one hand, after phase inverter NB25 is anti-phase, export Boot_Serial signal, 3 pin ground connection on the other hand.When adopting jumper wire device JMB01 control, if 1 pin of jumper wire device JMB01 and 2 pin are communicated with, then Boot_Nand exports high level signal, Boot_Serial output low level signal; If 2 pin of jumper wire device JMB01 and 3 pin are communicated with, Boot_Nand output low level signal then, Boot_Serial exports high level signal.When adopting software control, with 1 pin and the connection of 2 pin of jumper wire device JMB01, at this moment, if GPIO_SEL_SERIAL is set to high level, then Boot_Nand exports high level signal, Boot_Serial output low level signal; If GPIO_SEL_SERIAL is set to low level, Boot_Nand output low level signal then, Boot_Serial exports high level signal.This control circuit unit has realized for different control signals different level output being arranged.
Fig. 3 is a selection circuit unit of the present invention, and it includes three NAND gate circuit NB26A, NB26B and NB26C.Wherein, the Boot_Serial signal that the gating end 1 pin reception control circuit of Sheffer stroke gate NB26A sends, input end 2 pin receive the chip selection signal FLEX_CSO# that CPU sends; Gating end 4 pin of Sheffer stroke gate NB26B and NB26C and 10 pin are the Boot_Nand signal that sends of reception control circuit respectively, and input end 5 pin and 9 pin receive chip selection signal FLEX_CSO# or the FLEX_CSl# that CPU sends respectively; Their output terminal respectively with fallback circuit in the sheet choosing end of three different registers link to each other.
Fig. 4 is fallback circuit of the present invention unit, and it is made up of three back-up registers NB30, NB31 and NB32.Wherein, start-up routine is stored among register NB30, NB31, the NB32, in case when a register die is damaged, can guarantee that still system normally moves; Application storage can realize the backup of same application domain or the selection of different application in register NB31, NB32.The sheet choosing end S of register NB30 links to each other with output terminal 3 pin of Sheffer stroke gate NB26A, the sheet choosing end CE of register NB31 links to each other with output terminal 8 pin of Sheffer stroke gate NB26C, the sheet choosing end CE of register NB32 links to each other with output terminal 6 pin of Sheffer stroke gate NB26B, and it is effective that its chip selection signal is low level.
When system is selected when register NB30 starts, jumper wire device JMB01 need be communicated with 1,2 pin, and the control signal GPIO_SEL_SERIAL that CPU sends is a high level, and chip selection signal FLEX_CSO# is a low level, at this moment, the Boot_Serial signal of control circuit output is a low level, the Boot_Nand signal is a high level, and then control Sheffer stroke gate NB26A gating, and NB26B, NB26C end, output low level ROMCS# signal is realized the selection to register NB30.If when selecting from register NB31 or NB32 startup, jumper wire device JMB01 need be communicated with 2,3 pin, at this moment, the Boot_Serial signal of control circuit output is a high level, the Boot_Nand signal is a low level, and control Sheffer stroke gate NB26A ends NB26B, NB26C gating; At this moment, the chip selection signal FLEX_CSO# that sends of CPU and the high-low level state of FLEX_CS1# will determine selected register NB31 or NB32.For the uniqueness that guarantees that chip is selected, chip selection signal FLEX_CSO# and FLEX_CS1# can not be low level simultaneously, when FLEX_CSO# is a low level, when FLEX_CS1# is high level, Sheffer stroke gate NB26B output low level, NB26C exports high level, and then realizes the selection to register NB32; When FLEX_CSO# is a high level, when FLEX_CS1# is low level, Sheffer stroke gate NB26C output low level, NB26B exports high level, thereby realizes the selection to register NB31.
In the present invention, select circuit to realize by one four tunnel Sheffer stroke gate chip; Jumper wire device JMB01 can be substituted by a selector switch, and described jumper wire device or selector switch are positioned on the shell or control panel of system, is convenient to user's operation.
Circuit structure of the present invention is simple, can realize the expansion to selection circuit output end and register die number easily, and then realizes the selection to a plurality of registers.Certainly; above-mentioned explanation is not to be limitation of the present invention; the present invention also is not limited in above-mentioned giving an example, and variation, remodeling, interpolation or replacement that those skilled in the art are made in essential scope of the present invention also should belong to protection scope of the present invention.
Claims (8)
1. a fallback circuit that improves system performance comprises control circuit and fallback circuit, includes two back-up registers in the described fallback circuit at least, it is characterized in that: between described control circuit and fallback circuit, be connected with one and select circuit, wherein,
Include a line control machine in described control circuit, the input end of described line control machine receives CPU and sends control signal or receive high/low level signal by hardware configuration, and output terminal links to each other with the gating control end of described selection circuit;
In described selection circuit, include gate circuit, the input end of described gate circuit links to each other with the chip selection signal end of CPU, the gating control end connects the output terminal of described line control machine, under the acting in conjunction of control circuit and CPU, export corresponding back-up registers chip selection signal, select back-up registers different in the described fallback circuit.
2. the fallback circuit of raising system performance according to claim 1, it is characterized in that: 1 pin of described line control machine links to each other with the control signal end of direct supply and CPU respectively, 2 pin one tunnel directly connect described selection circuit, and another Lu Jingyi phase inverter links to each other 3 pin ground connection with selecting circuit.
3. the fallback circuit of raising system performance according to claim 2, it is characterized in that: described selection circuit includes at least two NAND gate circuit, the gating end of one of them Sheffer stroke gate links to each other with the output terminal of described phase inverter, the gating end of another Sheffer stroke gate directly links to each other with 2 pin of line control machine, and the input end of described Sheffer stroke gate links to each other with the different chip selection signal end of CPU.
4. the fallback circuit of raising system performance according to claim 3, it is characterized in that: described selection circuit includes three NAND gate circuit, wherein, the gating end of first Sheffer stroke gate links to each other with the output terminal of described phase inverter, the gating end of two other Sheffer stroke gate directly links to each other with 2 pin of line control machine, the input end of described first, second Sheffer stroke gate links to each other with the chip selection signal end of CPU, and the input end of the 3rd Sheffer stroke gate links to each other with another chip selection signal end of CPU.
5. the fallback circuit of raising system performance according to claim 4 is characterized in that: described selection circuit adopts one four tunnel Sheffer stroke gate chip to realize.
6. according to the fallback circuit of claim 4 or 5 described raising system performances, it is characterized in that: described fallback circuit includes three register die, and its sheet choosing end links to each other with the output terminal of three NAND gate circuit in the described selection circuit respectively.
7. according to the fallback circuit of claim 2 or 3 or 4 described raising system performances, it is characterized in that: described line control machine is a jumper wire device.
8. according to the fallback circuit of claim 2 or 3 or 4 described raising system performances, it is characterized in that: described line control machine is a selector switch.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100363158A CN1311355C (en) | 2004-11-17 | 2004-11-17 | Spare circuit for raising system performance |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100363158A CN1311355C (en) | 2004-11-17 | 2004-11-17 | Spare circuit for raising system performance |
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| CN1609815A CN1609815A (en) | 2005-04-27 |
| CN1311355C true CN1311355C (en) | 2007-04-18 |
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| Application Number | Title | Priority Date | Filing Date |
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| CNB2004100363158A Active CN1311355C (en) | 2004-11-17 | 2004-11-17 | Spare circuit for raising system performance |
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| CN108280340A (en) * | 2018-01-18 | 2018-07-13 | 郑州云海信息技术有限公司 | A kind of system password sweep-out method, system, equipment and readable storage medium storing program for executing |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1227387A (en) * | 1998-02-25 | 1999-09-01 | 三菱电机株式会社 | Memory capacity switching method and semiconductor device to which the same applies |
| CN2530291Y (en) * | 2001-10-29 | 2003-01-08 | 王钧 | Computer memory reversing device |
| CN2593255Y (en) * | 2002-05-16 | 2003-12-17 | 刘宏 | Computer switching power source with dual harddisk drive switching device |
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- 2004-11-17 CN CNB2004100363158A patent/CN1311355C/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1227387A (en) * | 1998-02-25 | 1999-09-01 | 三菱电机株式会社 | Memory capacity switching method and semiconductor device to which the same applies |
| CN2530291Y (en) * | 2001-10-29 | 2003-01-08 | 王钧 | Computer memory reversing device |
| CN2593255Y (en) * | 2002-05-16 | 2003-12-17 | 刘宏 | Computer switching power source with dual harddisk drive switching device |
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| CN1609815A (en) | 2005-04-27 |
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Address after: 266071 Shandong city of Qingdao province Jiangxi City Road No. 11 Co-patentee after: Hisense Visual Technology Co., Ltd. Patentee after: HISENSE Co.,Ltd. Address before: 266071 Shandong city of Qingdao province Jiangxi City Road No. 11 Co-patentee before: QINGDAO HISENSE ELECTRONICS Co.,Ltd. Patentee before: HISENSE Co.,Ltd. |
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