CN1309044C - BiMOS digital-analog mixed integrated circuit with DP sink and producing method thereof - Google Patents
BiMOS digital-analog mixed integrated circuit with DP sink and producing method thereof Download PDFInfo
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- CN1309044C CN1309044C CNB031169937A CN03116993A CN1309044C CN 1309044 C CN1309044 C CN 1309044C CN B031169937 A CNB031169937 A CN B031169937A CN 03116993 A CN03116993 A CN 03116993A CN 1309044 C CN1309044 C CN 1309044C
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Abstract
The present invention relates to a producing method of a BiMOS digital-analog hybrid integrated circuit with a DP trap. After the CMOS process is used for making an N well and a P well on a P type substrate, a photomask is used for defining a region of the DP well in the P well, the region of non-DP well is covered with photoresist, ions are implanted into the region of the DP well to make the DP well, and the sebsequent steps are basically the same as the double-level-polysilicon double-level-metal CMOS manufacturing process. The BiMOS digital-analog hybrid integrated circuit with a DP well, which is manufactured by the manufacturing method, comprises a structure of a CMOS integrated circuit, the DP well formed in the N well by diffusion, a base electrode for forming an NMOS tube and an NPN type bipolar tube. With the technical scheme, a CMOS device and a bipolar device are combined on a chip, only a few steps and cost are added simultaneously, and the purpose of obtaining high performance with least cost is achieved.
Description
Technical field
The present invention relates to BiMOS (the ambipolar metal-oxide semiconductor (MOS) of composite type) number and touch hybrid integrated circuit manufacturing field, relate to the BiMOS hybrid digital-analog integrated circuit and the manufacture method thereof of a kind of DP of having (dark P type) trap by it.
Background technology
What mainly use in the integrated circuit at present is CMOS (complementary metal oxide semiconductors (CMOS)) device and bipolar device, these two kinds of devices have advantage and limitation separately, cmos device has the advantage that device power consumption is low, integrated level is high and antijamming capability is strong, and the device operating rate is low, the shortcoming of driving force difference but also have.The advantage that the bipolar device device speed is fast, driving force is strong, simulation precision is high, but the device power consumption height is also arranged, the shortcoming that integrated level is low.From the above mentioned, the pluses and minuses that can see CMOS and bipolar device are just in time complementary, so, a kind of CMOS and ambipolar two kinds of semiconductor device be produced on simultaneously on the same chip technology---BiCMOS (the ambipolar metal-oxide semiconductor (MOS) of composite type) is development therefore, to satisfy the demand for development of industry toward high speed, high integration, high performance large scale integrated circuit (LSI) and very lagre scale integrated circuit (VLSIC) (VLSI).
The basic demand of BiCMOS technology is with needing " at a high speed " and " current drives " part in the entire circuit, to handle with ambipolar with two kinds of combination of devices to same chip, as the I/O part (I/O) of circuit; And with " high integrated " " low-power consumption " zone in the circuit, as array, make with CMOS, the chip that obtains thus has good comprehensive performances, but making BiCMOS needs to add bipolar device in the circuit that original CMOS is a design agents, existing BiCMOS technology will be than simple CMOS complex process, and cost also can improve.
Summary of the invention
The BiMOS hybrid digital-analog integrated circuit and the manufacture method thereof that the purpose of this invention is to provide a kind of DP of having trap; increasing the DP trap on CMOS technology basis is integrated into CMOS and bipolar devices in the same technology; make required resistance, electric capacity, diode, high-low pressure PMOS (P-type mos)/NMOS (N type metal oxide semiconductor), isolate devices such as NMOS (isolating the N type metal oxide semiconductor) and NPN, develop and improve the manufacturing process of the double level polysilicon double-level-metal BiCMOS hybrid digital-analog integrated circuit of live width 1.2um.
In order to achieve the above object, the present invention adopts following technical scheme:
According to an aspect of the present invention, provide a kind of manufacture method of BiMOS hybrid digital-analog integrated circuit of the DP of having trap, may further comprise the steps:
A. on P type substrate, make N trap and P trap with CMOS technology;
B. use mask in the N trap, to define the zone of DP trap, the zone of non-DP trap is made with photoresist cover, carry out ion in the zone of DP trap and inject and make the DP trap;
C. in N trap, P trap or DP trap, be manufactured with the source region with CMOS technology;
D. lay polysilicon, comprise two-layer polysilicon, the polysilicon of ground floor is as the grid of metal-oxide-semiconductor and the bottom electrode of polysilicon resistance and polysilicon capacitance, and the polysilicon of the second layer is as the top electrode of polysilicon resistance and polysilicon capacitance;
E. in N trap, P trap or DP trap, inject N type ion, make double-diffused drain electrode (DDD) structure, form the emitter and collector of source electrode, drain electrode and the bipolar npn type pipe of NMOS pipe;
F. in N trap or DP trap, inject P type ion, form the base stage of source electrode, drain electrode and the described bipolar npn type pipe of PMOS pipe; Lay boron-phosphorosilicate glass with CMOS technology, and the contact hole that links to each other with device and metal level of making;
G. lay the first metal layer, dielectric layer, in dielectric layer, make to connect the through hole of the first metal layer, lay second metal level on dielectric layer and connect described through hole;
H. lay passivation layer with CMOS technology, carry out alloying afterwards and carry out on-line parameter (PCM) test, next encapsulation, making finishes.
The ion that described step b injects when making the DP trap is boron (B11+) ion, and concentration is 2.5E13cm
-2, energy is 150keV, the DP trap diffuses to form in the N trap.
Described step e injects N type ion, makes in the DDD structure, and the ion that dense N type ion double-diffused drain electrode (N+DDD) layer injects is phosphorus (P31+) ion, and concentration is 3E13cm
-2, energy is 40keV, and the ion that the N+ layer injects is arsenic (As75+) ion, and concentration is 1.7E17cm
-2, energy is 150keV.
According to a further aspect in the invention, provide a kind of BiMOS hybrid digital-analog integrated circuit of the DP of having trap, comprise the structure of CMOS integrated circuit,
The BiMOS hybrid digital-analog integrated circuit of the described DP of having trap comprises the DP trap that is arranged in the N trap, can form the base stage of NMOS pipe and bipolar npn type pipe;
The BiMOS hybrid digital-analog integrated circuit of the described DP of having trap also comprises the DDD structure, and described DDD structure is to be arranged in N trap, P trap or described DP trap, can form the emitter and collector of source electrode, drain electrode and the described NPN type Bipolar pipe of NMOS pipe;
The BiMOS hybrid digital-analog integrated circuit of the described DP of having trap comprises two metal layers.
Described DP trap is to be 2.5E13cm by concentration
-2, energy is that boron (B11+) ion of 150keV diffuses to form in the N trap.
The N+DDD layer of described DDD structure is to be 3E13cm by concentration
-2, energy is that phosphorus (P31+) ion of 40keV diffuses to form in N trap, P trap or described DP trap; The N+ layer of described DDD structure is to be 1.7E17cm by concentration
-2, energy is that arsenic (As75+) ion of 150keV diffuses to form in N trap, P trap or described DP trap.
Owing to adopted technique scheme; the method of the manufacture method of a kind of BiMOS hybrid digital-analog integrated circuit that the DP trap arranged of the present invention by increasing the DP trap well on chip piece in conjunction with cmos device and bipolar device; compare with traditional CMOS technology simultaneously; only increased few steps; the increase of cost has also seldom reached the purpose of obtaining high performance BiCMOS chip with as far as possible little cost.
Description of drawings
Figure 1A carries out the flow chart of step a with making N trap and P trap in one embodiment of the present of invention;
Figure 1B carries out the schematic diagram of step a with making N trap and P trap in one embodiment of the present of invention;
Fig. 2 carries out flow chart and the schematic diagram that step b makes the DP trap in one embodiment of the present of invention;
Fig. 3 A carries out step c among the embodiment who invents to be manufactured with the source region flow chart;
Fig. 3 B carries out step c among the embodiment who invents to be manufactured with the source region schematic diagram;
Fig. 4 A carries out the flow chart that steps d is laid two-layer polysilicon among the embodiment who invents;
Fig. 4 B carries out the schematic diagram that steps d is laid two-layer polysilicon among the embodiment who invents;
Fig. 5 A carries out the flow chart that step e makes the DDD structure among the embodiment who invents;
Fig. 5 B is the structure chart of DDD;
Fig. 5 C carries out the schematic diagram that step e makes the DDD structure among the embodiment who invents;
Fig. 6 A carries out step f to inject P type ion, lay BPSG (boron-phosphorosilicate glass) and make the flow chart of device in the continuous contact hole of metal level among the embodiment who invents;
Fig. 6 B carries out step f to inject P type ion, lay BPSG and make the schematic diagram of device in the continuous contact hole of metal level among the embodiment who invents;
Fig. 7 A carries out step g to lay the first metal layer, dielectric layer among the embodiment who invents, through hole that the making two metal layers links to each other and the flow chart of laying second metal level;
Fig. 7 B carries out step g to lay the first metal layer, dielectric layer among the embodiment who invents, through hole that the making two metal layers links to each other and the schematic diagram of laying second metal level;
Fig. 8 A is the flow chart that carries out step h laying passivation layer, carries out alloying, carries out PCM test, encapsulation among the embodiment of invention.
Fig. 8 B lays the schematic diagram after the passivation layer.
Embodiment
Further specify technical scheme of the present invention below in conjunction with embodiment and accompanying drawing.
One embodiment of the present of invention, preparation forms following device on a P type substrate, shown in the schematic diagram of Figure 1B, be followed successively by from left to right: an ambipolar NPN triode, NMOS FET pipe (N type metal oxide semiconductor field-effect transistor), HV-NMOS FET pipe (high-pressure N-type metal oxide semiconductor field effect transistor), an Iso-NMOS FET (isolating N type metal oxide semiconductor field-effect transistor) pipe, a PMOS FET (P-type mos field-effect transistor) pipe and a polysilicon capacitance (Capacitor).
According to the step of manufacturing that the BiMOS hybrid digital-analog integrated circuit of DP trap is arranged of the present invention; at first carry out step a and make N trap and P trap with CMOS technology on P type substrate, Figure 1A and Figure 1B carry out flow chart and the schematic diagram of step a with making N trap and P trap among this embodiment.Shown in Figure 1A, the step of making P trap and N trap comprises:
A1. carry out oxygen just, promptly on P type substrate, form layer of oxide layer (silicon dioxide SiO
2), i.e. oxide layer among Figure 1B 11 (being called oxide layer Oxide among the figure);
The a2.LPCVD silicon nitride is promptly at surface coverage one deck silicon nitride (Si of above-mentioned oxide layer 11
3N
4), because this layer silicon nitride only is temporary transient existence, so among Figure 1B and for this layer is showed;
The photoetching of a3.N trap, the photoetching method of CMOS technology is adopted in the photoetching of N trap, at first defines the zone of N trap, then the silicon nitride and the oxide layer 11 of N well area is removed;
The a4.N trap injects;
A5. autoregistration oxidation, the N well area carries out oxidation;
A6. silicon nitride etch is all removed the silicon nitride of remainder;
The a7.P trap injects;
A8. deoxidation layer;
The a9.P trap advances.
Above-mentioned steps is all basic identical with the step of existing CMOS technology, just has been not described in detail these steps here, after above-mentioned steps is finished promptly shown in Figure 1B: made N trap and P trap on P type substrate, there is oxide layer 11 on the upper strata.
Step b makes the DP trap, and this is characteristics of the present invention places.The DP trap diffuses to form in the N trap, and in the present embodiment, the ion that injects when making the DP trap is boron (B11+) ion, and its concentration is 2.5E13cm
-2, energy is 150keV.As shown in Figure 2, in the present embodiment, use above-mentioned concentration, above-mentioned energy boron (B11+) ion, in the N trap, diffuseed to form two DP traps 21.After having made the DP trap, also need to form one deck and comprise silica (SiO on the surface
2) and silicon nitride (Si
3N
4) LOCOS (silicon selective oxidation) field isolating layer 22.
Step c is manufactured with the source region, may further comprise the steps, as shown in Figure 3A:
C1. basic oxygen promptly carries out oxidation to all surface;
C2. low-pressure chemical vapor deposition (LPCVD) silicon nitride is laid silicon nitride, is used as coverlay and uses;
C3. active area photoetching defines and removes the silicon nitride of active area to active area;
C4. the place is injected, and injects highly doped ion below selected field oxide region;
C5. an oxidation is carried out oxidation to selected field oxide region, forms very thick oxide layer (SiO
2);
C6. the denitrification silicon/oxidative silicon is removed residual silicon nitride/silica.
The above-mentioned steps all CMOS technology with existing is identical, just has been not described in detail here.
Shown in Fig. 3 B, the gray area among the figure is a field oxide region 31, is called field oxide (FieldOxide) among the figure, forms very thick silica (SiO here
2), as the isolation between the different components.Residual silicon nitride/silica is 32, is called thin oxide layer (Sacrificial Oxide) among the figure.
Steps d shown in Fig. 4 A, may further comprise the steps:
D1. pre-grid oxygen carries out oxidation to the surface;
D2.N buried regions (BN) photoetching, (Buried N BN) carries out the photoetching location to the N buried regions;
D3.BN injects, and the ion that carries out the N buried regions injects;
D4. a grid oxygen carries out once oxidation to the surface, and the oxide layer of formation is thinner, is used for the zone of low-voltage device, and the required oxide layer of low-voltage device is thinner;
D5. grid oxygen photoetching;
D6. secondary grid oxygen carries out once oxidation again to the surface, and the oxide layer of formation is thicker, is used for the zone of high tension apparatus, and the required oxide layer of high tension apparatus is thicker;
D7.Vt regulates injection, regulates for the ion concentration of each diffusion region, to adjust the cut-in voltage (V of each device
Threshold);
D8. ground floor polysilicon deposition, the ground floor polysilicon is as the grid of metal-oxide-semiconductor and the bottom electrode of polysilicon resistance and polysilicon capacitance;
D9. ground floor polysilicon ion injects, and is mainly used in the adjustment resistance;
D10. ground floor polysilicon photoetching;
The d11.CAP oxidation promptly covers one deck dielectric layer on the ground floor polysilicon, be used in the zone of polysilicon resistance and polysilicon capacitance device correspondence;
D12. second layer polysilicon deposition, the polysilicon of the second layer is as the top electrode of polysilicon resistance and polysilicon capacitance;
D13. second layer polysilicon ion injects, and regulates resistance;
D14. second layer polysilicon photoetching.
Above-mentioned steps and existing CMOS technology are basic identical, just are not described in detail here.
The schematic diagram of the laying two-layer polysilicon that Fig. 4 B is, shown in Fig. 4 B, 41 is the ground floor polysilicon, and for the pipe of the NMOS FET shown in the figure, HV-NMOS FET pipe, Iso-NMOS FET pipe and PMOSFET pipe, the ground floor polysilicon is as the grid of these metal-oxide-semiconductors.For polysilicon capacitance (Capacitor), ground floor polysilicon 41 is as its bottom electrode, and ground floor polysilicon 41 is called Poly1 among the figure; Polysilicon capacitance as shown in Figure 4 except its bottom electrode is ground floor polysilicon 41, is coated with dielectric layer 42 on ground floor polysilicon 41, be called silicate oxide layer (TEOS-Oxide) among the figure, its very second layer polysilicon 43 that powers on, be called among the figure (polysilicon layer 2, Poly2).
Step e shown in Fig. 5 A, may further comprise the steps:
E1. silicate (TEOS) deposits, in the two side areas metallization medium layer of polysilicon;
E2. supporting walls (Spacer) etching after the dielectric layer etching that deposits among the step e1, because the thickness of polysilicon is understood the two item metallization medium layer that form arcs of nature at polysilicon, is called supporting walls (Spacer);
The e3.N+DDD layer photoetching;
E4.N+DDD leafing injects, and in the present embodiment, what the N+DDD layer injected is that concentration is 3E13cm
-2, energy is phosphorus (P31+) ion of 40keV, the N+DDD layer can diffuse to form in N trap, P trap or DP trap;
The annealing of e5.N+DDD layer;
E6. dense N type (N+) layer photoetching;
E7. dense N type (N+) leafing injects, and in the present embodiment, what dense N type (N+) layer injected is that concentration is 1.7E17cm
-2, energy is arsenic (As75+) ion of 150keV, dense N type (N+) layer can diffuse to form in N trap, P trap or described DP trap;
E8. the annealing of dense N type (N+) layer.
Above-mentioned steps and existing CMOS technology are basic identical, so just be not described in detail here.
Fig. 5 B is the structure chart of DDD, and among Fig. 5 B, 51 is Spacer, and 52 is the N+DDD layer, and 53 is dense N type (N+) layer.
Fig. 5 C carries out the schematic diagram that step e makes the DDD structure among the embodiment who invents, 51 is supporting walls (Spacer) among the figure, as seen, in each ground floor polysilicon both sides as the metal-oxide-semiconductor grid supporting walls (Spacer) is arranged all.From Fig. 5 C, be also shown in, above-mentioned DDD structure can be used as the emitter and collector of source electrode, drain electrode and the ambipolar pipe of NMOS pipe, 54 is the DDD that diffuses to form in the DP trap among the figure, as the emitter of Bipolar NPN pipe, 55 is the DDD that diffuses to form in the N trap, as the collector electrode of ambipolar NPN pipe, the 56th, the DDD that in the P trap, diffuses to form, as the source electrode of NMOS FET pipe, the 57th, the DDD that diffuses to form in the N trap is as the drain electrode of HV-NMOS FET pipe; 58,59 are the DDD that diffuses to form in the DP trap, respectively as source electrode and the drain electrode of Iso-NMOS FET.
Step f as shown in Figure 6A, may further comprise the steps:
F1. dense P type (P+) photoetching defines the zone that dense P type (P+) ion injects;
F2. dense P type (P+) injects, as the base stage of source electrode, drain electrode and the bipolar npn type pipe of PMOS pipe;
F3. plasma reinforced chemical vapour deposition (PECVD) boron-phosphorosilicate glass (BPSG, B+P+siliconGlass), the silex glass that promptly contains B+ and P+ ion, because it has flowability, cover behind this layer the class hour smooth surface, in order to prevent that B+ and P+ ion from infiltrating device, need between device and BPSG, lay one deck dielectric layer and be used for isolating;
The f4.BPSG densification;
F5. contact hole photoetching, contact hole are the contact holes of interface unit and ground floor metal;
F6. contact hole etching;
Above technology is basic identical with existing C MOS technology, just is not described in detail here.
Fig. 6 B is that step f injects P type ion, lay BPSG and make the schematic diagram of device in the continuous contact hole of metal level, wherein 64 are the isolation dielectric layer, 65 is BPSG, 61 is the P type ion districts that spread in the DP trap among the figure, be called P+ base (P+BASE) among the figure, base stage as bipolar npn type pipe, 62 and 63 is the P type ion districts that spread in the N trap, be called P+ source/drain regions (P+Source/Drain) among the figure, form the source electrode and the drain electrode of PMOS pipe respectively, 64B is the contact hole opening, is called contact hole opening (CONTACT Openings) among the figure, and dielectric layer 64 and the openings on the BPSG65 all among Fig. 6 B all are contact hole openings.
Step g is laid the first metal layer, dielectric layer, makes the continuous through hole of two metal layers and lays second metal level, shown in Fig. 7 A, comprises following rapid:
G1. the first metal layer deposits, and the first metal layer can use Ti/TiN/AlSiCu, and the first metal layer river is filled up all contact hole holes and covered full all surfaces;
G2. the first metal layer photoetching and etching are removed lip-deep unwanted the first metal layer;
G3. dielectric layer (SiO
2/ SOG/SiO
2) deposition, dielectric layer comprises 3 layers, is silicon oxide sio up and down
2, the centre is SOG dielectric layer (SOG);
G4. via etch, through hole are the contact holes that connects the first metal layer and second metal level;
G5. second layer metal deposition, second metal level can use Ti/TiN/AlSiCu, and second metal level will fill up all through hole holes and cover full all surfaces;
G6. second metal level photoetching and the etching removed lip-deep unwanted second metal level;
Above step with and materials used and existing C MOS technology basic identical, just be not described in detail here.
Fig. 7 B is that step g is laid the first metal layer, dielectric layer, through hole that the making two metal layers links to each other and the schematic diagram of laying second metal level; 71 is silica dioxide medium layer (SiO among the figure
2), be called plasma reinforced chemical vapour deposition oxide layer (PECVD Oxide) among the figure, 72 is SOG dielectric layer (SOG), is called the SOG dielectric layer among the figure, 73 is silica dioxide medium layer (SiO
2), plasma reinforced chemical vapour deposition (PECVD Oxide), dielectric layer is the first metal layer below 71, more than be second metal level, hole in the dielectric layer 71,72,73 is through hole hole 74,75 is metal Ti N, it is the metal of the upper space of second metal level, 76 is metal Ti, be the metal on second metal level and dielectric layer 71,72,73 interfaces, 77 is Al, is the major metal of second metal level, except the thin layer on surface is metal Ti and the TiN, second metal level is metal A l.
Step h shown in Fig. 8 A, may further comprise the steps:
H1. passivation layer Si
3N
4And SiO
2Deposition;
H2. passivation layer photoetching;
H3. alloying;
The h4.PCM test;
H5. slice inspection.
Above step all adopts existing C MOS technology, just is not described in detail here.
Fig. 8 B carries out step h and lays passivation layer schematic diagram afterwards, and 81 is silicon nitride Si among the figure
3N
4Layer is called nitride layer (Nitride) among the figure, 82 is silicon oxide sio
2Layer is called oxide skin(coating) (Oxide) among the figure.Step afterwards is same as the prior art, and those skilled in the art only needs can finish with reference to existing CMOS technology.
Adopt technical scheme of the present invention, method by increasing the DP trap well on chip piece in conjunction with cmos device and bipolar device, compare with traditional CMOS technology simultaneously, only increased few steps, the increase of cost has also seldom reached the purpose of obtaining high performance BiCMOS chip with as far as possible little cost.
Claims (6)
1. manufacture method that the BiMOS hybrid digital-analog integrated circuit of DP trap is arranged may further comprise the steps:
A. on P type substrate, make N trap and P trap with CMOS technology;
B. use mask in the N trap, to define the zone of DP trap, the zone of non-DP trap is made with photoresist cover, carry out ion in the zone of DP trap and inject and make the DP trap;
C. in N trap, P trap or DP trap, be manufactured with the source region with CMOS technology;
D. lay polysilicon, comprise two-layer polysilicon, the polysilicon of ground floor is as the grid of metal-oxide-semiconductor and the bottom electrode of polysilicon resistance and polysilicon capacitance, and the polysilicon of the second layer is as the top electrode of polysilicon resistance and polysilicon capacitance;
E. in N trap, P trap or DP trap, inject N type ion, make the double-diffused drain electrode structure, form the emitter and collector of source electrode, drain electrode and the bipolar npn type pipe of NMOS pipe;
F. in N trap or DP trap, inject P type ion, form the base stage of source electrode, drain electrode and the described bipolar npn type pipe of PMOS pipe; Lay boron-phosphorosilicate glass with CMOS technology, and the contact hole that links to each other with device and metal level of making;
G. lay the first metal layer, dielectric layer, in dielectric layer, make to connect the through hole of the first metal layer, lay second metal level on dielectric layer and connect described through hole;
H. lay passivation layer with CMOS technology, carry out alloying afterwards and carry out the on-line parameter test, next encapsulation, making finishes.
2. the manufacture method that the BiMOS hybrid digital-analog integrated circuit of DP trap is arranged as claimed in claim 1 is characterized in that, the ion that described step b injects when making the DP trap is boron (B11+) ion, and concentration is 2.5E13cm
-2, energy is 150keV, the DP trap diffuses to form in the N trap.
3. the manufacture method that the BiMOS hybrid digital-analog integrated circuit of DP trap is arranged as claimed in claim 1; it is characterized in that described step e injects N type ion, make in the double-diffused drain electrode structure; the ion that dense N type ion double-diffused drain electrode layer injects is phosphorus (P31+) ion, and concentration is 3E13cm
-2, energy is 40keV, and the ion that the N+ layer injects is arsenic (As75+) ion, and concentration is 1.7E17cm
-2, energy is 150keV.
4. BiMOS hybrid digital-analog integrated circuit that the DP trap is arranged comprises it is characterized in that the structure of CMOS integrated circuit,
The BiMOS hybrid digital-analog integrated circuit of the described DP of having trap comprises the DP trap that is arranged in the N trap, can form the base stage of NMOS pipe and bipolar npn type pipe;
The BiMOS hybrid digital-analog integrated circuit of the described DP of having trap also comprises the double-diffused drain electrode structure, described double-diffused drain electrode structure is to be arranged in N trap, P trap or described DP trap, can form the emitter and collector of source electrode, drain electrode and the described bipolar npn type pipe of NMOS pipe;
The BiMOS hybrid digital-analog integrated circuit of the described DP of having trap comprises two metal layers.
5. the BiMOS hybrid digital-analog integrated circuit that the DP trap is arranged as claimed in claim 4 is characterized in that, described DP trap is to be 2.5E13cm by concentration
-2, energy is that boron (B11+) ion of 150keV diffuses to form in the N trap.
6. the BiMOS hybrid digital-analog integrated circuit that the DP trap is arranged as claimed in claim 4 is characterized in that, the dense N type ion double-diffused drain electrode layer of described double-diffused drain electrode structure is to be 3E13cm by concentration
-2, energy is that phosphorus (P31+) ion of 40keV diffuses to form in N trap, P trap or described DP trap; The N+ layer of described double-diffused drain electrode structure is to be 1.7E17cm by concentration
-2, energy is that arsenic (As75+) ion of 150keV diffuses to form in N trap, P trap or described DP trap.
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| CN100409449C (en) * | 2005-04-27 | 2008-08-06 | 上海华虹Nec电子有限公司 | Polysilicon-insulating layer-polysilicon capacitance, high-capacitant polysilicon device and its production |
| US7598560B2 (en) * | 2007-03-30 | 2009-10-06 | Kavalieros Jack T | Hetero-bimos injection process for non-volatile flash memory |
| CN101740639B (en) * | 2008-11-24 | 2012-02-29 | 上海华虹Nec电子有限公司 | Manufacturing method of polycrystalline silicon electric resistance |
| CN101635298B (en) * | 2009-06-10 | 2014-12-31 | 北京中星微电子有限公司 | Three-dimensional integrated circuit of planar technology |
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| US4737472A (en) * | 1985-12-17 | 1988-04-12 | Siemens Aktiengesellschaft | Process for the simultaneous production of self-aligned bipolar transistors and complementary MOS transistors on a common silicon substrate |
| US5747369A (en) * | 1997-01-13 | 1998-05-05 | Chartered Semiconductor Manufacturing Ltd. | Formation of a capacitor using a sacrificial etch stop |
| US5939753A (en) * | 1997-04-02 | 1999-08-17 | Motorola, Inc. | Monolithic RF mixed signal IC with power amplification |
| US5888861A (en) * | 1997-06-06 | 1999-03-30 | Integrated Device Technology, Inc. | Method of manufacturing a BiCMOS integrated circuit fully integrated within a CMOS process flow |
| US6472716B2 (en) * | 2001-03-22 | 2002-10-29 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device with a well wherein a scaling down of the layout is achieved |
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