CN1309044C - BiMOS digital-analog mixed integrated circuit with DP sink and producing method thereof - Google Patents

BiMOS digital-analog mixed integrated circuit with DP sink and producing method thereof Download PDF

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CN1309044C
CN1309044C CN 03116993 CN03116993A CN1309044C CN 1309044 C CN1309044 C CN 1309044C CN 03116993 CN03116993 CN 03116993 CN 03116993 A CN03116993 A CN 03116993A CN 1309044 C CN1309044 C CN 1309044C
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CN1549330A (en )
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乔琼华
肖明
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上海先进半导体制造有限公司
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Abstract

一种有DP阱的BiMOS数模混合集成电路的制造方法,在用CMOS工艺在P型衬底上制作N阱和P阱后在N阱中使用掩膜定义DP阱的区域,将非DP阱的区域使用光刻胶覆盖,在DP阱的区域进行离子注入制作DP阱,以后的步骤与的双层多晶硅双层金属CMOS制造工艺基本相同。 A kind of method of producing a BiMOS integrated circuit digital-analog mixed well DP, DP well defined area mask used in the production of the N-well and N-well on a P-well CMOS process with P-type substrate, the well non-DP use areas covered by the photoresist, ion-implanted in the well region DP DP production wells, and the subsequent step of double-poly double-layer metal CMOS fabrication process is substantially the same. 一种用上述制造方法制造的有DP阱的BiMOS数模混合集成电路,包括CMOS集成电路的结构,还包括N阱中扩散形成的DP阱,可形成NMOS管的基极和NPN型Bipolar管。 A method of manufacturing by the above methods for producing a BiMOS integrated circuit Mixed-DP wells, including CMOS integrated circuit structure further includes a DP-well formed in N-well diffusion, the base may be formed of NMOS transistor and the NPN Bipolar tube. 采用上述技术方案,能在一块芯片上结合CMOS器件和Bipolar器件,同时仅增加了少量步骤与成本,达到了以尽可能小的代价获取高性能的BiCMOS芯片的目的。 With the above technical solutions, capable of binding in a CMOS device and Bipolar devices, while only a small number of steps and increased cost, achieve the purpose of obtaining a high-performance BiCMOS chip with the lowest possible cost.

Description

有DP阱的BiMOS数模混合集成电路及其制造方法 There DP well mixed-BiMOS integrated circuit and its manufacturing method

技术领域 FIELD

本发明涉及BiMOS(组合式双极型金属氧化物半导体)数摸混合集成电路制造领域,由其涉及一种有DP(深P型)阱的BiMOS数模混合集成电路及其制造方法。 The present invention relates to a BiMOS (bipolar modular metal oxide semiconductor) manufacturing hybrid integrated touch number, by digital-analog mixed relates to an integrated circuit manufacturing method thereof DP (deep P-type) well BiMOS.

背景技术 Background technique

目前集成电路中主要使用的是CMOS(互补金属氧化物半导体)器件和双极型器件,这两种器件有各自的优点和局限性,CMOS器件有器件功耗低、集成度高和抗干扰能力强的优点,但也有器件工作速度低、驱动能力差的缺点。 Mainly used in current integrated circuit is a CMOS (Complementary Metal Oxide Semiconductor) devices and bipolar devices, these two devices have their own advantages and limitations, the CMOS device has a low-power devices, high integration and performance, strong advantages, but there are also low-speed device operation, the driving capability of the shortcomings of poor. 双极型器件器件速度快、驱动能力强、模拟精度高的优点,但也有器件功耗高,集成度低的缺点。 Fast speed bipolar devices, driving ability, the advantages of high precision analog, power devices but there are also high, a low degree of integration drawbacks. 由上所述,可看到CMOS和双极型器件的优缺点正好互补,于是,一种把CMOS和双极型两种半导体器件同时制作在同一芯片上的工艺——BiCMOS(组合式双极型金属氧化物半导体)因此发展,以满足业界往高速、高集成度、高性能的大规模集成电路(LSI)和超大规模集成电路(VLSI)的发展要求。 From the above, the advantages and disadvantages can be seen CMOS and bipolar devices is complementary, Thus, a CMOS and the two kinds of bipolar semiconductor device fabricated simultaneously on the same chip process --BiCMOS (combined Bipolar type metal-oxide semiconductor) thus developed to meet the requirements of the industry to the development of high speed, high integration, high performance large scale integrated circuit (LSI) and very large scale integration (VLSI) a.

BiCMOS工艺的基本要求是要将两种器件组合到同一芯片上,将整个电路中需要“高速度”和“电流驱动”部分,以双极型来处理,如电路的输入/输出部分(I/O);而将电路中“高集成”“低功耗”区域,如阵列,以CMOS来制作,由此得到的芯片具有良好的综合性能,但制造BiCMOS需在原来CMOS为设计主体的电路中加入双极型器件,现有的BiCMOS工艺将比单纯的CMOS工艺复杂,而且成本也会提高。 Basic requirements To BiCMOS process is a combination of the two devices on the same chip, the entire circuit is required "high speed" and the "current drive" section to bipolar processed, such as input circuit / output portion (I / O); and the circuit "high integration", "low power" area array, fabricated in CMOS, the chip thus obtained having good overall performance, but manufacturing a BiCMOS circuit as required in the original design of CMOS main body Join bipolar, BiCMOS process than existing pure CMOS process is complex, and the cost will increase.

发明内容 SUMMARY

本发明的目的是提供一种有DP阱的BiMOS数模混合集成电路及其制造方法,在CMOS工艺基础上增加DP阱将CMOS与双极性器件集成到同一个工艺中,制成所需的电阻、电容、二极管、高低压PMOS(P型金属氧化物半导体)/NMOS(N型金属氧化物半导体)、隔离NMOS(隔离N型金属氧化物半导体)和NPN等器件,开发和完善线宽1.2um的双层多晶硅双层金属BiCMOS数模混合集成电路的制造工艺。 Object of the present invention is to provide a well with a DP BiMOS integrated circuit and mixed-manufacturing method, the increase DP-well CMOS process based on a CMOS integrated bipolar devices with the same process to produce the desired resistors, capacitors, diodes, high and low voltage PMOS (P-type metal oxide semiconductor) / NMOS (N-type metal oxide semiconductor), isolating the NMOS (N-type metal oxide semiconductor spacer) and the other NPN devices, develop and improve line width 1.2 um double polysilicon manufacturing process of mixed analog-digital integrated circuit bimetallic BiCMOS.

为了达到上述目的,本发明采用如下技术方案:根据本发明的一方面,提供一种有DP阱的BiMOS数模混合集成电路的制造方法,包括以下步骤:a.用CMOS工艺在P型衬底上制作N阱和P阱;b.使用掩膜在N阱中定义DP阱的区域,将非DP阱的区域使用光刻胶覆盖,在DP阱的区域进行离子注入制作DP阱;c.用CMOS工艺在N阱、P阱或DP阱中制作有源区;d.铺设多晶硅,包括两层多晶硅,第一层的多晶硅作为MOS管的栅极以及多晶硅电阻和多晶硅电容的下电极,第二层的多晶硅作为多晶硅电阻和多晶硅电容的上电极;e.在N阱、P阱或DP阱中注入N型离子,制作双扩散漏极(DDD)结构,形成NMOS管的源极、漏极以及NPN型双极型管的发射极和集电极;f.在N阱或DP阱中注入P型离子,形成PMOS管的源极、漏极以及所述NPN型双极型管的基极;用CMOS工艺铺设硼磷硅玻璃,并制作与器件及金属层相连的 To achieve the above object, the present invention employs the following technical solutions: According to an aspect of the present invention, there is provided a method of manufacturing a mixed-DP well a BiMOS integrated circuit, comprising the steps of:. A CMOS process with P-type substrate the production of N well and P well;. B region DP wells using a mask defined in the N-well, the use of non-DP-well region covered by the photoresist, ion-implanted in the well region DP DP production well; C with. in N-well CMOS technology, P-well or DP well active region;. d laying polysilicon, comprising two layers of polysilicon, a gate of the first layer and a polysilicon MOS transistor and the polysilicon resistance lower capacitor electrode, a second the polysilicon layer and polysilicon as a polysilicon resistor capacitor upper electrode;. e N-type ion implantation in the N-well, P-well or well DP, making a double diffused drain (DDD) structure, forming a source electrode of the NMOS transistor, and a drain emitter and collector of the NPN bipolar tube; F P-type ions implanted in the N-well or well DP, a source electrode of the PMOS transistor, a drain and a base of the NPN bipolar transistor is;. with CMOS technology laying borophosphosilicate glass, and connected to the device and making the metal layer 触孔;g.铺设第一金属层、介质层,于介质层中制作连接第一金属层的通孔,铺设第二金属层于介质层之上并连接所述通孔;h.用CMOS工艺铺设钝化层,之后进行合金化并进行在线参数(PCM)测试,接下来封装,制作完毕。 Contact hole; G laying a first metal layer, a dielectric layer, a dielectric layer produced on the connection through-hole of the first metal layer, laying a second metal layer on the dielectric layer and connected to the through hole;.. H in CMOS laying a passivation layer followed by alloying and line parameters (PCM) test, the next package, production is completed.

所述步骤b制作DP阱时注入的离子为硼(B11+)离子,浓度为2.5E13cm-2,能量为150keV,DP阱是在N阱中扩散形成的。 Injected when making said step b DP boron ion trap (B11 +) ion concentration of 2.5E13cm-2, energy of 150 keV, in the DP well formed in N-well diffusion.

所述步骤e注入N型离子,制作DDD结构中,浓N型离子双扩散漏极(N+DDD)层注入的离子为磷(P31+)离子,浓度为3E13cm-2,能量为40keV,N+层注入的离子为砷(As75+)离子,浓度为1.7E17cm-2,能量为150keV。 Said step e implanting N type ions, making DDD structure, the concentration of N-type ions double diffused drain (N + DDD) layer of implanted ions is phosphorous (P31 +) ions at a concentration of 3E13cm-2, energy of 40keV, N + layer the ion implantation is arsenic (As75 +) ion concentration of 1.7E17cm-2, energy of 150keV.

根据本发明的另一方面,提供一种有DP阱的BiMOS数模混合集成电路,包括CMOS集成电路的结构, According to another aspect of the present invention, there is provided a mixed analog-digital integrated circuits BiMOS DP wells, comprising a structure of a CMOS integrated circuit,

所述有DP阱的BiMOS数模混合集成电路包括位于N阱中的DP阱,可形成NMOS管和NPN型双极型管的基极;所述有DP阱的BiMOS数模混合集成电路还包括DDD结构,所述DDD结构是位于N阱、P阱或所述DP阱中,可形成NMOS管的源极、漏极以及所述NPN型Bipolar管的发射极和集电极;所述有DP阱的BiMOS数模混合集成电路包括两层金属层。 The well has a DP BiMOS integrated circuit includes a digital-analog mixed well DP N well, and the NMOS transistor may be formed in the base NPN bipolar transistor is; there is the DP well BiMOS integrated circuit further comprises a digital-analog mixed DDD structure, DDD structure is located in the N-well, P-well or the DP well, may be formed in the emitter and collector of the NMOS transistor source electrode, the drain electrode and the NPN Bipolar tube; DP has the well the BiMOS integrated circuit comprising a mixed-two metal layers.

所述DP阱是由浓度为2.5E13cm-2,能量为150keV的硼(B11+)离子在N阱中扩散形成的。 The DP is well concentration 2.5E13cm-2, energy of 150keV boron (B11 +) ions are diffused in an N-well formed.

所述DDD结构的N+DDD层是由浓度为3E13cm-2,能量为40keV的磷(P31+)离子在N阱、P阱或所述DP阱中扩散形成的;所述DDD结构的N+层是由浓度为1.7E17cm-2,能量为150keV的砷(As75+)离子在N阱、P阱或所述DP阱中扩散形成的。 The N + layer DDD DDD structure is composed of a concentration of 3E13cm-2, energy of 40keV phosphorus (P31 +) ion diffusion is formed in N-well, P-well or the DP well; DDD structure of the N + layer having a concentration of 1.7E17cm-2, energy of 150keV arsenic (As75 +) ion diffusion is formed in N-well, P-well or well DP.

由于采用了上述技术方案,本发明所述的一种有DP阱的BiMOS数模混合集成电路的制造方法通过增加DP阱的方法很好的在一块芯片上结合CMOS器件和双极型器件,同时与传统的CMOS工艺相比,仅增加了少量步骤,成本的增加也很少,达到了以尽可能小的代价获取高性能的BiCMOS芯片的目的。 By adopting the technical solution of the present invention have one of the method of manufacturing a mixed analog-digital integrated circuit DP well BiMOS good combination of bipolar and CMOS devices on a single chip by increasing the DP well a method, while compared with conventional CMOS processes, increased by only a small number of steps to increase the cost of rarely achieve the purpose of obtaining high-performance BiCMOS chips with the smallest possible price.

附图说明 BRIEF DESCRIPTION

图1A是本发明的一个实施例中进行步骤a用制作N阱和P阱的流程图;图1B是本发明的一个实施例中进行步骤a用制作N阱和P阱的示意图;图2是本发明的一个实施例中进行步骤b制作DP阱的流程图和示意图;图3A是发明的一个实施例中进行步骤c制作有源区流程图;图3B是发明的一个实施例中进行步骤c制作有源区示意图;图4A是发明的一个实施例中进行步骤d铺设两层多晶硅的流程图;图4B是发明的一个实施例中进行步骤d铺设两层多晶硅的示意图;图5A是发明的一个实施例中进行步骤e制作DDD结构的流程图;图5B是DDD的结构图;图5C是发明的一个实施例中进行步骤e制作DDD结构的示意图; FIG 1A is a flow chart for making N-well and P-well is a step in the embodiment of the present invention; FIG. 1B is an embodiment of the present invention with a schematic view of a production step N well and P well were embodiment; FIG. 2 is one embodiment of the present invention prepared in step b and schematic flowchart DP well; FIG. 3A is an embodiment of the invention step c is produced in the active region flowchart embodiment; FIG. 3B is one embodiment of step c of the invention production schematic active region; FIG. 4A is a flowchart of step d Example polysilicon layers laid one embodiment of the invention; FIG. 4B is a schematic view of a laying step d polysilicon layers in the embodiment of the invention; FIG. 5A is the invention e embodiment of a flowchart of the steps DDD structure produced for example; FIG. 5B is a configuration diagram of a DDD; FIG. 5C is a schematic view of a production step e DDD structure embodiment of the invention;

图6A是发明的一个实施例中进行步骤f注入P型离子、铺设BPSG(硼磷硅玻璃)并制作器件于金属层相连的接触孔的流程图;图6B是发明的一个实施例中进行步骤f注入P型离子、铺设BPSG并制作器件于金属层相连的接触孔的示意图;图7A是发明的一个实施例中进行步骤g铺设第一金属层、介质层,制作两层金属层相连的通孔并铺设第二金属层的流程图;图7B是发明的一个实施例中进行步骤g铺设第一金属层、介质层,制作两层金属层相连的通孔并铺设第二金属层的示意图;图8A是发明的一个实施例中进行步骤h铺设钝化层、进行合金化、进行PCM测试、封装的流程图。 6A is a flowchart of the invention step f implanted P type ions, laying BPSG (borophosphosilicate glass), and contact holes connected to the metal layer of the device according to an embodiment; FIG. 6B is an embodiment of the invention, the step f P-type ion implantation, a schematic lay BPSG and devices connected to the contact hole made in the metal layer; FIG. 7A is one embodiment of the invention step g laying a first metal layer, a dielectric layer, made of two metal layers are connected through the laying a flowchart aperture and the second metal layer; FIG. 7B is a schematic diagram for a first embodiment in step g laying metal layer, a dielectric layer, making the through holes connected to two metal layers and a metal layer is laid a second embodiment of the invention; FIG 8A is a flowchart of steps in laying h passivation layer, alloying PCM-test, a package embodiment of the invention.

图8B铺设钝化层之后的示意图。 FIG. 8B a schematic view after laying a passivation layer.

具体实施方式 detailed description

下面结合实施例和附图进一步说明本发明的技术方案。 Embodiment further below in conjunction with the technical solutions of the present invention and the accompanying drawings.

本发明的一个实施例,准备在一P型衬底上形成以下器件,如图1B的示意图所示,从左至右依次为:一双极型NPN三极管、一NMOS FET管(N型金属氧化物半导体场效应晶体管)、一HV-NMOS FET管(高压N型金属氧化物半导体场效应晶体管)、一Iso-NMOS FET(隔离N型金属氧化物半导体场效应晶体管)管、一PMOS FET(P型金属氧化物半导体场效应晶体管)管以及一个多晶硅电容(Capacitor)。 An embodiment of the present invention, the device is ready to be formed on a P-type substrate, a schematic diagram is shown in Figure 1B, from left to right: a bipolar NPN transistor, an NMOS FET tube (N-type metal oxide semiconductor Field Effect transistor), an HV-NMOS FET pipe (high-voltage N-type metal oxide semiconductor field effect transistor), a Iso-NMOS FET (isolated N-type metal oxide semiconductor field effect transistor) tube, a PMOS FET (P-type metal oxide semiconductor field effect transistor) and a tube-poly capacitor (capacitor).

按照本发明的有DP阱的BiMOS数模混合集成电路的制造方法的步骤,首先进行步骤a用CMOS工艺在P型衬底上制作N阱和P阱,图1A和图1B是该实施例中进行步骤a用制作N阱和P阱的流程图和示意图。 A method of manufacturing steps according to the number of DP Mixed well BiMOS integrated circuit according to the present invention, the first step of making a P-well and N-well CMOS process with P-type substrate, FIGS. 1A and 1B in this embodiment is a step of making the flowchart and schematic diagram of the N-well and P-well. 如图1A所示,制作P阱和N阱的步骤包括:a1.进行初氧,即在P型衬底上形成一层氧化层(二氧化硅SiO2),即图1B中的氧化层11(图中称为氧化层Oxide);a2.LPCVD氮化硅,即在上述氧化层11的表面覆盖一层氮化硅(Si3N4),因为该层氮化硅仅是暂时存在,所以图1B中并为将该层表示出来;a3.N阱光刻,N阱光刻采用CMOS工艺的光刻方法,首先定义出N阱的区域,然后将N阱区域的氮化硅以及氧化层11除去;a4.N阱注入;a5.自对准氧化,N阱区域进行氧化;a6.氮化硅刻蚀,将剩余部分的氮化硅都除去;a7.P阱注入;a8.去氧化层;a9.P阱推进。 , The step of forming the P-well and N-well comprises FIG 1A:. A1 oxygen for early, i.e. form a layer of oxide (silicon dioxide SiO2) on a P type substrate, i.e., the oxide layer 11 in FIG. 1B ( FIG referred oxide layer oxide); a2.LPCVD silicon nitride, i.e. the silicon nitride layer covering (Si3N4) on the surface of the oxide layer 11, nitride layer because the presence of only temporary, and therefore FIG. 1B the layer is expressed out; a3.N well lithography, photolithography N-well CMOS process using a photolithography method, first define the N-well region, and the N-well region and the silicon nitride oxide layer 11 is removed; A4 .N well implant;. a5 self-aligned oxide, N-well oxidation zone;. a6 nitride etch, the remaining portions of silicon nitride are removed; a7.P well implantation;. a8 to the oxide layer; a9. P-well advanced.

上述步骤均与现行的CMOS工艺的步骤基本相同,这里就不再详细描述这些步骤了,上述步骤完成后即如图1B所示:在P型衬底上制作好了N阱和P阱,上层有氧化层11。 The above steps with the existing CMOS process step is substantially the same, these steps will not be described here in detail, after the above steps shown in FIG. 1B: a substrate formed on a P-type well P-well and N-well, the upper layer oxide layer 11.

步骤b,制作DP阱,这是本发明的特点所在。 Step B, DP production well, which is a feature of the invention resides. DP阱是在N阱中扩散形成的,本实施例中,制作DP阱时注入的离子为硼(B11+)离子,其浓度为2.5E13cm-2,能量为150keV。 DP diffusion well is formed in the N-well, in this embodiment, the production of DP implanted boron ion trap (B11 +) ions, at a concentration of 2.5E13cm-2, energy of 150keV. 如图2所示,本实施例中,使用上述浓度,上述能量的的硼(B11+)离子,在N阱中扩散形成了两个DP阱21。 2, in this embodiment, the above-described concentration, the above-described energy boron (B11 +) ions, diffused in the N-well 21 is formed of two DP wells. 在制作完DP阱后,还需在表面形成一层包括氧化硅(SiO2)和氮化硅(Si3N4)的LOCOS(硅局部氧化)场隔离层22。 After the production of DP-well layer formed on the surface needs to comprise a silicon oxide (SiO2) and silicon nitride (Si3N4) in the LOCOS (local oxidation of silicon) field isolation layer 22.

步骤c,制作有源区,包括以下步骤,如图3A所示:c1.基氧,即对所有表面进行氧化;c2.低压化学气相沉积(LPCVD)氮化硅,铺设氮化硅,当作覆盖膜使用;c3.有源区光刻,对有源区进行定义并除去有源区的氮化硅;c4.场区注入,在选定的场氧化区的下方注入高掺杂的离子;c5.场氧化,对选定的场氧化区进行氧化,形成很厚的氧化层(SiO2);c6.去氮化硅/氧化硅,除去剩余的氮化硅/氧化硅。 Step C, making the active region, comprising the following steps, shown in Figure 3A: c1-yloxy, i.e. all surfaces oxidized; C2 low pressure chemical vapor deposition (LPCVD) silicon nitride, silicon nitride laying, as. use cover film;. c3 photolithography active region, the active region is defined and removing the silicon nitride active region;. c4 field region implantation, implantation under the highly doped ions selected field oxide region; . C5 field oxide, the field oxide region selected for oxidized to form thick oxide layer (SiO2);. c6 to the silicon nitride / silicon oxide, to remove the remaining nitride / silicon oxide.

上述步骤均与现行的CMOS工艺相同,这里就不再详细描述了。 Above steps are identical with the existing CMOS process, not described in detail herein.

如图3B所示,图中的灰色区域为场氧化区31,图中称为场氧化层(FieldOxide),这里形成很厚的氧化硅(SiO2),用作不同器件之间的隔离。 As shown in FIG. FIG. 3B is a gray area field oxide regions 31, referred to as a field oxide layer (FieldOxide), where the formation of thick silicon oxide (SiO2), is used as the isolation between different devices. 剩余的氮化硅/氧化硅为32,图中称为薄氧化层(Sacrificial Oxide)。 The remaining silicon nitride / silicon oxide 32, FIG referred thin oxide layer (Sacrificial Oxide).

步骤d,如图4A所示,包括以下步骤:d1.预栅氧,对表面进行氧化; Step d, as shown in Figure 4A, comprising the steps of: d1 pre-gate oxide, the surface is oxidized;.

d2.N掩埋区(BN)光刻,对N掩埋区(Buried N,BN)进行光刻定位;d3.BN注入,进行N掩埋区的离子注入;d4.一次栅氧,对表面进行一次氧化,形成的氧化层较薄,用于低压器件的区域,低压器件所需的氧化层较薄;d5.栅氧光刻;d6.二次栅氧,对表面再进行一次氧化,形成的氧化层较厚,用于高压器件的区域,高压器件所需的氧化层较厚;d7.Vt调节注入,对于各个扩散区的离子浓度进行调节,以调整各个器件的开启电压(Vthreshold);d8.第一层多晶硅沉积,第一层多晶硅作为MOS管的栅极以及多晶硅电阻和多晶硅电容的下电极;d9.第一层多晶硅离子注入,主要用于调整阻值;d10.第一层多晶硅光刻;d11.CAP氧化,即在第一层多晶硅上覆盖一层介质层,用在多晶硅电阻和多晶硅电容器件对应的区域;d12.第二层多晶硅沉积,第二层的多晶硅作为多晶硅电阻和多晶硅电容的上 d2.N buried region (BN) lithography, an N buried region (Buried N, BN) positioned photolithography; d3.BN implantation, ion implantation of an N buried region; D4 a gate oxide on a surface oxidation. oxide layer is thin, a region for forming low-voltage devices, a low-pressure devices required a thin oxide layer;. d5 gate oxide photolithography;. d6 second gate oxide, the surface once again oxidized to form an oxide layer thick, a desired region, a high voltage device for a high voltage device thicker oxide layer; d7.Vt injection adjustment, ion concentration adjustment for each diffusion region, in order to adjust the threshold voltage of each device (Vthreshold);. d8 of depositing a layer of polysilicon, a gate polysilicon layer and a first polysilicon resistor and the capacitor lower electrode of polysilicon MOS transistor;. D9 first polysilicon layer ion implantation, mainly for adjusting the resistance; D10 a first layer of polysilicon lithography.; d11.CAP oxidation, i.e., the first polysilicon layer is covered with a dielectric layer, a polysilicon resistor regions and the polysilicon in the capacitor corresponding member;. d12 depositing a second polysilicon layer, the second polysilicon layer and polysilicon as a polysilicon resistor capacitor on 极;d13.第二层多晶硅离子注入,调节阻值;d14.第二层多晶硅光刻。 Electrode; a second layer of polycrystalline silicon ion implantation D13, adjust the resistance;. D14 of the second layer of polysilicon lithography.

上述步骤与现行的CMOS工艺基本相同,这里就不再详细描述。 The above steps with the existing CMOS process is basically the same, it is not described in detail herein.

图4B是的铺设两层多晶硅的示意图,如图4B所示,41为第一层多晶硅,对于图中所示的NMOS FET管、HV-NMOS FET管、Iso-NMOS FET管和PMOSFET管来说,第一层多晶硅作为这些MOS管的栅极。 4B is a schematic view of the laying of two layers of polysilicon, as shown in FIG. 4B, a first layer 41 of polysilicon, for NMOS FET tube shown in FIG, HV-NMOS FET tube, Iso-NMOS FET for pipes and tubes PMOSFET , the first layer of polycrystalline silicon as the gate of the MOS transistor. 对于多晶硅电容(Capacitor),第一层多晶硅41作为其下电极,图中第一层多晶硅41称为Poly1;如图4所示的多晶硅电容,除了其下电极为第一层多晶硅41外,在第一层多晶硅41上覆盖有介质层42,图中称为硅酸盐氧化层(TEOS-Oxide),其上电极为第二层多晶硅43,图中称为(多晶硅层2,Poly2)。 For poly capacitor (Capacitor), a first polysilicon layer 41 as the lower electrode, a first layer of polysilicon 41 in FIG referred Poly1; poly capacitor shown in Figure 4, except that the lower polysilicon electrode 41 is a first outer layer, the the first polysilicon layer 41 is covered with the dielectric layer 42, referred to in FIG silicate oxide (TEOS-oxide), on which the second electrode polysilicon layer 43, referred to in FIG. (polysilicon layer 2, Poly2).

步骤e,如图5A所示,包括以下步骤:e1.硅酸盐(TEOS)沉积,在多晶硅的两侧区域沉积介质层; Step E, 5A, comprising the steps of:. E1 silicate (TEOS) deposition, dielectric layer is deposited on both sides of the region of polysilicon;

e2.支撑壁(Spacer)刻蚀,将步骤e1中沉积的介质层刻蚀之后,由于多晶硅的厚度,会自然在多晶硅的两则形成弧形的沉积介质层,称为支撑壁(Spacer);e3.N+DDD层光刻;e4.N+DDD层离子注入,本实施例中,N+DDD层注入的是浓度为3E13cm-2,能量为40keV的磷(P31+)离子,N+DDD层可在N阱、P阱或DP阱中扩散形成;e5.N+DDD层退火;e6.浓N型(N+)层光刻;e7.浓N型(N+)层离子注入,本实施例中,浓N型(N+)层注入的是浓度为1.7E17cm-2,能量为150keV的砷(As75+)离子,浓N型(N+)层可在N阱、P阱或所述DP阱中扩散形成;e8.浓N型(N+)层退火。 . E2 support wall (Spacer) etching, after the step of etching the deposited dielectric layer, the thickness of polysilicon, polysilicon naturally in two arcuate deposited dielectric layer is formed e1, called support wall (Spacer); e3.N + DDD layer lithography; e4.N + DDD ion-implanted layer, in this embodiment, N + DDD layer is implanted at a concentration of 3E13cm-2, energy of 40keV phosphorus (P31 +) ions, N + DDD layer may be diffused N well, P-well or well formed DP; e5.N + DDD layer is annealed;. e6 concentration N type (N +) layers photolithography;. e7 concentration N type (N +) ion-implanted layer, the present embodiment , concentration N type (N +) layer is injected to a concentration of 1.7E17cm-2, energy of 150keV arsenic (As75 +) ion concentration N type (N +) layers may be diffused N well, P-well or the DP well formed ;. E8 concentration N type (N +) layer is annealed.

上述步骤与现行的CMOS工艺基本相同,所以这里就不再详细描述。 The above steps with the existing CMOS process is basically the same, so they are not described in detail herein.

图5B是DDD的结构图,图5B中,51为Spacer,52为N+DDD层,53为浓N型(N+)层。 5B is a configuration diagram of a DDD, 5B, 51 Spacer, 52 to DDD N + layer, 53 is a concentrated N-type (N +) layers.

图5C是发明的一个实施例中进行步骤e制作DDD结构的示意图,图中51为支撑壁(Spacer),可见,在各个用作MOS管栅极的第一层多晶硅两侧都有支撑壁(Spacer)。 5C is a schematic view of the invention step e DDD structure produced in the embodiment, FIG. 51 is a support wall (Spacer), seen in the respective sides of the first polysilicon layer as a gate MOS transistor has a support wall ( Spacer). 从图5C中还可见,上述的DDD结构可作为NMOS管的源极、漏极以及双极型管的发射极和集电极,图中54为在DP阱中扩散形成的DDD,作为Bipolar NPN管的发射极,55为在N阱中扩散形成的DDD,作为双极型NPN管的集电极,56是在P阱中扩散形成的DDD,作为NMOS FET管的源极,57是在N阱中扩散形成的DDD,作为HV-NMOS FET管的漏极;58、59为在DP阱中扩散形成的DDD,分别作为Iso-NMOS FET的源极和漏极。 Can also be seen in Figure 5C, the above-described DDD structure as the source electrode of the NMOS transistor, the drain and the bipolar emitter and collector tube, FIG. 54 is formed in the diffusion DDD DP well as Bipolar NPN tube the emitter 55 is formed in the N diffusion DDD well as the collector of the NPN bipolar, DDD diffusion 56 formed in the P-well, as the source of NMOS FET transistor is, in the N-well 57 DDD diffusion formed as HV-NMOS FET drain pipe; DDD 58, 59 is formed by diffusion in the DP well, it was used as the source and drain of Iso-NMOS FET.

步骤f,如图6A所示,包括以下步骤:f1.浓P型(P+)光刻,定义浓P型(P+)离子注入的区域;f2.浓P型(P+)注入,作为PMOS管的源极、漏极以及NPN型双极型管的基极;f3.等离子增强化学气相沉积(PECVD)硼磷硅玻璃(BPSG,B+P+siliconGlass),即含有B+与P+离子的硅玻璃,由于其具有流动性,覆盖该层后课时表面光滑,为了防止B+与P+离子渗入器件,需要在器件与BPSG之间铺设一层介质层用来隔离;f4.BPSG致密;f5.接触孔光刻,接触孔是连接器件与第一层金属的接触孔;f6.接触孔刻蚀;以上技术基本与现有的CMOS工艺相同,这里就不再详细描述。 Step F, shown in Figure 6A, comprising the steps of:.. F1 concentration P-type (P +) photolithography, defines thick P type (P +) ion implanted region; F2 concentration P-type (P +) is injected, as a PMOS transistor the source, base drain and an NPN bipolar transistor is;. f3 plasma enhanced chemical vapor deposition (PECVD) borophosphosilicate glass (BPSG, B + P + siliconGlass), i.e. containing a B + and the P + silicon glass ionomer, because of its flowability, the smoothness of the layer covering the surface of hours, in order to prevent the P + B + iontophoresis devices, the need to lay a dielectric layer for isolating between the device and the BPSG; f4.BPSG compact; F5 contact hole lithography. , the contact hole is a contact hole connecting the metal layer of the first device;. F6 contact hole etching; substantially the same over the prior art CMOS process, not described in detail herein.

图6B是步骤f注入P型离子、铺设BPSG并制作器件于金属层相连的接触孔的示意图,其中64为隔离用介质层,65为BPSG,图中61是在DP阱中扩散的P型离子区,图中称为P+基区(P+BASE),作为NPN型双极型管的基极,62和63是在N阱中扩散的P型离子区,图中称为P+源区/漏区(P+Source/Drain),分别形成PMOS管的源极和漏极,64B为接触孔开口,图中称为接触孔开口(CONTACT Openings),图6B中所有的介质层64和BPSG65上的开口均是接触孔开口。 6B is a step f implanted P type ions, lay BPSG and a schematic view of contact hole means connected to the metal layer is produced, where 64 is the isolation dielectric layer 65 of BPSG, FIG. 61 is diffused in the DP well P-type ions region, called FIG P + base region (P + bASE), a base of the NPN bipolar transistor is, 62 and 63 are P-type ions diffused in the N-well region in FIG called P + source / drain region (P + source / drain), forming a source electrode and a drain electrode of the PMOS transistor, 64B of the contact openings, referred to as contact openings figure (CONTACT openings), in FIG. 6B upper dielectric layer 64 and all of BPSG65 opening contact holes are open.

步骤g,铺设第一金属层、介质层,制作两层金属层相连的通孔并铺设第二金属层,如图7A所示,包括以下骤:g1.第一金属层沉积,第一金属层可以使用Ti/TiN/AlSiCu,第一金属层江填满所有的接触孔孔并覆盖满所有的表面;g2.第一金属层光刻并刻蚀,将表面上的不需要的第一金属层去掉;g3.介质层(SiO2/SOG/SiO2)沉积,介质层包括3层,上下均为氧化硅SiO2,中间为SOG介质层(SOG);g4.通孔刻蚀,通孔是连接第一金属层与第二金属层的接触孔;g5.第二金属层沉积,第二金属层可以使用Ti/TiN/AlSiCu,第二金属层将填满所有的通孔孔并覆盖满所有的表面;g6.第二金属层光刻并刻蚀,将表面上的不需要的第二金属层去掉;以上步骤与及使用材料与现有的CMOS工艺基本相同,这里就不再详细描述。 Step g, the laying of a first metal layer, a dielectric layer, making the through holes connected to two metal layers and a second metal layer is laid, FIG. 7A, includes the following step:. G1 depositing a first metal layer, a first metal layer use Ti / TiN / AlSiCu, the first metal layer to fill all contact holes Jiang aperture and to cover all over the surface;. g2 photolithography and etching the first metal layer, the unnecessary metal layer on the surface of the first remove;. g3 dielectric layer (SiO2 / SOG / SiO2) is deposited, the dielectric layer 3 comprises a layer of SiO2 of upper and lower silicon oxide, an intermediate dielectric layer of SOG (SOG);. g4 via etching, the through hole is connected to a first a contact hole and the second metal layer, the metal layer;. g5 depositing a second metal layer, the second metal layer may be Ti / TiN / AlSiCu, the second metal layer to fill all of the holes and covering the through holes all over the surface; . the second metal layer G6 photolithography and etching, the unnecessary metal layer on the second surface is removed; and the above steps with the use of conventional materials and substantially the same CMOS process, not described in detail herein.

图7B是步骤g铺设第一金属层、介质层,制作两层金属层相连的通孔并铺设第二金属层的示意图;图中71为二氧化硅介质层(SiO2),图中称为等离子增强化学气相沉积氧化层(PECVD Oxide),72为SOG介质层(SOG),图中称为SOG介质层,73为二氧化硅介质层(SiO2),等离子增强化学气相沉积(PECVD Oxide),介质层71以下的均为第一金属层,以上均为第二金属层,介质层71、72、73中的孔均为通孔孔74,75为金属TiN,为第二金属层的最上表面的金属,76为金属Ti,为第二金属层与介质层71、72、73交界面上的金属,77为Al,为第二金属层的主要金属,除了表面的薄层为金属Ti和TiN外,第二金属层均为金属Al。 7B is a step g laying a first metal layer, a dielectric layer, making the through holes connected to two metal layers and a second metal layer is a schematic view of laying; FIG. 71 is a silicon dioxide dielectric layer (SiO2), called plasma in FIG. enhanced chemical vapor deposition oxide (PECVD oxide), 72 is a SOG dielectric layer (SOG), referred to in FIG SOG dielectric layer, the dielectric layer 73 is silicon dioxide (SiO2), plasma enhanced chemical vapor deposition (PECVD oxide), medium the following are a first layer 71 of the metal layer, a second metal layer over both the dielectric layer 71, a hole-hole vias 74, 75 are metallic TiN, is the uppermost surface of the second metal layer metal, 76 is a metal Ti, a metal and a second metal layer 71, the boundary surface between the dielectric layer 77 of Al, as the primary metal of the second metal layer, except for an outer metal surface of a thin layer of Ti and TiN the second metal layer is a metal Al.

步骤h,如图8A所示,包括以下步骤:h1.钝化层Si3N4和SiO2沉积;h2.钝化层光刻;h3.合金化;h4.PCM测试;h5.出片检查。 Step h, as shown in FIG. 8A, comprising the steps of: h1 Si3N4 and SiO2 passivation layer is deposited; passivation layer lithography H2; H3 alloying; h4.PCM test; H5 the examination.....

以上步骤均采用现有的CMOS工艺,这里就不再详细描述。 The above steps are used conventional CMOS process, it is not described in detail herein.

图8B进行步骤h铺设钝化层之后的示意图,图中81是氮化硅Si3N4层,图中称为氮化物层(Nitride),82为氧化硅SiO2层,图中称为氧化物层(Oxide)。 FIG 8B is a schematic view of the step h after the laying of the passivation layer, FIG. 81 is a silicon nitride Si3N4 layer, the nitride layer is referred to FIG. (Nitride), 82 is a silicon oxide SiO2 layer, oxide layer, referred to in FIG. (Oxide ). 之后的步骤与现有技术相同,本领域的技术人员只需参照现有CMOS工艺即可完成。 After the same step in the prior art, the present art only with reference to the prior art CMOS process to complete.

采用本发明的技术方案,通过增加DP阱的方法很好的在一块芯片上结合CMOS器件和双极型器件,同时与传统的CMOS工艺相比,仅增加了少量步骤,成本的增加也很少,达到了以尽可能小的代价获取高性能的BiCMOS芯片的目的。 Aspect of the present invention, a good combination of increasing DP by methods well in a CMOS device and a bipolar device, while compared with the conventional CMOS process, only a small number of steps increases, an increase in cost rarely achieve the purpose of obtaining high-performance BiCMOS chips with the smallest possible price.

Claims (6)

  1. 1.一种有DP阱的BiMOS数模混合集成电路的制造方法,包括以下步骤:a.用CMOS工艺在P型衬底上制作N阱和P阱;b.使用掩膜在N阱中定义DP阱的区域,将非DP阱的区域使用光刻胶覆盖,在DP阱的区域进行离子注入制作DP阱;c.用CMOS工艺在N阱、P阱或DP阱中制作有源区;d.铺设多晶硅,包括两层多晶硅,第一层的多晶硅作为MOS管的栅极以及多晶硅电阻和多晶硅电容的下电极,第二层的多晶硅作为多晶硅电阻和多晶硅电容的上电极;e.在N阱、P阱或DP阱中注入N型离子,制作双扩散漏极结构,形成NMOS管的源极、漏极以及NPN型双极型管的发射极和集电极;f.在N阱或DP阱中注入P型离子,形成PMOS管的源极、漏极以及所述NPN型双极型管的基极;用CMOS工艺铺设硼磷硅玻璃,并制作与器件及金属层相连的接触孔;g.铺设第一金属层、介质层,于介质层中制作连接第一金属层的通孔 CLAIMS 1. A method for producing a mixed analog-digital integrated circuit DP wells BiMOS, comprising the steps of: a CMOS process with P-well and N-well on a P type substrate; b using a mask defined in the N-well. DP-well region, the well region of the non-DP use covered by the photoresist, ion-implanted in the well region DP DP production well; C with an active region in the CMOS process N well, P-well or well DP;. d laying polycrystalline silicon, comprising two layers of polysilicon, a gate of the first layer and a polysilicon MOS transistor and the polysilicon resistance lower capacitor electrode, the second polysilicon layer is a polysilicon resistor and a capacitor electrode of polysilicon;. E N well emitter and collector, the P-well or N-type ion implantation DP well, making the double diffused drain structure of the NMOS transistor forming the source, drain and NPN bipolar tube; F in a well or N-well DP. implanting P-type ions, the source electrode of the PMOS transistor, a drain and a base of the NPN bipolar transistor is; in CMOS laying borophosphosilicate glass, and contact holes connected with the device and the metal layer; G the through-hole laying a first metal layer, a dielectric layer, the dielectric layer on the first metal layer for forming the connector 铺设第二金属层于介质层之上并连接所述通孔;h.用CMOS工艺铺设钝化层,之后进行合金化并进行在线参数测试,接下来封装,制作完毕。 Laying a second metal layer on the dielectric layer and connected to the through hole;. H laying in CMOS passivation layer followed by alloying and online parameter test, the next package, production is completed.
  2. 2.如权利要求1所述的有DP阱的BiMOS数模混合集成电路的制造方法,其特征在于,所述步骤b制作DP阱时注入的离子为硼(B11+)离子,浓度为2.5E13cm-2,能量为150keV,DP阱是在N阱中扩散形成的。 2. The method for producing the mixed-DP well BiMOS integrated circuit according to claim 1, wherein said step b production of injection wells DP boron ions (B11 +) ion concentration of 2.5E13cm- 2, energy of 150keV, DP diffusion well is formed in the N-well.
  3. 3.如权利要求1所述的有DP阱的BiMOS数模混合集成电路的制造方法,其特征在于,所述步骤e注入N型离子,制作双扩散漏极结构中,浓N型离子双扩散漏极层注入的离子为磷(P31+)离子,浓度为3E13cm-2,能量为40keV,N+层注入的离子为砷(As75+)离子,浓度为1.7E17cm-2,能量为150keV。 3. The method for producing the mixed-DP well BiMOS integrated circuit according to claim 1, wherein said N-type ion implantation step e, making a double diffused drain structure, the double-diffused N-type ion concentration a drain layer of implanted ions is phosphorous (P31 +) ions at a concentration of 3E13cm-2, energy of 40keV, N + ion-implanted layer of arsenic (As75 +) ion concentration of 1.7E17cm-2, energy of 150keV.
  4. 4.一种有DP阱的BiMOS数模混合集成电路,包括CMOS集成电路的结构,其特征在于,所述有DP阱的BiMOS数模混合集成电路包括位于N阱中的DP阱,可形成NMOS管和NPN型双极型管的基极;所述有DP阱的BiMOS数模混合集成电路还包括双扩散漏极结构,所述双扩散漏极结构是位于N阱、P阱或所述DP阱中,可形成NMOS管的源极、漏极以及所述NPN型双极型管的发射极和集电极;所述有DP阱的BiMOS数模混合集成电路包括两层金属层。 A BiMOS integrated circuit with a mixed-DP wells, comprising a structure of a CMOS integrated circuit, wherein said well has a DP BiMOS integrated circuit includes a digital-analog mixed well to DP N-well, may be an NMOS base pipe and an NPN bipolar transistor is; there is the DP well BiMOS integrated circuit further comprises a digital-analog mixed double diffused drain structure, the double diffused drain structure is the N-well, P-well or the DP well, emitter and collector may be formed NMOS transistor source electrode, the drain electrode and the NPN bipolar tube; have the DP well BiMOS integrated circuit comprising a mixed-two metal layers.
  5. 5.如权利要求4所述的有DP阱的BiMOS数模混合集成电路,其特征在于,所述DP阱是由浓度为2.5E13cm-2,能量为150keV的硼(B11+)离子在N阱中扩散形成的。 5. There Mixed-DP well a BiMOS integrated circuit according to claim 4, wherein said concentration is well DP 2.5E13cm-2, energy of 150keV boron (B11 +) ions in the N-well diffusion formation.
  6. 6.如权利要求4所述的有DP阱的BiMOS数模混合集成电路,其特征在于,所述双扩散漏极结构的浓N型离子双扩散漏极层是由浓度为3E13cm-2,能量为40keV的磷(P31+)离子在N阱、P阱或所述DP阱中扩散形成的;所述双扩散漏极结构的N+层是由浓度为1.7E17cm-2,能量为150keV的砷(As75+)离子在N阱、P阱或所述DP阱中扩散形成的。 6. The integrated circuit has a digital-analog mixed well BiMOS 4 DP claim, wherein the concentration of N-type double-diffused drain structure of the ion double diffused drain layer having a concentration of 3E13cm-2, energy of 40keV phosphorus (P31 +) ions in the N-well, P-well or well diffusion formed DP; double diffused drain structure of the N + layer having a concentration of 1.7E17cm-2, energy of 150keV arsenic (As75 + ) ion diffusion is formed in N-well, P-well or well DP.
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