CN1308789A - System for generating an accurate low-noise periodic signal - Google Patents
System for generating an accurate low-noise periodic signal Download PDFInfo
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- CN1308789A CN1308789A CN 99808183 CN99808183A CN1308789A CN 1308789 A CN1308789 A CN 1308789A CN 99808183 CN99808183 CN 99808183 CN 99808183 A CN99808183 A CN 99808183A CN 1308789 A CN1308789 A CN 1308789A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
- H03L7/1806—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop the frequency divider comprising a phase accumulator generating the frequency divided signal
Abstract
In the illustrative embodiment, the inventive system includes a low-bit digital-to-analog converter(68) for converting a first signal at a reference frequency to a digital signal. A delta-sigma converter is included for suppressing noise in the digital signal within the predetermined range of the reference frequency and providing a noise-shaped signal in response thereto. A bandpass filter(72) filters out the out-of-band noise and provides an accurate periodic signal which lacks glitch noise. In a particular embodiment, the present inventive system further includes a direct digital synthesizer(42) for providing the first signal at the first frequency and the accurate reference periodic signal is supplied as reference signal to a phase-locked loop(50).
Description
Invention field
The present invention relates to communication system.Particularly, the present invention relates to be used for being created in the system and the technology of the accurate low-noise periodic signal of using in the communication system.
Description of related art
Use periodic electrical signal in various demands are used, wherein the demand is used to comprise and is used for the signal of modulation and demodulation in analog circuit and the reference oscillator (referenceoscillator) of the clock of digital circuit.This application requires very accurate noiselike signal usually, and the function that it consumed is minimum can to keep accuracy simultaneously in very wide scope.
In the digital communication system such as code division multiple access (CDMA) communication system, the accuracy of sort signal is very important.In cdma system, usually the frequency inverted in a certain scope is become different frequency range or frequency bands.The accuracy of clock signal has influenced the accuracy of frequency inverted.For example, in the cdma cellular telephone net, the local oscillator in mobile receiver (LO) provide periodic signal, and it promotes the conversion of Incoming radio frequency (RF) signal to intermediate frequency (IF) signal.If the frequency inaccuracy of local oscillator may will be transformed into through switching signal outside the required IF frequency band range so.
Digital communication system can adopt a kind of waveform that comes the demodulation Digital Modulation in the several different methods.This method comprises binary system-phase-shift keying (BPSK), Quadrature Phase Shift Keying method (QPSK), skew QPSK (OQPSK), M system phase shift keying method (MPSK) or quadrature amplitude modulation (QAM).This system need lock the RF signal that receives usually.Modulator is locked in the ability on this signal and worsens the influence that represented performance all is subjected to the phase noise of the clock signal that produced by the ratio of the bit error rate that records (BER) and theoretic BER.
Usually be created in the periodic signal of using in the digital communication system by the crystal oscillator with specific analog tuner circuit, wherein above-mentioned specific analog tuner circuit is used in response to the frequency of high BER adjusting oscillator.Generally, appended analog tuner circuit is very expensive and huge.
Accurately another kind of but expensive oscillator is a voltage controlled temperature compensated crystal oscillator.Yet the frequency range of these oscillators of self using is restricted.This is the semaphore lock ability of restriction mobile receiver usually.On the other hand, produce accurate relatively periodic signal by voltage controlled oscillator (VCO) with one or more phase-locked loops (PLL).PLL is that output is by the circuit of the signal of phase locking on input signal.PLL improves frequency accuracy, and reduces any phase noise by the periodic signal of VCO output, and has expanded possible reference frequency output., and provide by another PLL, Direct Digital synthesizer (DDS), voltage controlled oscillator or numerically-controlled oscillator (NCO) usually as the reference signal to the input signal of PLL.
By changing the specific PLL parameter such as loop feedback frequency dividing ratio (feedback divide ratio), gradable (in step) regulates output frequency.This, size determined frequency resolution (frequency resolution) and the class interval of PLL also to depend on some PLL parameter class interval.
Must produce several different frequencies according to single periodic signal, to drive the different local oscillators in circuit.Usually come to synthesize periodic signal scope under accurate frequency with PLL according to single periodic signal.
Yet the PLL that is driven by traditional oscillators is subjected to a lot of restrictions usually.For example, the output of PLL comprises tangible parasitic noise usually.In addition, the reference frequency output that causes being allowed owing to poor frequency resolution is restricted relatively, and because the restriction of design causes only scalable PLL in the coarse adjustment frequency diversity itself.
In order to reduce parasitic noise and to increase frequency resolution, adopt two PLL usually.Additional PLL provides to main PLL input or reference signal is provided, and improves the control to reference frequency.This causes exporting the frequency resolution and the precision height of periodic signal.
Yet the 2nd PLL represents additional firmware, and it has taken valuable circuit board space and consumed power.Secondary power consumption is a problem in the scope phone especially, because the battery life of mobile unit is crucial Consideration.In addition, the low switching times of this system causes output drift (wander) significantly between loop is proofreaied and correct of main PLL.
Owing to adopt two restrictions that PLL caused, replace second PLL to provide reference signal with DDS in order to overcome usually to main PLL.DDS generally improves the switch speed of frequency resolution and PLL, has improved the flexibility of PLL design simultaneously.Yet typical DDS drives PLL and exists tangible restriction equally.
Typical DDS long number-analogue converter (DAC).As known in the art, multidigit DAC is subjected to hardware constraints, and it causes producing overshoot (glitch) by the signal of the circuit output of adopting these devices.During all in being less than DAC, overshoot is the result change simultaneously.So when their appropriate value produced the position variation, output waveform presented interim improper value.This overshoot causes parasitic frequency tone (frequency tone) (that is overshoot noise) occurring in DAC output place that very approaches required output frequency.Spurious tone can worsen the PLL performance.
The output of DAC also comprises quantizing noise, and it is directly related with the amplitude resolution of DAC.Amplitude resolution is decided by the figure place that is used for DAC calculating.Have the power that the DAC of good amplitude resolution and frequency response is tending towards overrunning, and very expensive.In addition, when the periodic signal frequency increased, spurious tone more was a problem, and had also further limited the scope that can allow output frequency.
So, need a kind of system that the very accurate periodic signal of wide frequency range can be provided, its noise minimum and switch speed are fast.
Summary of the invention
The invention provides a kind of system and produce accurate periodic signal.In example embodiment, the present invention includes low order digit-analogue converter and under reference frequency, first conversion of signals is become digital signal.Comprise the delta sigma converter and be suppressed at noise in the digital signal in the predetermined reference frequency range, and provide noise setting signal (noise-shaped signal) in response to it.
In a specific embodiment, the present invention also provides a kind of Direct Digital synthesizer that is used to provide first signal under first frequency.Oscillator produces the analog that is input to the Direct Digital synthesizer.The Direct Digital synthesizer converts oscillator output signal to first signal.Low order digit-analogue converter is implemented as the delta sigma digital-to-analog converter.In preferred embodiment, the delta sigma digital-to-analog converter is a delta sigma digital-to-analog converter, and comprises the delta sigma modulator, and its exponent number is greater than 2.Noise setting signal is a digital signal, and by band pass filter it is carried out filtering removing any remaining signal of not wanting, such as by the delta sigma digital-to-analog converter it being released quantizing noise outside frequency band range.The output of delta sigma digital-to-analog converter is input to phase-locked loop.
In preferred embodiment, digital-to-analog converter is the 1 bit digital-analogue converter that does not have overshoot.So the overshoot noise relevant with the use of traditional long number-analog converting is eliminated.But utilization Direct Digital synthesizer provides the more complete control of tolerance frequency scope to noise setting signal, and the complete control to the frequency of output periodic signal is provided subsequently.
The accompanying drawing summary
Fig. 1 comprises the block diagram that drives the number generator of phase-locked loop according to the Direct Digital synthesizer (DDS) of prior art.
The block diagram of the pll synthesizer (PLL) of Fig. 2 delta sigma modulator that to be utilization constitute according to religious doctrine of the present invention and 1 bit digital-analogue converter (DAC).
Fig. 3 is the block diagram of the Δ ∑ modulator of Fig. 2.
Fig. 4 is the signal transfer function of Fig. 3 and the diagrammatic sketch of noise transfer function.
Fig. 5 is the spectrogram from the periodic signal of 1 the DAC output of Fig. 2.
The detailed description of preferred embodiment
Though describe the present invention with reference to the example embodiment that is used for special purpose, it should be understood that the present invention is not limited thereto.Those skilled in the art that will recognize that by reading explanation of the present invention additional corrections, application and embodiment fall within the scope of the invention, and the present invention also is very useful at other field.
The general introduction that traditional DDS is driven the operation of PLL is to be used for promoting the understanding of the present invention below.
Fig. 1 is the block diagram according to the signal generator 40 of prior art.Signal generator 40 has the DDS42 that is driven by reference oscillator 44.Synthetic its frequency of DDS42 relies on digital signal of frequency of its input signal analog signal of reference oscillator 44 outputs (that is, by) and its design parameter.The structure of known DDS42 in the prior art, and at U.S. Patent number 4,965, describe in No. 533 (denomination of invention is " the Direct Digital synthesizer drives phase-locked loop frequency synthesizer ", and transfers assignee of the present invention, is incorporated herein as the reference data).
By multidigit DAC46 the digital signal through synthesizing is converted to analog signal.Then, carry out filtering with removal signal (such as noise) not, and insert between the sampling to remove the not frequency spectrum image of reconstruction waveform by 48 pairs of gained analog signals of DDS filter.Provide the gained filtering signal as reference signal input to PLL50.
PLL50 is the feedback control loop with transfer function, and it designs the output signal that produces its frequency and the frequency dependence of the filtering reference signal that receives from DDS filter 48.The PLL50 output signal frequency is the function of the parameter of PLL50 and DDS42.
PLL50 comprises phase detectors, implements as digital subtractor 78, loop filter 80, voltage controlled oscillator (VCO) 82 and loop divider 84 with branch frequency N.PLL element 78,80,82 and 84 expressions are used for and will export the feedback control loop of the frequency tuning of periodic signal to specific frequency synthesis.
The additional design parameter that DDS42 is provided by DDS42 by interpolation provides the frequency resolution of the PLL that is better than designing previously.Yet as mentioned above, multidigit DAC46 is very responsive for overshoot and parasitic noise, and is difficult to eliminate it by filtering.The output that may worsen PLL50 from parasitic noise and the quantizing noise of DAC46.
Fig. 2 is the block diagram according to the signal generator 60 of content formation of the present invention.Signal generator 60 of the present invention comprises the reference oscillator 44 that is connected to DDS42, is thereafter a Δ ∑ modulator 62,1 DAC68, band pass filter 72 and PLL50, and all these is connected with said sequence.
The digit period signal 64 that the DDS42 output warp that is driven by oscillator 44 synthesizes is to Δ ∑ modulator 62.Δ ∑ modulator 62 is as the noise shaper, and it will be outside the quantizing noise in the synthetic periodic signal 64 be released frequency band, and is suppressed at the quantizing noise in the frequency band.Periodic signal 64 is digitized sine wave.
As following in detail as described in, the feature of resonator circuit (the basic building block piece of Δ ∑ modulator 62) is following noise transfer function:
Y(z)/Q(z)＝(1+A(z)B(z))
-1 (1)
Wherein z is the complex variable about signal frequency, Y (z) is that z territory output, Q (z) expression quantizing noise and the A (z) of basic building block piece and B (z) are the design z function that comes quantizing noise in the inhibition zone (that is, noise are released outside the frequency band or depart from required periodic signal).In this specific embodiment, A (z)=z
-1(1+z
-2)
-1, and B (z)=-z
-1Those skilled in the art that should understand can be used for other functions A (z) and B (z), and does not depart from scope of the present invention.
The signal transfer function of basic building block piece is;
Y(z)/X(z)＝A(z)(1+A(z)B(z))
-1＝1 (2)
Wherein X (z) is the z territory input of basic building block piece.
As following with reference to Fig. 3 in detail described, in example embodiment, Δ ∑ modulator 62 has cascade 3 basic building block pieces 90 together with parameter the 6th rank Δ ∑ modulator 62.Those skilled in the art that should be understood that the Δ ∑ modulator of available different rank and do not depart from scope of the present invention.
With reference to Fig. 2,66 to 1 DAC68 of Δ ∑ modulator 62 output noises setting signal.Δ ∑ modulator 62 is called as Δ ∑ DAC in conjunction with 1 DAC68.As described in detail later such, 1 DAC68 produces a large amount of quantizing noises.This quantizing noise is suppressed in the frequency band, that is, and near required periodic signal frequency.Because 1 DAC68 has only one, so avoided owing to use overshooting problem that multidigit DAC46 caused and the gained parasitic noise of Fig. 2.The simulation output of DAC70 comprises the outer quantizing noise of frequency band, is easy to it is leached with band pass filter 72.So band pass filter 72 provides accurate reference cycle signal on online 74 to PLL50, above-mentioned PLL50 does not have parasitic overshoot noise.Accurate reference signal allows PLL50 by changing the parameter of PLL50, produces accurate output periodic signal 76 over a range of frequencies.
By shown in 1, PLL50 comprises phase detectors, that is, and and signal subtraction device 78, loop filter 80, voltage controlled oscillator (VCO) 82 and have the loop divider 84 of branch frequency N.PLL element 78,80,82 and 84 expressions be used for output periodic signal 76 be tuned to the feedback control loop of specific frequency synthesis.
80 pairs of loop filters carry out filtering from the not signals of subtracter 78 outputs, and will controls voltage 86 and output to VCO82, produce and export periodic signals 76 in being in response to voltage control 86.Output periodic signal 76 is fed back to loop divider 84, and the frequency that its regulates output periodic signal 76 is thought to compare between reference signal 74 and frequency divider output 88 and is prepared.Carry out this relatively by subtracter 78, the output of above-mentioned subtracter 78 is illustrated in poor between the signal 74,88, then it is carried out filtering, draws control voltage 86.
In Application No. 08/893,267 (on July 8th, 1997 application, " phase-locked loop that has the noise shaper " by name is to transfer assignee of the present invention and be incorporated herein as the reference data), provide the another kind of phase-locked loop is described.
Following formula provides output periodic signal F
VC0Frequency and reference frequency between concern:
F
VC0＝F
R*N
R/(2
b) (3)
F wherein
RBe the frequency of reference signal 76, N
RThe FREQUENCY CONTROL variable and the b that are DDS42 are the figure places of using in DDS42.So, the frequency F of reference signal 74
RPrecision directly influence the frequency F of output signal 76
VC0Precision.
Utilization Δ ∑ modulator 62 promotes generation to export periodic signal 76 highly accurately, does not have the parasitic noise relevant with the multidigit DAC of costliness with 1 DAC68.In addition, the parasitic noise that is produced by the multidigit DAC of Fig. 1 does not limit the frequency of reference signal 74.In addition, relative more cheap Δ ∑ modulator 62 and 1 the multidigit DAC46 of DAC68 in Fig. 1.So PLL60 is a clock generation system economic, high precision, it has the allowed output frequency of the relative broad of scope.
Those skilled in the art that should be understood that available 1 DAC68 can be replaced such as 2 or 3 DAC, and do not departed from scope of the present invention by low level DAC.
Fig. 3 is the block diagram of the Δ ∑ modulator 62 of Fig. 2.Δ ∑ modulator 62 is the 6th rank Δ ∑ modulators.Δ ∑ modulator 82 has 3 basic building block pieces 90, also is called the second rank resonator, and their cascades together.Each basic building block piece 90 all comprises digital delay (z
-1) 94, have a voltage gain alpha
iAmplifier 96, adder 98 and the subtracter 100 of (wherein i is the integer index of scope from 0 to 5).Parallel input, output that adder 98 receives from amplifier 96.The input that is provided by digital delay 94 is provided one of amplifier 96, and wherein the input of above-mentioned digital delay still is the input of other amplifiers 96.Provide this input by the digital delay 94 in follow-up resonator 90, perhaps under the situation of output basic block 90, exporting 66 by the noise setting of Δ ∑ modulator 82 provides.
The first basic building block piece 90 receives noise setting signal 66 as the 3rd input to adder 98.Subsequently, building block 90 receives the output of last basic building block piece 90 as the 3rd input to adder 98.
Those skilled in the art that should be understood that the method for known in the prior art formation basic building block piece, and can implement by using any digital signal processing hardware.
The output of adder 98 provides input to subtracter 100.Output by digital delay 94 transmission adders 98 provides the output of resonator 90.Send the output of resonators 90 by another digital delay 94, and provide second input to the adder 98 that forms feedback control loop.
The quantizing noise modeling as line noise element 92, and was taken place before noise setting output 94.
The voltage gain of pickup amplifier 96 is to provide noise transfer function and signal transfer function, and it makes Δ ∑ modulator 82 can satisfy stability and the noise setting requirement for concrete application.The method of picking up gain alpha for amplifier 96 is known in the prior art.In this specific embodiment, gain is α
0=0, α
1=3/2, α
2=0, α
3=-3/4, α
4=0, α
5=1/8.
Fig. 4 is by the signal transfer function 104 of Δ ∑ modulator 62 enforcements of Fig. 3 and Figure 102 of noise transfer function 106.The ordinate of this figure is represented 20*log (V) (that is, decibel (dB)) and abscissa is represented frequency.Noise transfer function 106 is suppressed at the noise in the frequency range 112 (in the frequency band) that is known as working field significantly, and synchronous signal transfer function 104 allows signal not to be suppressed or even to be exaggerated.Noise transfer function 106 and signal transfer function 104 represent that respectively noise and signal gain distribute.
Fig. 5 is the diagrammatic sketch of frequency spectrum 120 of the DAC output 70 of Fig. 2.This figure has corresponding to the ordinate 122 of signal power with corresponding to the abscissa 124 of signal frequency.Frequency spectrum 120 is included in the quantizing noise 126 on the either side of power spike (spike) 128 that required output frequency 130 with the DAC of Fig. 2 output 70 is the center.Suppress noise 126 in the band, that is, and near required output frequency 130 and be pushed out outside the frequency band.The band pass filter 72 of Fig. 2 can be removed noise 126 easily, make signal spike 128 at required output frequency 130 places.So, signal energy is concentrated on required frequency 130 places, this indication cycle's signal has good frequency accuracy.
So, the present invention is described with reference to the specific embodiment of special applications.Those skilled in the art that will be appreciated that additional corrections, application and embodiment drop in its scope.Claims cover all this application, correction and embodiment within the scope of the invention.
Claims (31)
1. a system that produces accurate periodic signal under preset frequency is characterized in that, comprising:
Low order digit-analogue converter is used for first conversion of signals under reference frequency is become digital signal; With
The delta sigma device is used for being suppressed at the noise in the described digital signal in the preset range of described reference frequency, and provides noise setting signal in response to this.
2. invention as claimed in claim 1 is characterized in that, comprises the Direct Digital synthesizer that is used to provide described first signal under described reference frequency.
3. invention as claimed in claim 2 is characterized in that, also comprises being used for providing to described Direct Digital synthesizer the reference oscillator of input.
4. invention as claimed in claim 1 is characterized in that, described low order digit-analogue converter is the delta sigma digital-to-analog converter.
5. invention as claimed in claim 4 is characterized in that, described delta sigma digital-to-analog converter is operated to be less than 4.
6. invention as claimed in claim 5 is characterized in that, described delta sigma digital-to-analog converter is 1 delta sigma digital-to-analog converter.
7. invention as claimed in claim 4 is characterized in that, described delta sigma digital-to-analog converter comprises having exponent number greater than 2 delta sigma modulator.
8. invention as claimed in claim 1 is characterized in that, also comprises being used for producing the synthesizer of exporting periodic signal according to described noise setting signal.
9. invention as claimed in claim 1 is characterized in that described synthesizer is a phase-locked loop.
10. a system that is used to produce low-noise periodic signal is characterized in that, comprises;
Digital device is used to produce the digital signal with first centre frequency;
Filter is used for noise and formalizes described digital signal to be suppressed at the noise around the described centre frequency and to provide digital output signal in response to it;
Convertor device is used for converting described digital output signal to analog signal; With
Loop device, be used for described analog signal be tuned to preset frequency and provide described low-noise periodic signal in response to this.
11. invention as claimed in claim 10 is characterized in that, described digital device comprises the Direct Digital synthesizer.
12. invention as claimed in claim 11 is characterized in that, described digital device also comprises and is used for described Direct Digital synthesizer is provided the oscillator of input.
13. invention as claimed in claim 12 is characterized in that, described oscillator is a voltage controlled oscillator.
14. invention as claimed in claim 10 is characterized in that, described convertor device is the delta sigma digital-to-analog converter.
15. invention as claimed in claim 10 is characterized in that, described delta sigma digital-to-analog converter is operated to be less than 4.
16. invention as claimed in claim 15 is characterized in that described delta sigma digital-to-analog converter is 1 delta sigma digital-to-analog converter.
17. invention as claimed in claim 10 is characterized in that, described filter apparatus comprises the delta sigma modulator.
18. invention as claimed in claim 17 is characterized in that, described delta sigma modulator comprises the delta sigma modulator circuit, and its following column signal transfer function characterizes
Y(z)/Q(z)＝(1+A(z)B(z))
-1
The output signal of the described delta sigma modulator circuit of Y (z) expression in the z territory wherein, Q (z) is illustrated in the quantizing noise the z territory in, and A (z) and B (z) are the functions that designs the z of the interior quantizing noise of inhibition zone.
19. invention as claimed in claim 18 is characterized in that, B (z)=-z
-2
20. invention as claimed in claim 18 is characterized in that, A (z)=(1+z
-2)
-1
21. invention as claimed in claim 18 is characterized in that, described delta sigma modulator characterizes with following noise transfer function:
Y(z)/X(z)＝A(z)(1+A(z)B(z))
-1
Wherein, the input signal of X (z) the described delta sigma modulator circuit of expression in the z territory.
22. invention as claimed in claim 17 is characterized in that, described delta sigma modulator has the exponent number greater than 2.
23. invention as claimed in claim 22 is characterized in that, described delta sigma modulator is the 6th rank delta sigma modulator.
24. invention as claimed in claim 23 is characterized in that, described delta sigma modulator comprises that gain is approximately 3/2 amplifier.
25. invention as claimed in claim 23 is characterized in that, described delta sigma modulator comprises that gain is approximately-3/4 amplifier.
26. invention as claimed in claim 23 is characterized in that, described delta sigma modulator comprises that gain is approximately 1/8 amplifier.
27. invention as claimed in claim 10 is characterized in that, described loop device comprises phase-locked loop.
28. the system of synthesis cycle signal is characterized in that under the arbitrary frequency in a plurality of frequencies, comprising:
Oscillator is used for producing the signal of first frequency;
The Direct Digital synthesizer is used for described conversion of signals is become digital signal;
The delta sigma modulator connects with the output that receives described Direct Digital synthesizer as the input of arriving it;
Low order digit-analogue converter is used for converting the output of described delta sigma modulator to analog signal;
Filter is used for reducing the noise in described analog signal and provides clearly reference signal in response to this; With
Phase-locked loop has described reference signal and is used to produce that frequency described in a plurality of frequencies as input.
29. a generation has the system of the periodic signal of characteristic frequency, it is characterized in that, comprising:
Oscillator is used for producing the reference signal with the frequency in special frequency band;
The noise shaping device is used for being suppressed in the described oscillator signal noise in described frequency band and provides noise setting signal in response to it;
Convertor device is used for the low noise analog signal of described noise setting conversion of signals one-tenth under preset frequency; With
Phase-locked loop is used for according to the described periodic signal of described analogue signal generating.
30. a generation has the system of the periodic signal of characteristic frequency, it is characterized in that, comprising:
The direct signal synthesizer;
The delta sigma digital-to-analog converter connects with the output that receives described synthesizer as the input of arriving it; With
Phase-locked loop is connected to the described output of described delta sigma digital-to-analog converter.
31. a method that is created in the accurate periodic signal under the preset frequency is characterized in that, comprises the following steps:
Generation has the digit period signal of the component under required reference frequency;
Be suppressed in the described periodic signal noise in the preset range of described required reference frequency and provide noise setting signal in response to it; With
Synthesize periodic signal under described characteristic frequency according to described noise setting signal.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10786898A | 1998-06-30 | 1998-06-30 | |
| US09/107,868 | 1998-06-30 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN1308789A true CN1308789A (en) | 2001-08-15 |
Family
ID=22318894
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 99808183 Pending CN1308789A (en) | 1998-06-30 | 1999-06-29 | System for generating an accurate low-noise periodic signal |
Country Status (7)
| Country | Link |
|---|---|
| EP (1) | EP1095458A1 (en) |
| JP (1) | JP2002519924A (en) |
| CN (1) | CN1308789A (en) |
| AU (1) | AU4726099A (en) |
| BR (1) | BR9911733A (en) |
| CA (1) | CA2336383A1 (en) |
| WO (1) | WO2000001072A1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108028659A (en) * | 2015-07-31 | 2018-05-11 | 舒尔获得控股公司 | Hybrid frequency synthesizer and method |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE10019487A1 (en) | 2000-04-19 | 2001-11-08 | Siemens Ag | Frequency synthesizer |
| US7130327B2 (en) | 2003-06-27 | 2006-10-31 | Northrop Grumman Corporation | Digital frequency synthesis |
| US7482885B2 (en) * | 2005-12-29 | 2009-01-27 | Orca Systems, Inc. | Method of frequency synthesis for fast switching |
| US7782017B2 (en) * | 2006-02-28 | 2010-08-24 | Linear Technology Corporation | Apparatus and method for producing signal conveying circuit status information |
| JP2010219756A (en) * | 2009-03-16 | 2010-09-30 | Canon Inc | Signal processor |
| JP2015128220A (en) | 2013-12-27 | 2015-07-09 | セイコーエプソン株式会社 | Oscillator circuit, oscillator, electronic apparatus, movable body and frequency adjustment method of oscillator |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4965533A (en) * | 1989-08-31 | 1990-10-23 | Qualcomm, Inc. | Direct digital synthesizer driven phase lock loop frequency synthesizer |
-
1999
- 1999-06-29 EP EP99930808A patent/EP1095458A1/en not_active Withdrawn
- 1999-06-29 BR BR9911733-9A patent/BR9911733A/en not_active Application Discontinuation
- 1999-06-29 WO PCT/US1999/014655 patent/WO2000001072A1/en not_active Application Discontinuation
- 1999-06-29 CA CA002336383A patent/CA2336383A1/en not_active Abandoned
- 1999-06-29 CN CN 99808183 patent/CN1308789A/en active Pending
- 1999-06-29 JP JP2000557550A patent/JP2002519924A/en active Pending
- 1999-06-29 AU AU47260/99A patent/AU4726099A/en not_active Abandoned
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108028659A (en) * | 2015-07-31 | 2018-05-11 | 舒尔获得控股公司 | Hybrid frequency synthesizer and method |
| CN108028659B (en) * | 2015-07-31 | 2021-09-14 | 舒尔获得控股公司 | Hybrid frequency synthesizer and method |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2002519924A (en) | 2002-07-02 |
| CA2336383A1 (en) | 2000-01-06 |
| BR9911733A (en) | 2001-04-03 |
| WO2000001072A1 (en) | 2000-01-06 |
| EP1095458A1 (en) | 2001-05-02 |
| AU4726099A (en) | 2000-01-17 |
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