CN1307781A - Synchronizing, switching, and editing MPEG files - Google Patents
Synchronizing, switching, and editing MPEG files Download PDFInfo
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- CN1307781A CN1307781A CN99804907A CN99804907A CN1307781A CN 1307781 A CN1307781 A CN 1307781A CN 99804907 A CN99804907 A CN 99804907A CN 99804907 A CN99804907 A CN 99804907A CN 1307781 A CN1307781 A CN 1307781A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B27/00—Editing; Indexing; Addressing; Timing or synchronising; Monitoring; Measuring tape travel
- G11B27/02—Editing, e.g. varying the order of information signals recorded on, or reproduced from, record carriers
- G11B27/031—Electronic editing of digitised analogue information signals, e.g. audio or video signals
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B27/00—Editing; Indexing; Addressing; Timing or synchronising; Monitoring; Measuring tape travel
- G11B27/10—Indexing; Addressing; Timing or synchronising; Measuring tape travel
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/20—Servers specifically adapted for the distribution of content, e.g. VOD servers; Operations thereof
- H04N21/23—Processing of content or additional data; Elementary server operations; Server middleware
- H04N21/238—Interfacing the downstream path of the transmission network, e.g. adapting the transmission rate of a video stream to network bandwidth; Processing of multiplex streams
- H04N21/2389—Multiplex stream processing, e.g. multiplex stream encrypting
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
- H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
- H04N21/4302—Content synchronisation processes, e.g. decoder synchronisation
- H04N21/4307—Synchronising the rendering of multiple content streams or additional data on devices, e.g. synchronisation of audio on a mobile phone with the video output on the TV screen
- H04N21/43072—Synchronising the rendering of multiple content streams or additional data on devices, e.g. synchronisation of audio on a mobile phone with the video output on the TV screen of multiple content streams on the same device
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- H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
- H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
- H04N21/432—Content retrieval operation from a local storage medium, e.g. hard-disk
- H04N21/4325—Content retrieval operation from a local storage medium, e.g. hard-disk by playing back content from the storage medium
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
- H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
- H04N21/438—Interfacing the downstream path of the transmission network originating from a server, e.g. retrieving encoded video stream packets from an IP network
- H04N21/4385—Multiplex stream processing, e.g. multiplex stream decrypting
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- H—ELECTRICITY
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- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
- H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
- H04N21/44—Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream or rendering scenes according to encoded video stream scene graphs
- H04N21/44016—Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream or rendering scenes according to encoded video stream scene graphs involving splicing one content stream with another content stream, e.g. for substituting a video clip
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Abstract
A method and apparatus for flexibly and reliably processing one or more MPEG signals from at least one source. The method provides for synchronizing (28) decoded streams (36) to a reference clock, for playing multiple streams simultaneously or for transitioning (24) between streams in a seamless manner. The output streams can have varying formats and can include both video and audio. The structure and method further provide for the capability of skipping B frames to reach a desired reference frame quickly and to edit the MPEG streams regardless of GOP size.
Description
The present invention relates generally to coding and the decoding and the operation of video and audio signal.Specifically, the present invention relates to be used for to encode neatly and the decode method and apparatus of multiple MPEG digital video and audio stream.Television industry requires to access high-quality, complete movable Voice ﹠ Video signal (different sources is generally arranged).The United States Patent (USP) 5 that is entitled as " LOOSELY COUPLED MASS STORAGECOMPUTER CLUSTER " (loosely-coupled big capacity storage computer cluster) of authorizing in application on October 24 nineteen ninety-five, on January 19th, 1999,862, in 312 (its disclosure is whole as a reference incorporated herein), even when disclosing the failure of one of a kind of node at above-mentioned bunch, also can be reliably and send the method and apparatus of media stream continuously.These streams generally store as the stream and/or the compressed audio stream of mpeg encoded.Importantly can between various streams, carry out seamless, switch continuously and reliably, so that high-quality Voice ﹠ Video signal with radio broadcasting quality to be provided.
Development along with technology it is also important that, can carry out between the different mpeg streams seamless switching decode with the stream that provides multiple stream and will transmit " rapidly " (on-the-fly) with output video or audio frequency in do not interrupt.
The present invention relates to a kind of method that is used for coming the mpeg signal behind the broadcast decoder in flexible and structurized mode.In one aspect, the present invention relates to receive the stream of encoding from a plurality of mpeg datas at least one source with high data rate, to the stream decoding that is received, and a plurality of decoded streams and reference clock are synchronous.
In another aspect of this invention, provide a kind of user of making to play the structure of a plurality of stream inputs simultaneously.A plurality of output streams can have various forms, and can comprise video and audio stream.
The present invention also provides the ability of the mpeg file that is right after other file thereafter of play any type, and this operation is seamless.The present invention also provides the ability of B frame with the desired reference frame of quick acquisition of skipping.In addition, the present invention can flow by editing MPEG the user, and no matter the size of GOP.This editor also can carry out for two or more situations for the GOP size.
Other advantage of the present invention and feature thereof will become apparent by the detailed description below in conjunction with accompanying drawing.Among the figure:
Fig. 1 is the allomeric function block diagram according to equipment of the present invention;
Fig. 2 is the more detailed block diagram according to controller of the present invention;
Fig. 3 is the more detailed block diagram of controller shown in Figure 2;
Fig. 4 is the block diagram according to interface switch of the present invention;
Fig. 5 is the more detailed block diagram of the interface switch of Fig. 4;
Fig. 6 is interface switch FPGA;
Fig. 7 is according to GENLOCK circuit of the present invention;
Fig. 8 schematically illustrates according to frequency plot detector circuit of the present invention;
Fig. 9 has illustrated the operation of GENLOCK method.
With reference to figure 1, decode system 8 of the present invention comprises a controller 10, and it includes CPU (CPU) 12, random access memory 14, pci interface 16 and mpeg decoder 20 and interface switch 24.Interface switch 24 has digital and analog interface 26, GENLOCK input 28, and Voice ﹠ Video switch 30, decoder is to the interface 32 and the Movie-2 bus interface 34 of decoder.
Decode system produces two independently changeable passages of analog or digital video from compression mpeg data that pci bus transmitted, and four changeable passages of analog or digital audio stereo (can obtain on circuit 36) independently.Pci bus can be worked under the mode of 33Mhz, 32 bit data bus structures (its shared PCT controller 42 (Fig. 2) is to the bus bandwidth between the main determinant).Each passage all has a mpeg decoder 20, by optional second decode system, can also use four (4) mpeg decoders 20, and each all provides two stereo audio passages and decompressed video passage.These decompression audio connect any analog or digital output 26 with Reprogrammable digital crosspoint switch 30 switchings of " rapidly ".
As mentioned above, two or more decode systems can be linked together to increase other passage and more powerful switching capability.When connecting two systems 8 according to the present invention, used " MS master-slave " structure, four analog/digital (a/d) videos and eight (a/d) stereo audio passages can switch to any output " rapidly " so altogether.The switching construction of this Reprogrammable typical case uses in broadcast environment " previewing programs " is very useful in using.This switching capability also can be used in the various editing application.
Except above-mentioned switching capability, decode system 8 also provides the interface from the signal of outer (off-the-shelf) video effect unit of frame.This realizes with Movie-2 bus 70 (with reference to figure 1).The Movie-2 bus be a kind of plate to the plate interconnect standard, it provides, and 27Mhz between linkage unit is time-multiplexed not to compress the multi-channel video exchange.According to CCIR601, SMPTE126M and EBU technical specification, the Movie-2 bus allows professional audio/video product to be connected to each other and to exchange the video of full resolution studio quality, and can not increase the burden of local cpu bus.The support of Movie-2 bus surpasses the continuous aggregate data rate of 300MBps (megabytes per second).
According to the foregoing description, use the Movie-2 bus allow decode system with video from and/or support unit of Movie-2 bus to send by other, or be sent to these unit.The Movie-2 signal switches with the cross point switches 30 of switch 24.This makes decoded M PEG output send on the Movie-2 bus and sends to from the Movie-2 bus on the numeral and simulation output 26 of system.In order to realize the maximum set of these features, as mentioned above, connect two decode systems by the MS master-slave bus, special functional unit will be connected with the main decoder system by Movie-2 bus 70 simultaneously.Like this, the decoded video from a plurality of passages can send and be connected to special effect unit (for example character generator, static memory, 2D and 3D effect/frequency mixer or the like) by Movie-2 bus 70.
This result can show before or after passing through switch 30, and can go back so that any resulting editing video is encoded by the mpeg encoder transmission.
With reference to figure 2, controller 10 is made up of following major function element: CPU12 and PCI control 42 are used for pci bus 111 to pci interface 16; RAM14; FPGA (field programmable gate array) control 84; FPGA unit 86; Two mpeg audio/Video Decoders 20; Audio/video-switch 87; Audio/video output 36; Periphery and system synchronization (Sync).These functional areas combine to produce two independently switchable passages on circuit 36, by the mpeg data output analog/digital audio and the vision signal that transmit by pci bus 111.Built-in CPU processor 12 (for example Intel 80960HA) control 20 high speed data transfer from RAM to the audio/video decoder.Under the control of FPGA84 logic, carry out high speed data delivery from the pci bus to RAM as this machine bus/pci bus main interface chip (for example PCI9080 of PCL Technology) of pci controller 42.This built-in processor is also carried out audio/video initialization and the mpeg video decode that helps each the audio/video decoder passage in output 36.Controller comprises dual serial port one 00,102, and the state LED on circuit 104, is used for external status/observation.External system 106 (external video input) synchronously provides the optional synchronous of all passages of system.
CPU and PCI element comprise that pci bus interface 16, built-in CPU12, CPU guide PLX121 and controller fpga logic 84.
System receives mpeg data by pci bus interface 42.Interface function between pci interface chip 110 control pci buss 111 and built-in this machine of the CPU bus 112.Pci interface 16 request cpu buss 112 (becoming this machine bus master) are to export to this machine RAM14 or from this machine RAM14 according to the burst mode Data transmission.
Built-in CPU processor 12 is used to control mpeg data and moves to the initialization of two audio/video decoder 20, audio/video decoder and the initialization and the management of system.
CPU12 and (interface 16) pci bus main interface chip 110 and dma bus master control 120 shared buss that are positioned at controller FPGA84.RAM control is carried out by controller FPGA84, and direct memory visit (DMA) and I/O control are also carried out by controller FPGA84.Sheet choosing, CPU start-up logic and FPGA programming Control are carried out by CPU guiding PLD121.
The flash memory 122 of boot partition (512K for example
*8) provide the setup code of CPU pilot operationp.Application code is downloaded to the part of RAM as initialization process.Main line (Mainline) CPU code is handled from RAM.Serial port 100,102 or pci interface 16 can be used to download new code to flash memory 122.FPGA structure, video quantizing table and other non-volatile structure data also are stored in the flash memory.
According to the present invention, decode system decompresses to two video channels and four stereo audio passages.Video can show with SIF, half D-1 or D-1 resolution under NTSC or pal mode.Audio frequency output can be monophony, two monophony, stereo or joint stereo (joint stereo).Mpeg decoder (for example, IBM MPEGCD21) is decoded to compressed source information material with one of following column format:
The streams of data elements (PES) of-MPEG grouping defines as ISO/IEC13818-1;
-MPEG-2 video data element stream, defined as ISO/13818-2;
-mpeg audio streams of data elements (PES), defined as ISO/IEC11172-3, layer I and II;
-MPEG video data element stream, defined as ISO/IEC11172-2;
-ISO/IEC11172-1 packet;
-support 4:2:2 chromium form, the 1PB data are up to 50Mb/s.
The MPEG packed data inputs to the internal processor of mpeg decoder chip by 84,86 (they have set up the serial I/O on bus 130, this bus 130 is one 16 bit data bus, is shared by asynchronous read and write) of FPGA.Position and display buffer can dynamically be adjusted size, and are arranged in the RAM 133 of mpeg decoder special use.RAM can constitute for example 4:2:0, D1; 4:2:2, D1; Or 4:2:2, full CCIR601 resolution.
In the above-described embodiments, audio/video decoder 20 has the work clock of a 27MHz, and it adopts the VCXO/ systematic synchronous circuit that is positioned at interface switch 24 to realize.The inside PLL circuit that the specific clock of Voice ﹠ Video passes through mpeg decoder produces.Audio frequency PCM clock and 256fs clock (256 times sample frequencys) are output the A/V cross point switches 30 to interface switch 24.VCXO/ system synchronization function is returned all mpeg decoders 20 and is produced vertical and horizontal-drive signal.
The software programming that audio level is regulated IC by the decay register of mpeg decoder and/or the programming audio level that is positioned at interface switch 24 is controlled.Control 10 more detailed block diagrams are shown in Fig. 3.
With reference to figure 4, interface switch 24 slave controllers 10 or receive decoded digital audio/video data from other decode system 10a and/or Movie-2 bus interface 34.Digital audio and video switch with the cross point switches array 30 of Reprogrammable.Audio/video signal can be from decoder on (1) plate, (2) another decode system, or (3) Movie-2 bus interface switches to: output circuit on (1) plate, (2) another decode system, or (3) Movie-2 bus interface.Output can be broadcasting-quality analogue audio frequency, AES/EBU digital audio, broadcasting-quality analog video and SMPTE serial D 1 (digital composition) video.Interface switch 24 also be provided for all video channels line lock GENLOCK and be used for the GENLOCK of the color locking of analog video passage.
The cross point switches 30 of Reprogrammable is used for constructing the connection of the audio/video output 36 of decoder 20 again.Each MPEG on circuit 36 separates device Voice ﹠ Video output (from main decoder or from decoder) can be connected to one of the simulation of interface switch and/or numeral output 26.This switching layout is provided for the Promgramming of whole broadcast industry and the function of preview.It also provides from subcard and receives and send the ability of signal to it, and receives and to its ability that sends signal from Movie-2 bus 70, and the ability of various aerial, online and off-line editing and effects also is provided.
Use above-mentioned structure, equipment of the present invention provides the ability of playing the mpeg file of any kind that is right after other file thereafter.Transition between file is seamless, and is combined with interface switch 24 by CPU12 built-in in the controller and to control.Specifically, first mpeg stream is stored in the CPU memory 14, and decodes with one of decoder 20.When playing this stream, second data flow is stored in the CPU memory 14, can be used for the decoding of other decoder 20 of controller 10.In the correct time, second stream begins to play by the action of cross point switches array 30.For example, this array is seamless and switch to second inlet flow continuously with first inlet flow on the circuit 36, thus to the output of analog/digital audio/video output 26 in transition seamlessly when first inlet flow switches to second inlet flow.
In addition, the flexibility of decoder 20 is enough to the form of processing variation.They not only can handle different pattern of the inputs, and multiple output format can be provided.As the example of this system flexibility, two decoders can be operated simultaneously to different inlet flows, and the output from each switch to crosspoint switching array 30 can be connected to correct outlet line 26 on the circuit 36.Transition when therefore, the invention provides a plurality of stream between the output of output, a stream and two stream.
As mentioned above, all inlet flows can be synchronous with identical reference clock, thereby utilize GENLOCK signal and circuit, can make them synchronous mutually.In addition, structure of the present invention can be used for making a stream by preview, and other stream is play as output, i.e. broadcasting.The stream of preview can directly point to the Movie-2 bus or point at being positioned at for example output that separates of the display monitor of studio.In this way, different video flowings can be examined, and exports known stream simultaneously and broadcasts.In these examples with reference to figure 1, adopted second decode system, and utilized best control element with the MS master-slave relational operation, can obtain greater flexibility.The Movie-2 bus functionality
Movie-2 bus 70 provides the passive rear interface 34 of standard, increases special feature with the output to decoder.Mixing, 2D video effect and linearity and alpha keying (keying) are several functions that can add.The Movie-2 bus is positioned on the interface switch, wherein utilizes cross point switches 30 and the FPGA (Field Programmable Gate Array) that is positioned at interface FPGA 241 to handle I/O.Interface EPLD
Interface EPLD 243 provides two YUV passages to the parallel D1 conversion of SMPTE-125 (for the data that send to D1 digital video transducer), video GENLOCK PLL control, video Hsync, Vsync and frame regularly, the audio pack of built-in SMPTE-125, LITC data input and output form and multiple hardwares control.Multiple hardwares control is communicated by letter with control 10 by serial I/O (SIO) bus 270.
Fig. 5 and Fig. 6 are the more detailed illustrative (interface switch FPGA) of interface switch.Video GENLOCK PLL control
With reference to figure 7, FPGA is used to provide the video GENLOCK control of VCXO 293 and external reference 284 on the plate.Inner VCXO locks with external video Hsync on frequency and phase place.If external clock reference does not exist, control voltage is set to the frequency of the intermediate range of VCXO.
System GENLOCK uses VCXO clock source 293, and FPGA and 12 bit digital are to simulation (D/A) transducer 290.All phase locking information are arranged in FPGA.D/A converter 290 each horizontal synchronizing cycle upgrade.D/A converter is approximately responding in the 16-32 microsecond by changing the analog control voltage that exports VCXO 293 on its via line 292.FPGA sets up the horizontal synchronization (Hout) (and all other video regularly) of an output according to the VCXO clock frequency.
The horizontal synchronization (Hout) of output is handled by two steps and is locked onto the horizontal synchronization of sending here (Hin).Each step uses Digital Logic to produce desired response.
At first, with reference to figure 9, can be with automatic detection external source (step 500) time, frequency detector 296 be measured Hin cycle (step 502) of a plurality of 27Mhz clock samplings.Regulate VCXO 293 then till the clock number of every row is correct (for NTSC is 1716, is 1728 for PAL) (step 504).
Second step of phase-locked processing is regulating frequency and the phase place (step 506) of aiming at Hout and Hin also.This be by at first with Hout and Hin (step 508) synchronously, then D/A 290 (step 510) is measured and regulated to the clock sampling of each detected phase difference.Adopt " seizures " (snap) algorithm with the realization minimum alignment time.This algorithm is based on phase-lock mode continuous or simulation.Because two signals are on phase place " slip " each other, phase-locked loop is attempted " pulling " or is regulated VCXO.When state that the VCXO frequency equates by Hout and Hin, the direction of " slip " will change.In Fig. 8, explain frequency/phase detector 296.
Continuous system goes up the frequency increment that equates by regulating VCXO with every circuit time and is similar to.In this way, the rate of change of frequency is linear.When the slope of frequency change is zero, just reach required frequency.When VCXO is conditioned, phase difference just will begin and return the threshold value of a setting in the short time.Locking frequency is the frequency mid point between the threshold frequency.(this is that slope is zero point.) this frequency is loaded in the D/A converter when next phase difference is zero, makes " seizure " effect reach desired frequency.
In addition, reduction of the present invention and other modification also are conspicuous for a person skilled in the art.
Claims (5)
1. the method for the mpeg signal behind the broadcast decoder comprises:
Receive stream with high data rate from a plurality of mpeg datas coding at least one source, to the stream decoding of described reception and
A plurality of decoded streams and reference clock are synchronous.
2. the method for the played in order first and second encoded MPEG files comprises:
Each mpeg file decoding that will show;
Seamlessly switch between first and second mpeg files, wherein said first and second mpeg files have different forms.
3. method of editing the encoded MPEG file comprises:
Decode described mpeg file and
Irrespectively edit described mpeg file with the GOP size.
4. the method for an editing MPEG coded file comprises:
Read the file of coding,
Skip the file that reads of selected B frame, they are not decoded; With
Only handle the non-B frame in next mpeg file.
5. the method for a processing and audio plays and vision signal comprises:
Obtain a plurality of video and audio signals, described vision signal and described audio signal have different forms and
Handle described different format signal and produce the stream of single form, this stream obtains from the video and audio signal of described different-format.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US8091698P | 1998-04-06 | 1998-04-06 | |
| US60/080,916 | 1998-04-06 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1307781A true CN1307781A (en) | 2001-08-08 |
| CN1184813C CN1184813C (en) | 2005-01-12 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB998049077A Expired - Fee Related CN1184813C (en) | 1998-04-06 | 1999-04-06 | Synchronizing, switching, and editing MPEG files |
Country Status (6)
| Country | Link |
|---|---|
| EP (1) | EP1078522A1 (en) |
| JP (1) | JP2003514404A (en) |
| CN (1) | CN1184813C (en) |
| CA (1) | CA2327620A1 (en) |
| IL (1) | IL138870A (en) |
| WO (1) | WO1999052283A1 (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN100531383C (en) * | 2006-05-23 | 2009-08-19 | 中国科学院声学研究所 | Hierarchical processing method of video frames in video playing |
| CN102185998A (en) * | 2010-12-31 | 2011-09-14 | 北京中科大洋科技发展股份有限公司 | A method for synchronizing video signals by employing AES/EBU digital audio signals |
| CN103843352A (en) * | 2011-08-30 | 2014-06-04 | 微软公司 | Techniques for dynamic switching between coded bitstreams |
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| US7068724B1 (en) | 1999-10-20 | 2006-06-27 | Prime Research Alliance E., Inc. | Method and apparatus for inserting digital media advertisements into statistical multiplexed streams |
| US6704930B1 (en) | 1999-04-20 | 2004-03-09 | Expanse Networks, Inc. | Advertisement insertion techniques for digital video streams |
| US20040148625A1 (en) | 2000-04-20 | 2004-07-29 | Eldering Charles A | Advertisement management system for digital video streams |
| US6753925B2 (en) * | 2001-03-30 | 2004-06-22 | Tektronix, Inc. | Audio/video processing engine |
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| JPS63252080A (en) * | 1987-04-08 | 1988-10-19 | Pioneer Electronic Corp | Video signal output device |
| JP3161614B2 (en) * | 1991-11-30 | 2001-04-25 | ソニー株式会社 | Video decoding device |
| JP3264290B2 (en) * | 1992-09-22 | 2002-03-11 | ソニー株式会社 | Decoding method and decoding device |
| US5299855A (en) * | 1992-11-25 | 1994-04-05 | Zubeck Michael J | Child seat restraint apparatus |
| KR0178819B1 (en) * | 1993-03-16 | 1999-05-01 | 보조 다꾸로 | Method for jump-reproducing video data of moving picture coded with high efficiency |
| US5325131A (en) * | 1993-05-03 | 1994-06-28 | Tektronix, Inc. | Multiformat television switcher |
| JPH07212766A (en) * | 1994-01-18 | 1995-08-11 | Matsushita Electric Ind Co Ltd | Moving picture compression data changeover circuit |
| US5635979A (en) * | 1994-05-27 | 1997-06-03 | Bell Atlantic | Dynamically programmable digital entertainment terminal using downloaded software to control broadband data operations |
-
1999
- 1999-04-06 CN CNB998049077A patent/CN1184813C/en not_active Expired - Fee Related
- 1999-04-06 EP EP99917346A patent/EP1078522A1/en not_active Withdrawn
- 1999-04-06 CA CA002327620A patent/CA2327620A1/en not_active Abandoned
- 1999-04-06 WO PCT/US1999/007507 patent/WO1999052283A1/en not_active Application Discontinuation
- 1999-04-06 IL IL13887099A patent/IL138870A/en not_active IP Right Cessation
- 1999-04-06 JP JP2000542917A patent/JP2003514404A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100531383C (en) * | 2006-05-23 | 2009-08-19 | 中国科学院声学研究所 | Hierarchical processing method of video frames in video playing |
| CN102185998A (en) * | 2010-12-31 | 2011-09-14 | 北京中科大洋科技发展股份有限公司 | A method for synchronizing video signals by employing AES/EBU digital audio signals |
| CN102185998B (en) * | 2010-12-31 | 2013-05-22 | 北京中科大洋科技发展股份有限公司 | A method for synchronizing video signals by employing AES/EBU digital audio signals |
| CN103843352A (en) * | 2011-08-30 | 2014-06-04 | 微软公司 | Techniques for dynamic switching between coded bitstreams |
Also Published As
| Publication number | Publication date |
|---|---|
| WO1999052283A1 (en) | 1999-10-14 |
| IL138870A (en) | 2005-08-31 |
| EP1078522A1 (en) | 2001-02-28 |
| CA2327620A1 (en) | 1999-10-14 |
| CN1184813C (en) | 2005-01-12 |
| IL138870A0 (en) | 2001-11-25 |
| JP2003514404A (en) | 2003-04-15 |
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