CN1302377C - Memory program patching and expanding method for digital signal processor - Google Patents
Memory program patching and expanding method for digital signal processor Download PDFInfo
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- CN1302377C CN1302377C CNB2003101023286A CN200310102328A CN1302377C CN 1302377 C CN1302377 C CN 1302377C CN B2003101023286 A CNB2003101023286 A CN B2003101023286A CN 200310102328 A CN200310102328 A CN 200310102328A CN 1302377 C CN1302377 C CN 1302377C
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Abstract
The present invention relates to a method for patching and expanding a storage program of a digital signal processor so that a read-only storage for storing main programs in the digital signal processor (DSP) is connected with a static access storage with small capacity and at least one temporary storage. A segment of newly added or patched program codes are arranged at the point of the static access storage. Mutually corresponding addresses are set for the read-only storage, the static access storage and the temporary storage by the method of the present invention so that an address pointing path is formed. Wrong program codes can be skipped over by the address redirecting function of the temporary storage by the digital signal processor, and the static access storage can also be pointed so as to read the newly added program codes. The effect of simply and conveniently achieving DSP program patch or expansion is provided.
Description
Technical field
The present invention is that a kind of memory program of digital signal processor is repaired and extending method, refers to that especially a kind of internal processes that can't change digital signal processor provides an easy repairing and the method for expansion.
Background technology
Along with the arriving of IT, IA Age of Technology, the application of embedded dsp is got over to become to popularizing and is reached extensively at present.
The program that contains in the digital signal processor is with pending computing or control relevant peripheral circuit.General digital signal processor stored routine can be divided into following several means:
1, with the design of ROM (read-only memory) (ROM) as the internal program memory that cooperates the digital signal processor arithmetic element.
Because ROM (read-only memory) can't be rewritten again and be stored data, and therefore, in case adopt the digital signal processor program of this program storage to write in the ROM (read-only memory), can not change again.Therefore, program wrong (BUG) can't be revised in the future, also can't increase program newly.
2, replace the internal storage of aforementioned ROM (read-only memory) (ROM) with static RAM (SRAM) as digital signal processor.
Because this static RAM has and overrides (repetitive read-write) function, when electric power starting, this random access memory sign indicating number that can download from the outside enters.So when routine change, only need download the distinct program sign indicating number and can elasticity change or the repairing internal processes, so have better selectivity and extendability compared to ROM (read-only memory).
But use the digital signal processor of this framework, replace ROM (read-only memory) with SRAM (Static Random Access Memory), outside not only price significantly increases, and the shared chip area of SRAM (Static Random Access Memory) also far surpasses ROM, cause taking the layout area of more than half digital signal processor wafer, be not inconsistent the principle of economy and miniaturization.
3, with flash memory (FLASH MEMORY) as framework as the internal storage of digital signal processor.
The area of read-write characteristic of flash utensil and physical layout circuit is a compromise proposal less than SRAM in fact.Yet the processing procedure of flash memory is comparatively complicated, and price is higher, also non-optimal scheme.
Based on aforementioned reason, product for maturation is partial to first kind of digital signal processor that price is the cheapest of employing, but, in case program makes a mistake when producing, can't revise program at all, only can solve by digital signal processor (DSP) beginning of changing redaction, if the SRAM that use cost is high or the digital signal processor (DSP) of FLASH pattern, then more competitiveless, how under low-cost situation, have the function of repairing and expanding program content concurrently, be the target that industry is made joint efforts.
Summary of the invention
Fundamental purpose of the present invention provides a kind of memory program of digital signal processor and repairs and extending method, do not changing under the condition of use ROM (read-only memory) as internal program memory, only increase the random access memory of little part and little cost, make digital signal processor have the function of error correction and program expansion.
The memory program of digital signal processor provided by the invention is repaired and extending method, comprising:
Make the SRAM (Static Random Access Memory) and at least one working storage that are connected with a low capacity in the digital signal processor in order to the ROM (read-only memory) that stores master routine;
The procedure code that writes repairing or increase newly is in SRAM (Static Random Access Memory);
The address, source of setting working storage is the address that the ROM (read-only memory) desire is heavily led, and destination address then is set at the address of ROM (read-only memory) or SRAM (Static Random Access Memory);
Carry out the procedure code of master routine in regular turn;
When the address of carrying out present master routine procedure code when identical with this address, working storage source, the corresponding destination address of working storage procedure code address pointed is jumped in the address that makes master routine carry out at present, to carry out this procedure code, because the pairing procedure code of destination address is stored another section procedure code of ROM (read-only memory) or the procedure code of SRAM (Static Random Access Memory), so can be the term of execution of the script master routine, point to origin source address and the required procedure code that skips over or carry out of destination address appointment by described address, and then master routine is repaired or expansion.
According to said method of the present invention, include a working storage, be set with an address, source and a destination address; This address, source and destination address are set at the wherein initial and end point of one section program of ROM (read-only memory) master routine respectively.
According to said method of the present invention, include a working storage, be set with an address, source and a destination address; This address, source is set at a particular address of ROM (read-only memory) master routine, this destination address then is set in the SRAM (Static Random Access Memory) to be repaired or the start address of newly-increased program, wherein, this repairing or newly-increased EOP (end of program) address are provided with the instruction of returning the master routine particular address;
When this digital signal processor is carried out master routine, can temporaryly think highly of the program address of leading or calling out SRAM (Static Random Access Memory) by this, return master routine with executive routine after the newly-increased or program patch operation.
According to said method of the present invention, include a working storage, be set with two groups of addresses, source and destination address;
Wherein one group of source address and destination address are set at wherein one section initial and end point of program of ROM (read-only memory) master routine respectively;
Another address, group source is set at a particular address of ROM (read-only memory) master routine, this destination address then is set in the SRAM (Static Random Access Memory) to be repaired or the start address of newly-increased program, wherein, this repairing or newly-increased EOP (end of program) address are provided with the instruction of returning the master routine particular address;
When this digital signal processor is carried out master routine, can temporaryly think highly of the program address of leading or calling out SRAM (Static Random Access Memory) by this, return master routine with executive routine after the newly-increased or program patch operation.
According to said method of the present invention, include two working storages, be set with an address, source and a destination address respectively;
Wherein the address, source of a working storage and destination address are set at wherein one section initial and end point of program of ROM (read-only memory) master routine respectively;
The address, source of another working storage is set at a particular address of ROM (read-only memory) master routine, its destination address then is set in the SRAM (Static Random Access Memory) to be repaired or the start address of newly-increased program, wherein, this repairing or newly-increased EOP (end of program) address are provided with the instruction of returning the master routine particular address;
When this digital signal processor is carried out master routine, can temporaryly think highly of the program address of leading or calling out SRAM (Static Random Access Memory) by this, return master routine with executive routine after the newly-increased or program patch operation.
According to said method of the present invention, described two working storages are respectively equipped with an activation end, whether control its activation for external control signal.
According to said method of the present invention, the relative ROM (read-only memory) of the capacity of this SRAM (Static Random Access Memory) is less.
In sum, the ROM (read-only memory) in the digital signal processor of the present invention (stored routine with) is connected with SRAM (Static Random Access Memory) and at least one working storage of a low capacity with address bus; The path is pointed in the address that ROM (read-only memory), SRAM (Static Random Access Memory) and working storage is set with mapping, and optionally a shed repair is mended or newly-increased procedure code to writing in the SRAM (Static Random Access Memory); So, this digital signal processor can heavily be led effect by the address of working storage, reads interior Hotfix of SRAM (Static Random Access Memory) or newly-increased program in good time, reaches the purpose of correction or newly-increased internal processes sign indicating number.
Because the inventive method only needs the erroneous procedures sign indicating number is skipped and carried out the content of revised procedure code or newly-increased program, so only need increase the SRAM (Static Random Access Memory) of minimum capacity gets final product to digital signal processor, digital signal processor compared to aforementioned whole use SRAM (Static Random Access Memory) or flash memory enforcement, tool benefit cheaply not only, more having use elasticity concurrently, is the program patch of a suitable tool intention and the method for expansion.
Description of drawings
Fig. 1 is an application state synoptic diagram of the present invention.
Fig. 2 is a method flow diagram of the present invention.
Fig. 3 is that the path synoptic diagram is pointed in an address of the present invention.
Embodiment
At first see also shown in Figure 1ly, the first preferred embodiment Organization Chart for digital signal processor of the present invention except that control module 10, ALU 20 and ROM (read-only memory) 30, further includes:
At least one group of working storage 40 is connected to this ROM (read-only memory) 30 with address bus, and each working storage is set with address 41, source and destination address 42; And
One SRAM (Static Random Access Memory) 60 is connected to this ROM (read-only memory) 30 and working storage 40 with address bus, and the relative ROM (read-only memory) 30 of the capacity of this SRAM (Static Random Access Memory) 60 is less.
See also shown in Figure 2ly, be the method for repairing of the present invention or extended memory program, be applied in the aforementioned digital processing unit framework, it includes following steps:
Step S1: write repair or newly-increased program in SRAM (Static Random Access Memory) 60;
Step S2: the address, source of setting working storage 40 is the address that ROM (read-only memory) 30 desires are heavily led, and destination address then is set in the address of ROM (read-only memory) 30 or SRAM (Static Random Access Memory) 60.
According to above-mentioned steps, the present invention has the processing capacity of following three kinds of master routine debugs and repairing/newly-increased program at least:
1, master routine debug/error eliminating function:
At first set the section start (be starting point that address heavily lead) of the address, source 41 of working storage 40 for erroneous procedures in ROM (read-only memory) 30 master routines, working storage destination address 42 then is set at the end of this erroneous procedures sign indicating number.
So, master routine can directly heavily be led the end of erroneous procedures with the address by working storage 40 before carrying out erroneous procedures, make this core dumped program not be performed.And common engineering teacher can utilize preceding method, and specific one section or several sections programs of master routine is independent and do not carry out, and uses the inspection that reaches the master routine debug.
2, newly-increased program function:
Set the address (be starting point that address heavily lead) of address 41, source for the desire setting point of interruption in ROM (read-only memory) 30 master routines in working storage 40, the destination address 42 of working storage 40 then is set at the actual address of SRAM (Static Random Access Memory) 60.Wherein the newly-increased program FA final address content of this SRAM (Static Random Access Memory) 60 is to return the instruction of master routine particular address.
So, when master routine is carried out to the point of interruption, can read in the storer 60 by the address, source 41 and the destination address 42 sensing static state of working storage 40, read repairing or newly-increased program in the storer 60 to carry out static state, and execute back rebound master routine in program, carry out master routine other section program or end to continue.
3, repair the master routine function:
At first in working storage 40, set two groups of addresses 41,51, source and destination address 42,52, wherein address 41, a source is set at the erroneous procedures sign indicating number section start (being the starting point that heavily lead the address) of ROM (read-only memory) 30 master routines, cooperates the order address 42 of this address, source then to be set at master routine erroneous procedures sign indicating number end; Another address 51, group source is set at the address (starting point that heavily lead another address) that the master routine desire is set the point of interruption, cooperate this destination address 52 of originating address 51 then to be set at the Hotfix starting point of SRAM (Static Random Access Memory) 60, equally, the last address of finishing of this Hotfix is provided with the instruction of returning other section of master routine program.So, the slip-stick artist can be with the erroneous procedures of checking out, by aforementioned manner erroneous procedures is skipped and is not carried out, and replace it with a Hotfix, so, can reach the purpose of revising master routine.
By aforementioned three kinds of modes as can be known, the present invention makes that by the address, source and the destination address of at least one group of corresponding main program address/SRAM (Static Random Access Memory) of working storage internal memory the master routine that is stored in the ROM (read-only memory) can be by debug, debug, correction and expansion.
Aforementioned three kinds of functions can and be stored in the same digital signal processor.If only want the term of execution of master routine, control is not when wherein one section or several sections programs are performed, then a group of pointing to ROM (read-only memory) and SRAM (Static Random Access Memory) can be originated address 51 and destination address 52 is set in another working storage 50, as shown in Figure 3, this working storage is provided with the activation end, need via after the external control activation, master routine could heavily be led in the SRAM (Static Random Access Memory) 60.
Below lift an actual debug and newly-increased program process description it, please cooperate shown in Figure 3, point to the path synoptic diagram for the address of aforementioned ROM (read-only memory) (memory space is 0X0000-0X3EFF) 30,60 and two first, second working storages 40,50 of SRAM (Static Random Access Memory) (0X3F00-0X3FFF), the address of phase mapping arranged between ROM (read-only memory), SRAM (Static Random Access Memory) and working storage:
The debug flow process at first is described: the content of the source working storage 41 of first working storage 40 is made as address 0X1215, and setting destination address working storage 42 is address 0X12C0, so, this master routine can skip the position between the 0X1215 to 0X12C0 of ROM (read-only memory) 30 program and do not carry out, use the origination point of the problem of detecting and the program segment that skips over the generation problem is provided, so that repair or correcting process, even carry out the extended function of procedure code by follow-up revision program sign indicating number (appearance aftermentioned).
When desire correction or expanding program sign indicating number, in this example for utilizing second working storage 50, the address register 51 of wherein originating is made as address 0X21AB, and destination address working storage 52 then is made as the address 0X3F55 (repairing or newly-increased procedure code section start) that corresponds to SRAM (Static Random Access Memory) 60.When master routine begins to carry out and second working storage 50 when being enabled, when master routine is carried out to 0X21AB, promptly point to the start address 0X3F55 of the newly-increased program of SRAM (Static Random Access Memory) by destination address working storage 52, and direct calling is stored in the repairing of SRAM (Static Random Access Memory) 60 or newly-increased procedure code, after EOP (end of program), return (the storage address ending is provided with link order), because this link order promptly automatically returns to a time address 0X21AC of master routine, and continues to carry out master routine.
From the above, when master routine is written into ROM (read-only memory),, can sets the point of interruption or skip certain program segment, and can heavily be directed at the SRAM (Static Random Access Memory) place, carry out program patch or expansion by SRAM (Static Random Access Memory) by the simple setting of working storage.
The present invention is not changing under the existing framework of digital signal processor, the SRAM (Static Random Access Memory) that only adds little memory capacity, increase under the minimum situation in cost, give the function that digital signal processor has procedure code correction and expansion, and the function of carrying out debug on the line, therefore, the present invention has usability, novelty and the progressive on the industry really.
Claims (7)
1, a kind of memory program of digital signal processor is repaired and extending method, comprising:
Make the SRAM (Static Random Access Memory) and at least one working storage that are connected with a low capacity in the digital signal processor in order to the ROM (read-only memory) that stores master routine;
The procedure code that writes repairing or increase newly is in SRAM (Static Random Access Memory);
The address, source of setting working storage is the address that the ROM (read-only memory) desire is heavily led, and destination address then is set at the address of ROM (read-only memory) or SRAM (Static Random Access Memory);
Carry out the procedure code of master routine in regular turn;
When the address of carrying out present master routine procedure code when identical with this address, working storage source, the corresponding destination address of working storage procedure code address pointed is jumped in the address that makes master routine carry out at present, to carry out this procedure code, because the pairing procedure code of destination address is stored another section procedure code of ROM (read-only memory) or the procedure code of SRAM (Static Random Access Memory), so can be the term of execution of the script master routine, point to origin source address and the required procedure code that skips over or carry out of destination address appointment by described address, and then master routine is repaired or expansion.
2, the memory program of digital signal processor as claimed in claim 1 is repaired and extending method, it is characterized in that: include a working storage, be set with an address, source and a destination address; This address, source and destination address are set at the wherein initial and end point of one section program of ROM (read-only memory) master routine respectively.
3, the memory program of digital signal processor as claimed in claim 1 or 2 is repaired and extending method, it is characterized in that: include a working storage, be set with an address, source and a destination address; This address, source is set at a particular address of ROM (read-only memory) master routine, this destination address then is set in the SRAM (Static Random Access Memory) to be repaired or the start address of newly-increased program, wherein, this repairing or newly-increased EOP (end of program) address are provided with the instruction of returning the master routine particular address;
When this digital signal processor is carried out master routine, can temporaryly think highly of the program address of leading or calling out SRAM (Static Random Access Memory) by this, return master routine with executive routine after the newly-increased or program patch operation.
4, the memory program of digital signal processor as claimed in claim 1 is repaired and extending method, it is characterized in that: include a working storage, be set with two groups of addresses, source and destination address;
Wherein one group of source address and destination address are set at wherein one section initial and end point of program of ROM (read-only memory) master routine respectively;
Another address, group source is set at a particular address of ROM (read-only memory) master routine, this destination address then is set in the SRAM (Static Random Access Memory) to be repaired or the start address of newly-increased program, wherein, this repairing or newly-increased EOP (end of program) address are provided with the instruction of returning the master routine particular address;
When this digital signal processor is carried out master routine, can temporaryly think highly of the program address of leading or calling out SRAM (Static Random Access Memory) by this, return master routine with executive routine after the newly-increased or program patch operation.
5, the memory program of digital signal processor as claimed in claim 1 is repaired and extending method, it is characterized in that: include two working storages, be set with an address, source and a destination address respectively;
Wherein the address, source of a working storage and destination address are set at wherein one section initial and end point of program of ROM (read-only memory) master routine respectively;
The address, source of another working storage is set at a particular address of ROM (read-only memory) master routine, its destination address then is set in the SRAM (Static Random Access Memory) to be repaired or the start address of newly-increased program, wherein, this repairing or newly-increased EOP (end of program) address are provided with the instruction of returning the master routine particular address;
When this digital signal processor is carried out master routine, can temporaryly think highly of the program address of leading or calling out SRAM (Static Random Access Memory) by this, return master routine with executive routine after the newly-increased or program patch operation.
6, the memory program of digital signal processor as claimed in claim 5 is repaired and extending method, and it is characterized in that: two working storages are respectively equipped with an activation end, whether controls its activation for external control signal.
7, the memory program of digital signal processor as claimed in claim 1 is repaired and extending method, and it is characterized in that: the relative ROM (read-only memory) of the capacity of this SRAM (Static Random Access Memory) is less.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2003101023286A CN1302377C (en) | 2003-10-24 | 2003-10-24 | Memory program patching and expanding method for digital signal processor |
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| Application Number | Priority Date | Filing Date | Title |
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| CNB2003101023286A CN1302377C (en) | 2003-10-24 | 2003-10-24 | Memory program patching and expanding method for digital signal processor |
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| Publication Number | Publication Date |
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| CN1609786A CN1609786A (en) | 2005-04-27 |
| CN1302377C true CN1302377C (en) | 2007-02-28 |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5677859A (en) * | 1994-02-02 | 1997-10-14 | Kabushiki Kaisha Toshiba | Central processing unit and an arithmetic operation processing unit |
| JP2001056758A (en) * | 1999-08-19 | 2001-02-27 | Sharp Corp | Information equipment and recording medium recording module updating program |
| CN1395173A (en) * | 2001-07-06 | 2003-02-05 | 宏碁股份有限公司 | Test system for information equipment and test method |
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- 2003-10-24 CN CNB2003101023286A patent/CN1302377C/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5677859A (en) * | 1994-02-02 | 1997-10-14 | Kabushiki Kaisha Toshiba | Central processing unit and an arithmetic operation processing unit |
| JP2001056758A (en) * | 1999-08-19 | 2001-02-27 | Sharp Corp | Information equipment and recording medium recording module updating program |
| CN1395173A (en) * | 2001-07-06 | 2003-02-05 | 宏碁股份有限公司 | Test system for information equipment and test method |
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| CN1609786A (en) | 2005-04-27 |
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