CN1300984A

CN1300984A - Interface method between microprocessor and CAN controller

Info

Publication number: CN1300984A
Application number: CN 01103932
Authority: CN
Inventors: 肖海华; 张忠理; 刘建飞
Original assignee: HADEWEI SIFANG PROTECTION AND CONTROL EQUIPMENT CO Ltd BEIJING
Current assignee: Electric Power Research Institute of State Grid Zhejiang Electric Power Co Ltd
Priority date: 2001-02-15
Filing date: 2001-02-15
Publication date: 2001-06-27
Anticipated expiration: 2021-02-15
Also published as: CN1120423C

Abstract

An interface method between microprocessor and CAN controller features that the P2.7 of microprocessor M37733 is used as chip selection signal of SJA1000, the addresses P2.0-P2.7 of CPU are sequentially connected to D0-D7 of SJA1000. The R, W and ALE signals are sequentially connected. The P2.7 is connected via on NAND gate to CS of SJA1000, and the P2.0-P2.6 are set as address signals for addressing the built-in memory of SJA1000. Its advantages are simple structure and programming, high transmission speed, and use of less I/O ports.

Description

The interface method of microprocessor and CAN controller

The present invention relates to the chip interface technical field, relate to the interface method of microprocessor and CAN controller particularly.

CAN net (CONTROLLER AREA NETWORK) is a kind of novel serial fieldbus, the flexible configuration of this bus, support a plurality of main websites, there is nondestructive bus arbitration scheme based on right of priority in each main website according to the right of priority access bus, and transmission speed is the fastest to reach 1MBIT/S, fault freedom is good, antijamming capability is strong, is well suited for industrial control field, is a kind of up-and-coming fieldbus.SJA1000 is the CAN controller that PHILIP company produces, and this controller is supported the CAN2.0B agreement, very strong packet filtering function is arranged, control is flexible, well selects when being expansion CAN network.

7700 series microprocessors (CPU) are 16 high-performance single-chip microcomputers that MIT produces, this serial CPU contains rich in natural resources, timer/counter is arranged, A/D converter, contain ram in slice and EPROM (FLASH), I/O mouth line is many, and processing speed is fast, when selecting the 24MHZ crystal oscillator for use, the short instruction execution time is 166ns.Having many uses of industrial control field.

Therefore, the simple and effective interface that designs between these two kinds of chips has very realistic meanings.

The interface signal of SJA1000 and CPU mainly contains: totally 8 of time-multiplexed address/data lines, address latch signal line, read-write control line, chip selection signal line.7700 serial CPU (is example with M37733) have 24 address wires, and wherein the address wire of most-significant byte can time division multiplex be a data line.Just because of M37733 is a most-significant byte address wire time division multiplex,, can not link to each other with bus so it has been generally acknowledged that them so when linking to each other with bus, be difficult to constitute correct chip selection signal with SJA1000.

Modal connected mode is the I/O mouth with CPU, this mode is actually with I/O mouth emulation bus, principle of work is as follows: as CPU during from certain storer reading of SJA1000, produce chip selection signal, gating SJA1000 earlier, CPU is changed to the way of output to the P7 mouth, the address of output storage produces the ALE of an address latch signal to SJA1000, and changing the P7 mouth then is input mode, produce an effective read signal, at this moment the P7 mouth is exactly needed numerical value.It is also roughly the same to write several processes in the SJA1000, and from as can be seen above, once simple read-write operation deals with very complicated.In fact, this is also very time-consuming, test amount factually, and the time of writing a byte approximately is 16us, the time of writing a frame message like this is 0.17ms.If the communication speed of CAN is set as 1MBIT/S, a frame message transmission time on the net approximately is 0.11ms.

Can see that thus there is following shortcoming in traditional interface mode: 1. the time ratio of writing a frame message passes the time of a frame message and also will grow, so that the interface between CPU and the CAN controller become the bottleneck of communication, serious reduction the speed of communication.Handle communication 2.CPU take much time, be subjected to very big restriction in this application mode of the demanding occasion of ask for something real-time like this.3. this interface mode has taken a large amount of I/O mouth of cpu chip, is unfavorable for further expanding of system.

The purpose of this invention is to provide simple and reliable interface method between a kind of microprocessor and the CAN controller, make these two kinds of chips can both bring into play separately advantage, make the work of the least possible processing communication of CPU, the fast advantage of CAN transmission speed can be fully played as far as possible.

Technical scheme of the present invention is to realize like this, by further investigation to SJA1000, the address realm of finding the SJA1000 storer is 00-7FH, and the highest addresses line is invalid, that is to say concerning SJA1000,00H and 80H represent the address of same storer, and the like, n and n+80H represent the address of same storer.According to this thinking, we can come addressing SJA1000 by P2.7 (most significant digit of time-multiplexed address, data line), promptly P2.7 are arranged to chip selection signal, and P2.0-P2.6 is arranged to the on-chip memory of address signal in order to addressing SJA1000.So the specific address of No. 00 storer of SJA1000 is 80 * * * * H (* expression can be any numerical value), the specific address of No. 01 storer of SJA1000 is 81 * * * * H, the address of last storer of SJA1000 be OFF * * * * H.

A kind of microprocessor M37733 chip and a slice CAN controller SJA1000 method of attachment are: use the chip selection signal of the P2.7 (most significant digit of time-multiplexed address, data line) of microprocessor M37733 chip as SJA1000, CPU ground P2.0-P2.7 is received successively the D0-D7 of SJA1000, connected simultaneously read signal R successively, write signal W, address latch signal ALE; P2.7 is connected with the CS of SJA1000 through a not gate, and the specific address of No. 00 storer of SJA1000 is 80 * * * * H (* expression can be any numerical value), the address of the 10H storage unit of SJA1000 is 90 * * * * H; During from No. 00 storer reading of SJA1000, with an instruction LDA A, 80 * * * * H is just passable; When counting toward the 10H memory write of SJA1000, with instruction STA A, 90 * * * * H.

7700 serial CPU are when being used for the memory expansion mode, and maximum addressing range is OFFFFFFH, so above-mentioned address is still in the addressable scope of CPU.

In this way, can change a little and just be used in the occasion with a plurality of CAN nets, in use, the part address wire of P2.7 and P0 or P1 mouth be formed chip selection signal through logical combination get final product with a CPU.

The advantage of interface method of the present invention is that interface is simple, it is simple and convenient to programme, and CPU is freed from the task of heavy intervention communication, can give full play to the fast advantage of CAN transmission speed, save a large amount of I/O mouths, be easily extended to the occasion of controlling a plurality of CAN controllers with a cpu chip.

Below in conjunction with accompanying drawing the specific embodiment of the present invention is described in further detail.

Fig. 1 is the synoptic diagram of the interface method of prior art;

Fig. 2 is the synoptic diagram of interface method of the present invention;

Fig. 3 is the synoptic diagram of the interface method of an alternative embodiment of the invention.

Fig. 1 is the synoptic diagram of the interface method of prior art.Modal connected mode is the I/O mouth with CPU.This mode is actually with I/O mouth emulation bus, principle of work is as follows: as CPU during from certain storer reading of SJA1000, produce chip selection signal earlier, gating SJA1000, CPU is changed to the way of output to the P7 mouth, the address of output storage, produce the ALE of an address latch signal to SJA1000, changing the P7 mouth then is input mode, produces an effective read signal, and at this moment the P7 mouth is exactly needed numerical value.It is also roughly the same to write several processes in the SJA1000, and from as can be seen above, once simple read-write operation deals with very complicated.In fact, this is also very time-consuming, test amount factually, and the time of writing a byte approximately is 16us, the time of writing a frame message like this is 0.17ms.If the communication speed of CAN is set as 1MBIT/S, a frame message transmission time on the net approximately is 0.11ms.

Fig. 2 is the synoptic diagram of interface method of the present invention; The interface instance of 7700 serial CPU and CAN controller SJA1000 is listed below, and CPU is example with M37733.M37733 chip and a slice SJA1000 method of attachment are: with the chip selection signal of P2.7 (most significant digit of time-multiplexed address, data line) as SJA1000, CPU ground P2.0-P2.7 is received successively the D0-D7 of SJA1000, connected simultaneously read signal R successively, write signal W, address latch signal ALE; The specific address of No. 00 storer of SJA1000 is 80 * * * * H (* expression can be any numerical value), the address of the 10H storage unit of SJA1000 is 90 * * * * H; During from No. 00 storer reading of SJA1000, with an instruction LDA A, 80 * * * * H is just passable; When counting toward the 10H memory write of SJA1000, with instruction STA A, 90 * * * * H.

Fig. 3 is the synoptic diagram of the interface method of an alternative embodiment of the invention.When needs are controlled two CAN controllers with a cpu chip, on the basis of Fig. 2, revise getting final product a little, as shown in Figure 3, the chip selection signal of first SJA1000 gets address wire P2.7 by CPU and P1.7 produces jointly.So the address of No. 00 storer of first SJA1000 is 808 * * * H, the address of No. 01 storer is 818 * * * H; The chip selection signal of second SJA1000 gets address wire P2.7 by CPU and P1.6 produces jointly, so the address of No. 00 storer of second SJA1000 is 804 * * * H, the address of No. 01 storer is 814 * * * H, the address of other storer can and the like.With this connected mode, CPU just can realize with an instruction the read-write operation of SJA1000 internal storage.

When needs when controlling a plurality of CAN controller with a cpu chip, interface and addressing method are basic identical.

Claims

1. microprocessor M37733 chip and CAN controller SJA1000 method of attachment, it is characterized in that: use the chip selection signal of the P2.7 (most significant digit of time-multiplexed address, data line) of microprocessor M37733 chip as SJA1000, CPU ground P2.0-P2.7 is received successively the D0-D7 of SJA1000, connected simultaneously read signal R successively, write signal W, address latch signal ALE; P2.7 is connected with the CS of SJA1000 through a not gate, and the specific address of No. 00 storer of SJA1000 is 80 * * * * H (* expression can be any numerical value), the address of the 10H storage unit of SJA1000 is 90 * * * * H; During from No. 00 storer reading of SJA1000, with an instruction LDA A, 80 * * * * H is just passable; When counting toward the 10H memory write of SJA1000, with instruction STA A, 90 * * * * H.

2. according to the method for claim 1, it is characterized in that: described 7700 serial CPU are when being used for the memory expansion mode, and maximum addressing range is OFFFFFFH, so above-mentioned address is still in the addressable scope of CPU.

3. according to the method for claim 2, it is characterized in that: described 7700 serial CPU form chip selection signal to the part address wire of P2.7 and P0 or P1 mouth through logical combination and get final product during with the occasion of a plurality of CAN net.