CN1298055C

CN1298055C - Assembled static random read only memories and mask ROM memories

Info

Publication number: CN1298055C
Application number: CNB021273278A
Authority: CN
Inventors: 廖修汉; 陈立业
Original assignee: Lianbang Science And Technology Co Ltd
Current assignee: Lianbang Science And Technology Co Ltd; Brilliance Semiconductor Inc
Priority date: 2002-07-31
Filing date: 2002-07-31
Publication date: 2007-01-31
Anticipated expiration: 2022-07-31
Also published as: CN1841564A; CN1472811A; CN100454440C

Abstract

The present invention relates to a novel memory unit assembly which comprises a static random access unit and a mask read-only memory unit, wherein the read-only memory unit is positioned on a cross region formed by interlacing between a polysilicon region of a fifth transistor and a sixth transistor formed in the random access unit and an extension part of an active region where a source contact point is positioned, and thus, the read-only memory unit and the static random access unit are arranged in the same region. The arrangement enables a word line and a Vss contact point of the static random access unit and the mask read-only memory unit to be shared, an X-decoder line can also be shared, the respective arrangement of circuits of the two units at two regions is not needed, and thus, about 20% of the area of a tube core can be saved.

Description

Combined static RAM and mask ROM storage unit

Technical field

The invention relates to a kind of Nonvolatile static ROM memories, particularly a kind of Nonvolatile static ROM memories in conjunction with mask ROM (mask ROM).

Background technology

Memory can be divided into two big classes: volatile memory (Volatile Memory) and non-volatile (Non volatile Memory) memory.On the development history of nonvolatile memory, mask ROM (the MROM that is suggested at first, Mask ROM:Mask Read OnlyMemory), in manufacture process, in advance program or data are deposited in the employed mask of manufacture process (Photo Mask), but the storage device of permanent storage data.The structure of its memory cell does not need special manufacture process, so very economical.More owing to not needing write activity, so the formation of integrated circuit is comparatively simple.

But still have its following problem to demand urgently overcoming, for example wafer manufactory is long than other ROM (for example EPROM or EEPROM) from being fabricated onto the spent time of delivery, mainly be because Mask ROM is a kind of client's articles made to order, relevant preparation just can be set about producing after receiving the mnemonic code that the client sends here by manufactory.

In addition, must answer the different read-only memory that different clients propose and make mask respectively, just finish through after a certain chip manufacturing engineering, so cost is higher on produced in small quantities.In case after completing, just can't change the storage inside data, so client and manufactory all there is the risk of certain degree.

Though have above-mentioned problem, but still the using value of the mask ROM that do not detract.Yet under the driving of consumption electronic products demand, standing in great numbers in the memory hilltop of all size and form, presents the situation of letting a hundred schools contend.Wherein a kind of promptly is non-volatile static RAM, and the proposition of this technology is because static RAM is a volatile memory, because of its after power supply disappears, its stored data also disappear thereupon, do not have the ability of storage.Therefore, can't forever preserve the characteristic of data in order to remedy static RAM, the non-volatile static RAM with storage characteristics becomes designer trends gradually.

Yet, under the short and small frivolous product trend, for example personal digital assistant, game machine etc., its chip area occupies important decisive factor for the size of product, yet prior art proposes to include sram storage element and mask ROM storage unit, being with the zones of different of its layout on chip, in the utilization of chip area, but is suitable inefficent.Along with short and small frivolous product trend, the less Nonvolatile static ROM memories of a kind of unit are is proposed then.

Summary of the invention

In sum, main purpose of the present invention is to provide a kind of new-type memory cell combination, include a sram cell and a mask read-only memory unit, can optionally use, also have the characteristic of read-only memory simultaneously as static RAM.

Another object of the present invention is providing a kind of area less sram storage element, the active region (Active Area) at source electrode (Vss) contact point (Contact) place extends and forms the transistorized multi-crystal silicon area in memory block and intersects a cross ecotone, to form a mask read-only memory unit.

The invention provides a kind of combined static RAM and mask ROM storage unit, it includes a sram cell and a read-only memory unit, wherein this sram cell is in order to as random-access memory cell, include the first transistor, transistor seconds, the 3rd transistor, the 4th transistor, the 5th transistor and the 6th transistor, this the first transistor, this transistor seconds, the 3rd transistor and the 4th transistor form a flip-flop, this the first transistor and the 3rd transistor complementation, this transistor seconds and the 4th transistor complementation, this read-only memory unit is in order to permanent preservation data, include one the 7th transistor, wherein, this read-only memory unit is to be arranged in the cross district that an active region extension that forms the 5th transistor AND gate the 6th transistorized multi-crystal silicon area and one source pole contact point place is interlocked, and makes this read-only memory unit be arranged in this static random access memory (sram) cell.

The invention provides a kind of assembled static random access memory and mask ROM memory cell, it includes:

One sram cell, at least comprise a first transistor, transistor seconds, the 3rd transistor, the 4th transistor, the 5th electric crystal, the 6th transistor, wherein this first transistor, this second electric crystal, the 3rd transistor and the 4th transistor form a flip-flop, this the first transistor and the 3rd transistor complementation, this transistor seconds and the 4th transistor complementation;

One ROM unit comprises one the 7th transistor at least;

One first bit line is to join with the 5th transistorized source/drain;

One anti-first bit line is to join with the 6th transistorized source/drain;

One the 3rd bit line is to join with the 7th transistor drain/drain electrode; And

One word line is to join with the 5th transistor, the 6th transistor AND gate the 7th transistorized grid, to control the 5th transistor, the 6th transistor AND gate the 7th transistor.

This layout can be shared the word line (WORDLINE) and the Vss contact point of sram cell and mask read-only memory unit, and also can share at the X-decoder circuit, can not be used in two zones and respectively the circuit of two unit be made layout, so as to about 20 of the about percentage of area of saving tube core.

Relevant characteristics and implementation of the present invention are described in detail as follows as most preferred embodiment now in conjunction with the accompanying drawings:

Description of drawings

Fig. 1 is the circuit diagram for Nonvolatile static ROM memories of the present invention;

Fig. 2 is the circuit layout schematic diagram for the traditional static ROM memories; And

Fig. 3 is the circuit layout schematic diagram for Nonvolatile static ROM memories of the present invention.

Embodiment

Memory cell provided by the present invention as shown in Figure 1, include a sram cell 10 (for the ease of discussing and reading, hereinafter referred to as SRAM cell), and a mask read-only memory unit 20 (for the ease of discussing and reading, hereinafter referred to as ROM cell).

SRAM cell 10 is the storage architecture of one digit number certificate, can temporarily keep these data of, and in the time after a while, according to the desired execution command of central processing unit, data is sent to the computing environment.

As shown in Figure 1, include six transistors among the SRAM cell 10, be respectively the first transistor Q1, transistor seconds Q2, the 3rd transistor Q3, the 4th transistor Q4, the 5th transistor Q5, the 6th transistor Q6, a memory cell for a kind of six transistor architecture, be that a pair of CMOS reverser (Inverter) is connected into flip-flop (Flip Flop), memory node N1, N2 connects a pair of access transistor Q5 respectively, Q6 is as the transmission lock, the 5th transistor Q5, the grid of the 6th transistor Q6 connects word line (Word Line), via the first transistor Q1, transistor seconds Q2 and and read and write between the bit line (BitLine), write the transmission of data.Wherein the 3rd transistor Q3 and the 4th transistor Q4 are P raceway groove MOS (metal-oxide-semiconductor) transistor (pMOS), the first transistor Q1 and transistor seconds Q2 are n raceway groove MOS (metal-oxide-semiconductor) transistor (nMOS), and the first transistor Q1 and the 3rd transistor Q3, transistor seconds Q2 and the 4th transistor Q4 form the CMOS reverser respectively.

The grid of the first transistor Q1, the 3rd transistor Q3 (Gate) joins with the drain electrode (Drain) of transistor seconds Q2, the 5th transistor Q5, transistor seconds Q2, the 4th transistor Q4 grid and the drain electrode of the first transistor Q1, the 3rd transistor Q3 join, the source electrode (Source) of the 3rd transistor Q3, the 4th transistor Q4 is received power supply supply Vcc, and the source electrode of the first transistor Q1 and transistor seconds Q2 is ground connection (Vss) then.When data 1 storage (latch) was in SRAM cell 10, transistor seconds Q2 was ON, and the first transistor Q1 is OFF, and memory node N1 voltage is Vcc, and memory node N2 voltage is 0.That is when the first transistor Q1 is OFF and transistor seconds Q2 when being ON, then corresponding representative data 1 is stored among the SRAM cell 10.

The grid of transmission lock the 5th transistor Q5 and the 6th transistor Q6 is connected to word line, drain electrode then is connected respectively to memory node N1 and memory node N2, source electrode is connected respectively to the first bit line BLQ5 and the anti-first bit line BLQ6, the effect of the 5th transistor Q5 and the 6th transistor Q6 is as switch, when its state is ON, data can send out by the first bit line BLQ5 and the anti-first bit line BLQ6, and the state of its ON and OFF is determined by the voltage signal on the word line WL.When the voltage of word line WL was drawn high, the 5th transistor Q5, the 6th transistor Q6 just were opened.By the first bit line BLQ5 and the anti-first bit line BLQ6 one data storing is got up, and data passes is gone out by the first bit line BLQ5, with the anti-first bit line BLQ6.

Including one the 7th transistor Q7 among the ROM cell 20, is a n raceway groove metal-oxide half field effect transistor (nMOS), and its grid is to receive word line WL.Drain electrode is connected to one the 3rd bit line BLROM.Word line WL is that the 5th transistor Q5, the 6th transistor Q6 and the 7th transistor Q7 share, when word line WL voltage is drawn high, SRAM cell 10 and ROM cell 20 promptly are selected, can optionally become SRAM cell or ROM is cell by bit line, for the computing of secondary CPU.

Main purpose of the present invention is integrated into a single memory cell with SRAM cell 10 and ROM cell 20 under the situation that does not increase memory cell area, so as to saving the area of memory chip.As mentioned above, SRAM cell 10 and the word line WL of ROM cell 20 share, and therefore can save the arrangement space of the 7th transistor Q7.And how ROM cell 20 and SRAM cell 10 are combined not increasing area, be described below.

Fig. 2 is the circuit arrangement map of traditional static ROM memories, and the first active region A1 is arranged shown in the figure, is an inverted T-shaped shape; The second active region A2 is two zones that E word shape zone combines relatively; The 3rd active region A3 is an inverted T-shaped shape; The first multi-crystal silicon area P1, the second multi-crystal silicon area P2, the 3rd multi-crystal silicon area P3 are arranged in addition, wherein, the first multi-crystal silicon area P1, the second multi-crystal silicon area P2, the first active region A1, the second active region A2 form the ecotone that four crosses are arranged mutually, to form four transistors, be the first transistor Q1 among Fig. 1, transistor seconds Q2, the 3rd transistor Q3 and the 4th transistor Q4.Wherein the first transistor Q1 and transistor seconds Q2 are nMOS, and the 3rd transistor Q3 and the 4th transistor Q4 are pMOS.

T word protuberance has first make contact (Vcc Contact) CVcc among the first active region A1, the E word protuberance of the second active region A2 has one second contact point (Vss) CVss, the 3rd contact point CPH1, the 4th contact point CPH2 socket the contact on being, are the both sides that are positioned at the T word; The 5th contact point CPD1, the 6th contact point CPD2 are drop-down contact point, are the both sides that are positioned at the E word.

The second active region A2 and the 3rd multi-crystal silicon area P3 are two the cross ecotones that have that are staggered to form, and are the 5th transistor Q5 among Fig. 1 and the 6th transistor Q6.

Lower Half has the 4th multi-crystal silicon area P4, the 5th multi-crystal silicon area P5 and the 6th multi-crystal silicon area P6 among Fig. 2, be formed with six cross ecotones with the second active region A2 and the 3rd active region A3 respectively, be six transistors, form another sram storage element.The 3rd multi-crystal silicon area P3 and the 6th multi-crystal silicon area P6 are across the second active region A2, and the 3rd multi-crystal silicon area P3 and the 6th multi-crystal silicon area P6 do not contact with each other and leave a disconnected blank space, and layout has the first bit line contact point CBL1 and the second bit line contact point CBL2.So constitute two basic static random access memory (sram) cell configurations.

Examine among Fig. 2 and can find, the 3rd multi-crystal silicon area P3 and the 6th multi-crystal silicon area P6 do not join near the second contact point CVss place, and leave a clear area A4, and the present invention promptly utilizes this clear area, layout another read memory cell.

The present invention is that the active region with the second contact point CVss place extends to the 3rd multi-crystal silicon area P3 and the 6th multi-crystal silicon area P6, and staggered with it to form two transistors, as shown in Figure 3.The extension of the second contact point CVss promptly forms a read-only memory unit among the 3rd multi-crystal silicon area P3 and the second active region A2, the 6th multi-crystal silicon area P6 and another read-only memory unit of second active region A2 formation as the same.And the bit line contact point of read-only memory unit is the confluce that is positioned at the second contact point CVss active region extension, as the bit line contact point CBLR of the read-only memory unit among Fig. 3.

As mentioned above, so promptly form can be with the circuit layout of read-only memory unit in static random access memory (sram) cell for layout, effectively utilize the zone that is not used effectively as yet in the static random access memory (sram) cell circuit layout, and its word line can be shared, area and prior art are compared and can be reduced by at least 20 percent assault fortified position, and reach the purpose of effectively utilizing arrangement space, dwindling area.

Claims

1. combined static RAM and mask ROM storage unit is characterized in that, include:

One sram cell, comprise a first transistor, transistor seconds, the 3rd transistor, the 4th transistor, the 5th transistor, the 6th transistor, wherein this first transistor, this transistor seconds, the 3rd transistor and the 4th transistor form a flip-flop, this the first transistor and the 3rd transistor complementation, this transistor seconds and the 4th transistor complementation;

One read-only memory unit comprises one the 7th transistor;

One first bit line joins with the 5th transistorized source electrode;

One anti-first bit line joins with the 6th transistorized source electrode;

One the 3rd bit line joins with the 7th transistor drain; And

One word line joins with the 5th transistor, the 6th transistor and the 7th transistorized grid respectively, in order to control the 5th transistor, the 6th transistor AND gate the 7th transistor.

2. combined static RAM as claimed in claim 1 and mask ROM storage unit, it is characterized in that, this read-only memory unit is to be arranged in the cross district that an active region extension that forms the 5th transistor AND gate the 6th transistorized multi-crystal silicon area and one source pole contact point place is interlocked, and makes this read-only memory unit be in the layout of in this sram cell.

3. combined static RAM as claimed in claim 1 and mask ROM storage unit is characterized in that, this read-only memory unit is a mask ROM.

4. combined static RAM as claimed in claim 1 and mask ROM storage unit, it is characterized in that this first transistor, transistor seconds, the 3rd transistor, the 4th transistor, the 5th transistor and the 6th transistor are metal-oxide half field effect transistor.

5. combined static RAM as claimed in claim 1 and mask ROM storage unit is characterized in that, the bit line contact point of this read-only memory unit is in close proximity to this read-only memory unit.

6. combined static RAM as claimed in claim 1 and mask ROM storage unit is characterized in that, the source electrode contact point of this sram cell and this read-only memory unit is shared.

7. combined static RAM as claimed in claim 1 and mask ROM storage unit is characterized in that, the column decoder Line sharing of this sram cell and this read-only memory unit.