The IC-card of many logical partitions of framework and different purposes in a physical storage
The present invention relates to the integrated circuit structure design in a kind of IC smart card, exactly, relate to a kind of in a physical storage IC-card of the many logical partitions of framework and different purposes, belong to have and conduct electricity the technical field of processing of record carrier (for example credit card or identification card) of mark, P.e.c. or semiconductor circuit components.
Along with developing rapidly of global IC application of IC cards, the development of domestic IC smart card and related industry thereof has become a big focus of China's informatization and the new growth engines of information industry.At present, China's semiconductor production is compared with world's advanced level with processing technology and is also had certain gap, the manufacturing enterprise of a lot of integrated circuit only possesses the ability of production, the processing needed partial logic of smart card and storage unit, and a large amount of production high-performance chip card ICs also exist big difficulty; Therefore, how to break through the system structure of old IC smart card, the production technology of simplifying integrated circuit, become realize the production domesticization of IC intelligent card chip the primary difficult problem that must solve.
As everyone knows, in IC intelligent card chip inside, come down to a microcomputer system that is similar to the computer body system structure that has embedded microprocessor, its structure is formed as shown in Figure 1.At present, Jue Daduoshuo IC smart card all is to adopt this traditional CPU+RAM+ROM+EEPROM architectural framework.Wherein, RAM is a random access memory, is used for storing some interim parameter or intermediate variables of application of IC cards process, and these data are promptly lost after outage.ROM is a ROM (read-only memory), and normally as the program storage of IC smart card, COS (the Chip Operating System) operating system program that is used to store smart card reaches with safety, authenticates relevant cryptographic algorithm or other application program.EEPROM is the electric erazable programmable storer, usually as the data-carrier store of smart card, is used for storage and more user-dependent management datas and user data etc.Above-mentioned this few component parts is different memory modules separate on hardware.To in chip piece, be processed into these three kinds of memory modules simultaneously with difference in functionality, no matter for chip design, or chip production, all there is certain degree of difficulty.Therefore, how to break through the architectural framework of traditional IC smart card, the memory module that function is close merges, and then both can simplify the design difficulty of IC intelligent card chip, reduce the risk of the production and processing of chip, the manufacturing that more can be the IC intelligent card chip realizes that production domesticization creates conditions.
The purpose of this invention is to provide a kind of in a physical storage IC-card of the many logical partitions of framework and different purposes, only be provided with two kinds of memory modules of RAM and EEPROM in the chip of this IC smart card, and in this eeprom memory, set up two or more logical partitions, be respectively applied for different purposes and purposes, for example be respectively applied for storage COS program, cryptographic algorithm or other application program, and management data and user data.So not only the structure of simplified intelligent card is formed, and improves the yield rate of IC Chip Production, also paves the way for the production domesticization production of IC smart card, makes the safe reliability of IC smart card effectively be reported barrier.
The object of the present invention is achieved like this: a kind of in a physical storage IC-card of the many logical partitions of framework and different purposes, include microprocessor and peripheral circuit thereof, it is characterized in that; In the chip of this IC smart card, only be provided with two kinds of memory modules of RAM and EEPROM, and between this eeprom memory and microprocessor, have additional the memory access control module; This memory access control module is changed by its address to the reader storage operation of microprocessor and the storage operation that reads and writes data and its pointer is mapped to the different storage zone of this eeprom memory respectively, thereby make this physical storage (EEPROM) that is in continuous whole on the address logically can be divided into different storage areas according to different use-patterns, each storage area is finished difference in functionality separately respectively.
Wherein memory access control module is connected with eeprom memory with microprocessor respectively by address wire, also is connected with instruction decode line, external memory storage read gate PSEN signal wire and read gate RD signal wire between memory access control module and the microprocessor; The signal of in the memory access control module above-mentioned PSEN signal and read gate RD signal and back being exported then is connected to eeprom memory as read gate RD signal, the read-write control signal WR of microprocessor then directly outputs to eeprom memory, and the sheet choosing of this eeprom memory is connected to ground.
Can set up two or more logical partitions in the above-mentioned eeprom memory, one of them logical partition is as the program storage of storage smart card COS, and another logical partition is then as the data-carrier store of storaging user data.
The division of the logical partition in the above-mentioned eeprom memory is set by user flexibility, can be the logical partition of two equities, also can be two not reciprocity logical partitions, can also be the logical partition more than three or three.
The present invention is the IC-card of the many logical partitions of framework and different purposes in a physical storage, its technical characterstic is only to be provided with RAM and two kinds of memory modules of EEPROM in the chip of this IC smart card, and there is not the ROM memory module, and in this eeprom memory, set up two or more logical partitions, be respectively applied for storage COS program, cryptographic algorithm or other application program, and storage administration data and different purposes such as user data, so not only simplifying the structure of IC smart card forms, improve the yield rate of IC Chip Production, also pave the way for the production domesticization production of IC smart card, for country saves a large amount of foreign exchanges, the particularly important is the security of IC smart card is reliably guaranteed.
Describe structure of the present invention, feature and effect in detail below in conjunction with drawings and Examples:
Fig. 1 is the synoptic diagram of the traditional system framework of IC intelligent card chip.
Fig. 2 is the memory access control control module and electric principle schematic of being connected of microprocessor and eeprom memory of setting up in the IC intelligent card chip of the present invention.
Traditional system framework referring to IC intelligent card chip shown in Figure 1.Wherein ROM is a ROM (read-only memory), is generally used for storing chip operating system COS (Chip Operating System), cryptographic algorithm or other application program of smart card.And EEPROM is the electric erazable programmable storer, management data and user data that storage is relevant.In itself, ROM and EEPROM are storeies, and difference only is the data of wherein storing or the purposes difference of code.
Referring to Fig. 2, the present invention be a kind of in a physical storage IC-card of the many logical partitions of framework and different purposes, in the chip of this IC smart card, be provided with microprocessor 1 and peripheral circuit thereof, and memory module only is provided with two kinds of RAM (not shown) and EEPROM, and between this eeprom memory 3 and microprocessor 1, have additional memory access control module 2.Wherein memory access control module 2 is connected with eeprom memory 3 with microprocessor 1 respectively by address wire, also is connected with instruction decode line, external memory storage read gate DPSEN signal wire and read gate RD signal wire between memory access control module 2 and the microprocessor 1; Then be connected to eeprom memory 3 at 2 li signals that above-mentioned PSEN signal and RD signal and back are exported of memory access control module as the RD signal, the read-write control signal WR of microprocessor 1 then directly outputs to eeprom memory 3, and the sheet choosing of this eeprom memory 3 is connected to ground.Framework by this, this memory access control module 2 is changed by its address to the reader storage operation of microprocessor 1 and the storage operation that reads and writes data and its pointer is mapped to the different storage zone of this eeprom memory 3 respectively, thereby make this physical storage 3 (EEPROM) that is in continuous whole on the address logically can be divided into different storage areas according to different use-patterns, each storage area is finished difference in functionality separately respectively.
Essence of the present invention is the function of above-mentioned two kinds of ROM and eeprom memory and purposes are all born by storer of EEPROM and to be finished it, promptly will be in a memory module of continuation address originally physically by the memory access control module of setting up, logically be divided into a plurality of subregions, with a storer of original special purpose, become and possess difference in functionality, be used for a plurality of storeies of various objectives; Thereby the architecture of simplified intelligent the core of the card sheet, the fabrication yield of raising integrated circuit (IC) chip.
Realization principle of the present invention is summarized as follows: traditional IC smart card based on INTEL 8051 CPU systems, be to utilize 8051 pairs of outside storage operations to adopt time-multiplexed characteristics, PSEN signal and RD, WR signal can not be low simultaneously, so the geocoding of its data-carrier store and program storage overlaps, that is to say that the address of its program storage and data-carrier store all is to begin addressing from 0000H.So, architectural framework originally be impossible directly with a block storage not only as program storage, but also use as data-carrier store.But,, the data storage area is arranged again if, just can realize existing program storage area at a storer with program storage or the conversion of data memory addresses process that CPU sent.Referring to Fig. 2, this figure right side is a physically complete EEPROM macroelement storer 3, by the memory access control module 2 in the middle of Fig. 2, with a block storage 3 of continuous whole physically according to the use-pattern difference, logically be divided into different districts, each logic area is realized function separately respectively.The memory access control module is responsible for different application is mapped to the respective regions of macroelement storer.For example when CPU wants instruction fetch, this instruction address that will carry out (program memory address) of depositing in the programmable counter PC pointer, through the conversion of memory access control module, this address is mapped to corresponding program storage area in the macroelement storer, therefrom take out instruction code.When CPU requires to read and write data storer,, again this address is mapped to corresponding data storage area in the macroelement storer through the conversion of memory access control module.
Can set up two or more logical partitions in the eeprom memory among the present invention, one of them logical partition is as the program storage of storage smart card COS, and another logical partition is then as the data-carrier store of storaging user data.And the division of the logical partition in this eeprom memory is set by user flexibility, can be the logical partition of two equities, also can be two not reciprocity logical partitions, can also be the logical partition more than three or three.
For example, the eeprom memory module of a 32K capacity can be divided into two parts with it, a part is as the program storage of storage smart card COS, and another part is as the data-carrier store of storaging user data.Because the division of difference in functionality module relies on the memory access control module to finish, so the dividing mode to EEPROM can be very flexible, such as adopting following different schemes to realize: 1. 16K program storage+16K data-carrier store, 2. 20K program storage+12K data-carrier store, 3. 16K program storage+8K data-carrier store 1 district+multiple schemes such as 8K data-carrier store 2 districts.
With first kind of subregion is example, if wishing program pointer addressing and data field addressing all keeps from 0000H, then need following processing: when CPU read certain bar instruction on the 0080H address, through the memory access control module, the EEPROM home address after the decoding was 0080H; When CPU will read the data-carrier store of 0080H address, through the memory access control module, the EEPROM home address after the decoding was 4000H+0080H=4080H.
Below table 1 be depicted as the address mapping relation of above-mentioned three kinds of different schemes:
Table 1
16K+16K divides |
The procedure stores regional address | Data memory area address |
????0000H-3FFFH | ????4000H-7FFFH |
20K+12K divides |
The procedure stores regional address | Data memory area address |
????0000H-4FFFH | ????5000H-7FFFH |
16K+8K+8K divides |
The procedure stores regional address | Data memory area address |
????0000H-3FFFH | ????4000H-5FFFH,6000H-7FFFH |
Certainly, one can be if allow program storage area or data memory area address to have at least not begin addressing from 0000H, even 8051 OPADD directly is not connected to the address bus of EEPROM through the memory access control module, still can realize the subregion storage of a storer.Such as: program pointer addresses from 0000H, but the data field can only begin access from 4000H at this moment, can bring certain inconvenience to the operation of IC-card like this.
The applicant has carried out a large amount of demonstrations and has implemented test according to the solution of the present invention, and on the structural design of chip card IC system, carry out l-G simulation test, utilize novel smart card architectural framework of the present invention to design GSM mobile handset special SIM card chip, implement the respond well of test, realized goal of the invention.