CN1296831C - Sequential controlling method for synchronous memory - Google Patents
Sequential controlling method for synchronous memory Download PDFInfo
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- CN1296831C CN1296831C CNB031540007A CN03154000A CN1296831C CN 1296831 C CN1296831 C CN 1296831C CN B031540007 A CNB031540007 A CN B031540007A CN 03154000 A CN03154000 A CN 03154000A CN 1296831 C CN1296831 C CN 1296831C
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Abstract
The present invention relates to a sequence controlling method for a synchronous memory body. The synchronous memory body is provided with a regional information busbar, a signal amplifying busbar and a universal information busbar. The sensing sequence controlling method is used for precharging the regional information busbar, executing developed signals on the signal amplifying busbar in a sequence pulse period, amplifying and transmitting regional information to the universal busbar in a next sequence pulse and concealing the precharging period of the regional information. The present invention can make the synchronous memory body uniformly complete each work in a synchronous sequence, make the use of the synchronous sequence optimized, the operation speed of the synchronous memory body not limited, change the period of signal development time, and make the control of the signal development time optimized, so the present invention is favorable to increasing the operation speed of the synchronous memory body.
Description
Technical field
The present invention relates to the sequential control method in a kind of area information storage storer, particularly relate to a kind of sequential control method (Timing control method for operatinga synchronous memory) of synchronous memory body.
Background technology
In in the past 10 years, the speed and the capacity of memory body (be storer, below all be called memory body) array have had sizable improvement.More especially owing to the multiple function in each field, memory body has become the major product of integrated circuit industry.The technology of memory body is by asynchronous pattern, it for example is fast page mode, extension data output (EDO), pulse extension data output (PEDO), being evolved into the synchronous pattern of today, for example is the synchronous dynamic random memory body, directly random memory body bus-bar dynamic random memory body (Direct Rambus DRAM), double data rate synchronous dynamic random memory body (DDR-SDRAM), and link dynamic random memory (SLDRAM) etc. synchronously.
Seeing also shown in Figure 1ly, is the calcspar of the existing known synchronous memory body that is used for first kind of sequential control.In the drawings, demoder 102 is decoded into address value Baddress with the address value Xadress of system, and (Column Select Signal CSL) becomes high levle from low level will to select signal with the corresponding row of this address value Baddress.Reading region data LD (Local Data) (data is data, below all be called data) corresponding to the address of the memory array (Array) 104 of this address value Baddress then.Because the signal level very little (approximately being the accurate potential difference about 100mV) of region data LD, so the signal level of region data LD must be amplified to scope between accurate of 0V and the operating voltage.Therefore, the region data LD that is read by memory array 104 delivers to sensing amplifier (Sense Amplifier) 106 by region data bus-bar (LocalData Bus) 110, by sensing amplifier 106 signal level of the region data LD that received is converted to uri information GD (Global Data) between 0V and the accurate position of operating voltage scope, then uri information GD is delivered to working storage (Register) 108 by uri information bus-bar (Global Data Bus) 112 and keep in.This uri information GD will be temporary in the working storage 108, when next clock signal triggers working storage 108, just send an output data DO to synchronous memory body (Synchronous Memory) 100 by the outside bus-bar (not shown) that is connected.
Above-mentioned action is to finish in synchronous sequence P0, P1, three sequential circulations of P2, and Fig. 2 is for being supplied to the sequential chart of the action of the various signals of synchronous memory body 100 among Fig. 1.See also shown in Figure 2ly, P0 the sequential of synchronous sequence xclk reads a address value Xadress earlier.Then, demoder 102 will be gone and be selected signal (Column Select Signal CSL) exports after being decoded into high levle, and then, memory array 104 reads a region data LD of corresponding its address.
Then, LDB precharge signal end is sent a low level signal and is made the signal level preliminary filling (Precharge) of region data bus-bar 110 to operating voltage.At this moment, GDB precharge signal end is also sent a low level signal and is made the signal level of uri information bus-bar 112 be charged to operating voltage in advance.After region data bus-bar 110 finishes preliminary filling (being that signal LDB precharge transfers high levle to by low level), a region data LD forms the signal level with high-low signal difference gradually at region data bus-bar 110.Similarly, uri information bus-bar 112 finishes (being that signal GDB precharge transfers high levle to by low level) after the preliminary fillings, and a the region data LD that sensing amplifier 106 will have a signal level of high-low signal difference is enlarged into a uri information GD between 0V and the accurate scope of operating voltage.Then, sensing amplifier 106 is delivered to a uri information GD on the uri information bus-bar 112.
Carrying out development, the signal of preliminary fillings, region data signal and amplify and work such as data transmission so demoder 102 carries out decoding, read data, sensing amplifier 106 from memory array 104, all is to finish in P0 sequential.In addition, transferring high levle and signal set at signal LDB precharge to by low level, to transfer between the high levle to form the time span that a region data LD have the high-low signal difference by low level be to be called signal development time (Signal Developing Time).
After a high levle signal decoding was become row selection signal (CSL a+1), P1 the sequential of synchronous sequence xclk at first read a+1 address value Xadress.Then, read a+1 region data LD of corresponding its address.Secondly, region data bus-bar 110 and uri information bus-bar 112 are carried out preliminary filling, then the signal level of a+1 region data LD is enlarged into the signal level of a+1 uri information GD, and a+1 uri information GD delivered to uri information bus-bar 112.At this moment, working storage 108 is temporary in a uri information GD (Gda as shown in Figure 2) on the uri information bus-bar 112.In other words, working storage 108 is in the temporary action of P1 sequential execution data.
Similarly, after a high levle signal decoding was become row selection signal (CSL a+2), P2 the sequential of synchronous sequence xclk at first read a+2 address value Xadress.Then, read a+2 region data LD of corresponding its address.Secondly, region data bus-bar 110 and uri information bus-bar 112 are carried out preliminary filling, and then the signal level with a+2 region data LD is enlarged into the signal level of a+2 uri information GD and a+2 uri information GD is delivered to uri information bus-bar 112.At this moment, a the uri information GD that working storage 108 will before be kept in sends the outside bus-bar (not shown) that is connected to synchronous memory body 100 with a pen output data DO (DOa as shown in Figure 2), so working storage 108 is in the action of P2 sequential execution data output.
Seeing also shown in Figure 3ly, is the calcspar of the existing known synchronous memory body that is used for second kind of sequential control.In Fig. 3, its function is identical with Fig. 1, and Fig. 3 and Fig. 1 difference are synchronous sequence P0, P1, three sequential of P2 corresponding to the position of the device in the memory body synchronously.In other words, i.e. the operational circumstances difference of its device in each synchronous sequence.Fig. 4 is the sequential chart of the execution action of corresponding diagram 3.
See also shown in Figure 4, in Fig. 4 (in conjunction with consult shown in Figure 3), P0 the sequential of synchronous sequence xclk at first reads a address value Xadress, decoded by demoder 102 then.In other words, demoder 102 is carried out the action of decoding P0 sequential.
After a high levle signal decoding was become row selection signal (CSL a+1), P1 the sequential of synchronous sequence xclk at first read a+1 address value Xadress.At this moment, read a region data LD of corresponding its address at memory array 104.Then, LDB precharge signal end is sent a low level signal makes the signal level of region data bus-bar 110 be charged to operating voltage in advance, and GDB precharge signal end is also sent a low level signal and made the signal level of uri information bus-bar 112 be charged to operating voltage in advance.
After region data bus-bar 110 finishes preliminary filling (being that signal LDB precharge transfers high levle to by low level), a region data LD forms the signal level with high-low signal difference gradually at region data bus-bar 110.Similarly, uri information bus-bar 112 finishes (being that signal GDB precharge transfers high levle to by low level) after the preliminary fillings, and a the region data LD that sensing amplifier 106 will have a signal level of high-low signal difference is enlarged into a uri information GD between 0V and the accurate scope of operating voltage.Then, sensing amplifier 106 is delivered to a uri information GD on the uri information bus-bar 112.
So,, all be in P1 sequential, to finish from the work such as development, signal amplification and data transmission that memory array 104 reads data, sensing amplifier 106 execution preliminary fillings, region data signal.In addition, transferring high levle and signal set at signal LDB precharge to by low level, to transfer between the high levle to form the time span that a region data LD have the high-low signal difference by low level be to be called the signal development time.
Similarly, after decoding, read a+2 address value Xadress earlier in P2 the sequential of synchronous sequence xclk.Then, read a+1 region data LD of corresponding its address.Secondly, column selection CSL signal end is sent a high levle signal, and region data bus-bar 110 and uri information bus-bar 112 are carried out preliminary filling.And the signal level of a+1 region data LD is enlarged into the signal level of a+1 uri information GD, and a+1 uri information GD delivered to uri information bus-bar 112.At this moment, a the uri information GD that working storage 108 will before be kept in sends the outside bus-bar (not shown) that is connected to synchronous memory body 100 with a pen output data DO (DOa as shown in Figure 4), so working storage 108 is carried out the action of data storage and data output P2 sequential.
In sum, the work that sensing amplifier is carried out comprises that the preliminary filling of region data bus-bar, the signal of region data develop the required time, transmit uri information to the uri information bus-bar, and it is all finished in a synchronous sequence.And other interior device of memory body also is to finish its work in a synchronous sequence synchronously.Therefore, can know easily, in each synchronous sequence of synchronous memory body, be difficult to very much each device optimized, also so limited the operating speed of synchronous memory body.In addition, the required signal development time of region data is fixed, and makes the signal development time also be subjected to its influence.Therefore, the operating speed of how improving synchronous memory body in the signal development time of minimum is suitable difficulty.
This shows that the sequential control method of above-mentioned existing synchronous memory body still has many defectives, and demands urgently further being improved.For the defective of the sequential control method that solves existing synchronous memory body, relevant manufacturer there's no one who doesn't or isn't seeks solution painstakingly, but does not see always that for a long time suitable design finished by development, and this obviously is the problem that the anxious desire of relevant dealer solves.
Because the defective that the sequential control method of above-mentioned existing synchronous memory body exists, the inventor is based on being engaged in this type of product design manufacturing abundant for many years practical experience and professional knowledge, actively studied innovation, in the hope of founding a kind of sequential control method of synchronous memory body newly, can improve the sequential control method of existing synchronous memory body, make it have more practicality.Through constantly research, design, and after studying sample and improvement repeatedly, create the present invention who has practical value finally.
Summary of the invention
Fundamental purpose of the present invention is, overcome the defective of the sequential control method existence of above-mentioned existing synchronous memory body, and a kind of sequential control method of new synchronous memory body is provided, technical problem underlying to be solved is that to make its method be to make the utilization of synchronous sequence reach optimization, and can promote the operating speed of synchronous memory body.
Another object of the present invention is to, a kind of sequential control method of synchronous memory body is provided, technical matters to be solved is that the required signal development time of region data can be changed, and makes the signal development time can be controlled to minimum, and can improve the operating speed of synchronous memory body.
Purpose of the present invention and to solve its technical problem underlying be to adopt following technical scheme to realize.The sequential control method of a kind of synchronous memory body that proposes according to the present invention, this synchronous memory body has a region data bus-bar, a signal amplifies a bus-bar and a uri information bus-bar, the sequential control method of this synchronous memory body comprises the following steps: to provide a synchronous sequential, the step below n+1 sequential in this synchronous sequence carried out; An a+1 region data reads and decodes; In a region data bus-bar preliminary filling sequential, this region data bus-bar is charged to an initial value in advance; In a uri information transmission cycle, amplify an a uri information and transmit a uri information to this uri information bus-bar to this uri information bus-bar and from signal amplification bus-bar; In a non-region data bus-bar preliminary filling sequential, this a+1 region data delivered to this region data bus-bar; After this a uri information temporarily is stored in a working storage, amplify in the bus-bar preliminary filling sequential at a signal, this signal is amplified bus-bar be charged to this initial value in advance with this uri information bus-bar that stores this a uri information; And this a+1 region data is sent to this signal from this region data bus-bar amplifies bus-bar, wherein n and a are natural number.
The object of the invention to solve the technical problems can also be further achieved by the following technical measures.
The sequential control method of aforesaid synchronous memory body, the step below wherein n sequential in this synchronous sequence carried out: read an address value; This address value is decoded; And the data of retrieval and this region data bus-bar in a zone that conforms to by the address that decode operation provided.
The sequential control method of aforesaid synchronous memory body, after wherein this address value being finished to decode, in this non-region data bus-bar preliminary filling sequential, an a region data is to place this region data bus-bar, and it is to finish in the decode cycle in this location value that sequential is selected by delegation.
The sequential control method of aforesaid synchronous memory body wherein amplifies bus-bar with this a uri information by this signal and is sent to after this uri information bus-bar, more comprises in this a uri information of temporary transient storage this working storage in this synchronous memory body.
The sequential control method of aforesaid synchronous memory body wherein by after temporary a the uri information of this working storage, more is included in n+2 the sequential in this synchronous sequence, sends this a uri information by this working storage.
The sequential control method of aforesaid synchronous memory body, when wherein this a+1 region data being placed in this region data bus-bar, it is right to need a signal development time that this a+1 region data formed a+1 region data.
The sequential control method of aforesaid synchronous memory body, wherein the length of this signal development time changes the time interval in this uri information transmission cycle into for this a non-region data bus-bar preliminary filling sequential and a non-uri information transmission for this region data bus-bar preliminary filling timing transition.
The present invention compared with prior art has tangible advantage and beneficial effect.By above technical scheme as can be known, in order to reach aforementioned goal of the invention, major technique of the present invention thes contents are as follows:
The present invention proposes a kind of sequential control method of synchronous memory body, and this synchronous memory body comprises that region data bus-bar, signal amplify bus-bar and uri information bus-bar.Synchronously the sensing sequential control method of memory body is at first providing a synchronous sequential, and the step below n+1 the sequential execution in this synchronous sequence.During region data bus-bar preliminary filling, be an initial value with region data bus-bar preliminary filling.Then, corresponding to the region data bus-bar preliminary filling sequential in the circulation of first preliminary filling, after uri information bus-bar preliminary filling finishes, promptly a uri information amplified bus-bar by signal and transfer to the uri information bus-bar according to the first transmission round-robin uri information transmission cycle.Then, the non-region data bus-bar preliminary filling sequential in the circulation of first preliminary filling, a+1 region data will be sent to the region data bus-bar.Moreover, corresponding to the non-region data bus-bar preliminary filling sequential in the circulation of first preliminary filling, storing a uri information after working storage, signal amplification bus-bar preliminary filling sequential in circulating according to second preliminary filling respectively and the uri information bus-bar preliminary filling sequential in the circulation of the 3rd preliminary filling are amplified bus-bar with signal and uri information bus-bar preliminary filling is an initial value.And corresponding to the non-region data bus-bar preliminary filling sequential in the circulation of first preliminary filling, after signal amplifies bus-bar end preliminary filling, region data transmission cycle according to one second transmission time sequence, a+1 region data delivered to signal by the region data bus-bar amplify bus-bar, and a+1 region data is enlarged into a+1 uri information.So, sensing amplifier only needs to finish the preliminary filling and development required time of regional data signal of region data bus-bar in clock pulse circulation.Transmit uri information to uri information bus-bar and be configured in next cycle, and hidden the pre-charging time of region data bus-bar.In such configuration, can make synchronous memory body in a synchronous sequence, finish every work fifty-fifty.So synchronous sequence can fully be utilized, and the signal development time that is used for increasing operating speed can reach optimization.
By technique scheme, the performed work of sensing amplifier of the present invention is the required time of signal development of the preliminary filling and the region data of region data bus-bar, and it is to finish in a synchronous sequence.And other work that sensing amplifier is carried out, for example with uri information be sent to the uri information bus-bar, it is to finish in next synchronous sequence.Therefore, sensing amplifier only needs to finish the preliminary filling and development required time of regional data signal of region data bus-bar in clock pulse circulation.Transmit uri information to uri information bus-bar and be configured in next cycle, and hidden the pre-charging time of region data bus-bar.' LDB precharge ' signal change into by low level high levle during with ' set ' signal change into by low level high levle during, be referred to as the signal development time, and it depends on clock pulse cycling time.So memory body speed can be done the oneself and adjust in the signal development time.In such sequential is distributed, can make synchronous memory body in a synchronous sequence, finish every work fifty-fifty.Therefore, synchronous sequence can fully be utilized, and can improve the operating speed of synchronous memory body.Further, the signal development time that is used for region data can change, and can be used to shorten the running time.In a word, the present invention can increase the operating speed of synchronous memory body.
Therefore, advantage of the present invention is to make synchronous memory body finish every work fifty-fifty in a synchronous sequence, allows the utilization of synchronous sequence can reach optimization, and operating speed that can the limits synchronization memory body.Another advantage of the present invention is the time length that can change the signal development time, makes the signal development time can be controlled at the best, thereby helps increasing synchronous memory body operating speed.
In sum, the sequential control method of the synchronous memory body that the present invention is special, this synchronous memory body have a region data bus-bar, a signal amplifies a bus-bar and a uri information bus-bar.Its sensing sequential control method comprises makes region data bus-bar, signal amplification bus-bar and uri information bus-bar carry out preliminary filling, carry out the development signal that amplifies on the bus-bar the region data bus-bar in a clock pulse.And amplify with transit area data to general bus-bar and will carry out in next clock pulse, and it has hidden region data preliminary filling sequential.The sequential control method of this synchronous memory body can make the utilization of synchronous sequence reach optimization, and can promote the operating speed of synchronous memory body.Moreover the required signal development time of region data can change, and makes the signal development time can be controlled to minimum, and can improve the operating speed of synchronous memory body.It has above-mentioned many advantages and practical value, it really belongs to innovation on control method, no matter bigger improvement is all arranged on method or function, the sequential control method of more existing synchronous memory body has the multinomial effect of enhancement, and have large improvement technically, and produced handy and practical effect, have the extensive value of industry, thereby being suitable for practicality more, really is a new and innovative, progressive, practical new design.
Above-mentioned explanation only is the general introduction of technical solution of the present invention, for can clearer understanding technological means of the present invention, and can be implemented according to the content of instructions, below with preferred embodiment of the present invention and conjunction with figs. describe in detail as after.
Description of drawings
Fig. 1 is the calcspar that has the known synchronous memory body that is used for first kind of sequential control now.
Fig. 2 is the sequential chart of action of the various signals of corresponding diagram 1.
Fig. 3 is the calcspar that has the known synchronous memory body that is used for second kind of sequential control now.
Fig. 4 is the sequential chart of action of the various signals of corresponding diagram 3.
Fig. 5 is the calcspar of the synchronous memory body of a kind of sequential control of the present invention.
Fig. 6 is the calcspar of the synchronous memory body of another kind of sequential control of the present invention.
Fig. 7 is the circuit diagram of sensing amplifier of the present invention.
Fig. 8 is the sequential chart of the circuit of Fig. 7.
100: synchronous memory body (synchronous memories)
102:116,118: demoder (code translator)
104: memory array (memory array)
106: sensing amplifier
108: working storage (buffer)
110: region data bus-bar (area data bus)
112: uri information bus-bar (conventional data bus)
114: logical circuit
702，704，710，712，718，720，726，728，730，732，738：PMOS
706,708: the region data bus-bar is to (area data bus to)
714,716: signal amplifies bus-bar to (signal amplify bus to)
722,724: the uri information bus-bar is to (conventional data bus to)
734，736，740，742：NMOS
Embodiment
Below in conjunction with accompanying drawing and preferred embodiment, its concrete control method of sequential control method, step, feature and the effect thereof of the synchronous memory body that foundation the present invention is proposed, describe in detail as after.
Seeing also shown in Figure 5ly, is a kind of calcspar that is used for the synchronous memory body of sequential control of preferred embodiment of the present invention.In Fig. 5, its function is identical with Fig. 1 and Fig. 3, and Fig. 5 and Fig. 1 and Fig. 3 difference are synchronous sequence P0, P1, three sequential of P2 corresponding to the position of the device in the memory body synchronously.In other words, i.e. the operational circumstances difference of its device in each synchronous sequence.
Seeing also shown in Figure 6ly, is the calcspar that the another kind of preferred embodiment of the present invention is used for the synchronous memory body of sequential control.In Fig. 6, demoder 116 is decoded into row address value X (0)～X (N) and row address value Y (0)～Y (M) with demoder 118 respectively with address value Xadress, and select row selection signal CSL (0)～CSL (N * M) one of them.From memory array 104, read (the region data LD of N * M) then corresponding to these row selection signals CSL (0)～CSL.Owing to the signal level very little (approximately being the accurate potential difference about 100mV) of region data LD, the signal level of region data LD must be promoted to the scope of 0V and the accurate interdigit of operating voltage.Therefore, the region data LD that is read by memory array 104 is for to deliver to sensing amplifier 106 by region data bus-bar 110.At this moment, sensing amplifier 106 is converted to the region data LD of little signal level the uri information GD of the signal level between 0V and operating voltage according to clock signal LDB precharge, gate, precharge, set, GDB precharge etc. that logical circuit 114 sent.Then, uri information GD being delivered to working storage 108 by uri information bus-bar 112 keeps in.When receiving a clock signal, promptly send the outside bus-bar (not shown) that an output data DO is connected to synchronous memory body 100 by working storage 108.
Seeing also shown in Figure 7ly, is the circuit diagram of the sensing amplifier of preferred embodiment of the present invention.Circuit shown in Fig. 7 is the part circuit of sensing amplifier 106 (consulting shown in Figure 5), and this circuit only is that the single area data is done discussion to (Pair) (the right number of the region data of region data bus-bar 110 depends on the figure place of output data DO) and single general-purpose data to (the right number of the uri information of uri information bus-bar 112 depends on the figure place of output data DO).
In Fig. 7, PMOS 702 and PMOS 704 are for to be charged to VCC (being operating voltage) with the region data bus-bar in advance to 706,708, PMOS 710 and PMOS 712 are charged to VCC for signal is amplified bus-bar in advance to 714,716, and PMOS 718 and PMOS 720 are for to be charged to VCC with the uri information bus-bar in advance to 722,724.PMOS 726 and PMOS 728 are the usefulness as switch, and it is for transferring to signal amplification bus-bar respectively on 714,716 with the region data bus-bar to region data LDx on 706,708 and LDx.And NMOS 740 and NMOS 742 also are the usefulness as switch, and it transfers to the uri information bus-bar respectively on 722,724 for signal being amplified bus-bar to the uri information GDx that has been exaggerated on 714,716 and GDx.PMOS 730, PMOS 732, NMOS 734, NMOS 736 and PMOS 738 are the usefulness as the signal amplification, uri information GDx and GDx that it is amplified to the signal level between 0V and VCC voltage respectively for region data LDx and LDx with little signal level.
Seeing also shown in Figure 8ly, is the sequential chart of the circuit diagram of Fig. 7.In Fig. 8, in P0 the sequential of synchronous sequence xclk, it reads a address value Xadress earlier.Then, after demoder 102 was carried out a decoding action, memory array 104 read a region data LD of corresponding its address from a zone.
When reading address value and decoding, signal LDB precharge is a high levle, and PMOS702,704 does not carry out the action of preliminary filling to region data to bus-bar 706,708.Similarly, when signal gate is a high levle, PMOS 726,728 does not do the action of data transmission, and signal set is a high levle, and NMOS 740,742 does not do the action of data transmission.When signal precharge and signal set were low level, PMOS 710,712 amplified bus-bar to signal and does not carry out the action of preliminary filling to 714,716.On the other hand, when signal GDB precharge is low level, PMOS 718,720 with the uri information bus-bar to 722,724 voltages that are charged to VCC in advance.
When finishing to read action such as address value, decoding, row selection signal CSL end is sent a high levle signal, synchronous signal LDB precharge end is sent a low level signal, makes 702,704 pairs of region data bus-bars of PMOS be charged to VCC voltage in advance to 706,708.When the region data bus-bar finished preliminary filling to 706,708, signal LDB precharge transferred high levle to by low level.At this moment, deliver to region data by memory array 104 (consulting shown in Figure 5) a region data of bus-bar 706,708 developed into different signal level to LDx with the LDx commencing signal.
Then, signal gate transfers low level to by high levle, and PMOS 726,728 develops into signal a region data of different signal level LDx and LDx are delivered to signal amplification bus-bar to 714,716 by the region data bus-bar to 706,708.At this moment, because signal set is a low level.So ' LDB precharge ' signal change into from low level high levle and ' set ' signal change into from low level high levle during, a region data little by little develops signal level to LDx and LDx, and promptly is called the signal development time during this.
As mentioned above, demoder 102 (consulting shown in Figure 5) is carried out decoding; Sensing amplifier 106 (consulting shown in Figure 5) is to the preliminary filling of region data to bus-bar 706,708; From memory array 104 (consulting shown in Figure 5) acquisition data; A region data develops into different signal level at the region data bus-bar to 706,708 with LDx to LDx; And a region data done work such as signal amplification to LDx and LDx, all be in P0 sequential, to finish.
In P1 the sequential of synchronous sequence xclk, it has been carried out and has read a+1 address value Xadress and decoding.Array selecting signal CSL end is sent a low level signal, and array selecting signal CSL (a+1) end is sent a high levle signal.During CSL triggered, ' LDB precharge ' end was sent the low level signal so that the region data bus-bar is carried out preliminary filling to 706,708.After the LDB preliminary filling finishes, the signal development of a+1 region data to LDx and LDx will be finished.Carry out address value Xadress read and when decoding, signal set will transfer high levle to by low level.So, uri information GDx and GDx that PMOS730 and 732, NMOS734 and 736, PMOS738 are amplified to the signal level between 0V and VCC voltage respectively with the region data LDx and the LDx of little signal level.NMOS 740,742 delivers to uri information bus-bar to 722,724 by signal amplification bus-bar to 714,716 to GDx and GDx with a uri information.And working storage 108 (consulting shown in Figure 5) will temporarily be stored in uri information to a uri information on the bus-bar 722,724 to GDx and GDx.So, in P1 sequential, performed step comprises (a+1) address is read and decodes, the signal development that (a+1) region data is right, a uri information amplified GDx and GDx and be sent to uri information by NMOS 722,724 bus-bar 722,724, and in working storage 108, temporarily be stored in uri information to a uri information on the bus-bar 722,724 to GDx and GDx.
Similarly, in P2 the sequential of synchronous sequence xclk, it also for reading a+2 address value Xadress earlier, is decoded then.Then, read a+2 region data of corresponding its address to LDx and LDx.When row selection signal CSL (a+1) is low level and CSL (a+1) during for high levle, region data is carried out preliminary filling to bus-bar 706,708 and uri information to bus-bar 722,724.Then, finish of the signal development of a+2 region data to LDx and LDx.Then a+2 region data is enlarged into a+2 uri information to GDx and GDx and be sent to the uri information bus-bar to 722,724 to LDx and LDx.At last, uri information temporarily is stored in the working storage 108 (consulting shown in Figure 5) GDx and GDx a uri information on the bus-bar 722,724.At this moment, previous a temporary uri information GDx will be transferred into the outside bus-bar (not shown) that synchronous memory body 100 (consulting shown in Figure 5) is connected by output data DO end (DOa as shown in Figure 5) with GDx, so working storage 108 is in the function of P2 sequential execution data output.
In sum, the work that sensing amplifier is carried out is the required time of signal development of the preliminary filling and the region data of region data bus-bar, and it is to finish in a synchronous sequence.And other work that sensing amplifier is carried out, as with uri information be sent to the uri information bus-bar, it is to finish in next synchronous sequence.So, sensing amplifier only needs to finish the preliminary filling and development required time of regional data signal of region data bus-bar in clock pulse circulation.Transmit uri information to uri information bus-bar and be configured in next cycle, and hidden the pre-charging time of region data bus-bar.' LDBprecharge ' signal change into by low level high levle during with ' set ' signal change into by low level high levle during, be referred to as the signal development time, and it depends on clock pulse cycling time.So memory body speed can be done the oneself and adjust in the signal development time.In such sequential is distributed, can make synchronous memory body in a synchronous sequence, finish every work fifty-fifty.Therefore, synchronous sequence can fully be utilized, and can improve the operating speed of synchronous memory body.Furthermore, the signal development time that is used for region data can change, and can be used to shorten the running time.Generally speaking, the present invention can increase the operating speed of synchronous memory body.
The above, it only is preferred embodiment of the present invention, be not that the present invention is done any pro forma restriction, though the present invention discloses as above with preferred embodiment, yet be not in order to limit the present invention, any those skilled in the art, in not breaking away from the technical solution of the present invention scope, when the method that can utilize above-mentioned announcement and technology contents are made a little change or be modified to the equivalent embodiment of equivalent variations, but every content that does not break away from technical solution of the present invention, according to technical spirit of the present invention to any simple modification that above embodiment did, equivalent variations and modification all still belong in the scope of technical solution of the present invention.
Claims (7)
1, a kind of sequential control method of synchronous memory body is characterized in that this synchronous memory body has a region data bus-bar, a signal amplifies a bus-bar and a uri information bus-bar, and the sequential control method of this synchronous memory body comprises the following steps:
Provide a synchronous sequential, the step below n+1 sequential in this synchronous sequence carried out;
An a+1 region data reads and decodes;
In a region data bus-bar preliminary filling sequential, this region data bus-bar is charged to an initial value in advance;
In a uri information transmission cycle, amplify an a uri information and transmit this a uri information to this uri information bus-bar to this uri information bus-bar and from signal amplification bus-bar;
In a non-region data bus-bar preliminary filling sequential, this a+1 region data delivered to this region data bus-bar;
After this a uri information temporarily is stored in a working storage, amplify in the bus-bar preliminary filling sequential at a signal, this signal is amplified bus-bar be charged to this initial value in advance with this uri information bus-bar that stores this a uri information; And
This a+1 region data is sent to this signal from this region data bus-bar amplifies bus-bar, wherein n and a are natural number.
2, the sequential control method of synchronous memory body according to claim 1 is characterized in that the step below wherein n sequential in this synchronous sequence carried out:
Read an address value;
This address value is decoded; And
The data of retrieval and this region data bus-bar in a zone that conforms to by the address that decode operation provided.
3, the sequential control method of synchronous memory body according to claim 2, after it is characterized in that wherein this address value being finished to decode, in this non-region data bus-bar preliminary filling sequential, an one a region data is to place this region data bus-bar, and it is to finish in the decode cycle in this address value that sequential is selected by delegation.
4, the sequential control method of synchronous memory body according to claim 1, it is characterized in that wherein this a uri information amplified bus-bar by this signal to be sent to after this uri information bus-bar, more comprises in this a uri information of temporary transient storage this working storage in this synchronous memory body.
5, the sequential control method of synchronous memory body according to claim 4, it is characterized in that wherein by after temporary a the uri information of this working storage, more be included in n+2 the sequential in this synchronous sequence, send this a uri information by this working storage.
6, the sequential control method of synchronous memory body according to claim 1, when it is characterized in that wherein this a+1 region data being placed in this region data bus-bar, it is right to need a signal development time that this a+1 region data formed a+1 region data.
7, the sequential control method of synchronous memory body according to claim 6 is characterized in that wherein the length of this signal development time is that this a non-region data bus-bar preliminary filling sequential and a non-uri information transmit periodic transformation transmits the cycle for this uri information the time interval for this region data bus-bar preliminary filling timing transition.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB031540007A CN1296831C (en) | 2003-08-22 | 2003-08-22 | Sequential controlling method for synchronous memory |
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| CNB031540007A CN1296831C (en) | 2003-08-22 | 2003-08-22 | Sequential controlling method for synchronous memory |
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| CN1584853A CN1584853A (en) | 2005-02-23 |
| CN1296831C true CN1296831C (en) | 2007-01-24 |
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Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101246442B (en) * | 2007-02-12 | 2011-05-25 | 南亚科技股份有限公司 | Memory body access control method |
| CN104252429B (en) | 2014-09-03 | 2017-05-17 | 英业达科技有限公司 | Storage control device and method for calling its address |
| TWI554891B (en) * | 2014-09-05 | 2016-10-21 | 英業達股份有限公司 | Storage control devices and method therefor to invoke address thereof |
Citations (4)
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|---|---|---|---|---|
| US5787457A (en) * | 1996-10-18 | 1998-07-28 | International Business Machines Corporation | Cached synchronous DRAM architecture allowing concurrent DRAM operations |
| JPH117764A (en) * | 1997-04-25 | 1999-01-12 | Hyundai Electron Ind Co Ltd | Synchronous dram |
| CN1233019A (en) * | 1998-04-17 | 1999-10-27 | 摩托罗拉公司 | Synchronous pipelined burst memory and method for operating same |
| US6253298B1 (en) * | 1995-02-21 | 2001-06-26 | Micron Technology, Inc. | Synchronous SRAM having pipelined enable |
-
2003
- 2003-08-22 CN CNB031540007A patent/CN1296831C/en not_active Expired - Lifetime
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6253298B1 (en) * | 1995-02-21 | 2001-06-26 | Micron Technology, Inc. | Synchronous SRAM having pipelined enable |
| US5787457A (en) * | 1996-10-18 | 1998-07-28 | International Business Machines Corporation | Cached synchronous DRAM architecture allowing concurrent DRAM operations |
| JPH117764A (en) * | 1997-04-25 | 1999-01-12 | Hyundai Electron Ind Co Ltd | Synchronous dram |
| CN1233019A (en) * | 1998-04-17 | 1999-10-27 | 摩托罗拉公司 | Synchronous pipelined burst memory and method for operating same |
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