CN1294327A - Circuit for generating programmable frequency and diflective phase-locked loop clock - Google Patents
Circuit for generating programmable frequency and diflective phase-locked loop clock Download PDFInfo
- Publication number
- CN1294327A CN1294327A CN 99123241 CN99123241A CN1294327A CN 1294327 A CN1294327 A CN 1294327A CN 99123241 CN99123241 CN 99123241 CN 99123241 A CN99123241 A CN 99123241A CN 1294327 A CN1294327 A CN 1294327A
- Authority
- CN
- China
- Prior art keywords
- output terminal
- signal
- input
- input end
- clock
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
A frequency and deflection programmed phase-locked loop (PLL) timer generator is disclosed. The frequency and deflection of signal can be programmed for dynamic variation to compensate the clock signal deflection caused by load variation. A closed-loop PLL timer generator is used to effectively control the clock signal deflection in digital system (computer, for example) for stable running.
Description
The invention relates to a kind of clock generation circuit, and particularly produce circuit relevant for the pll clock of a kind of programmable frequency and skew.
Along with the progress of semiconductor technology, the operation frequency of digital circuitry is more and more higher now, an important topic that becomes system designer synchronously of clock (clock) signal.About the stationary problem of system clock, synchronization of clock signals problem just not usually, and involve between a plurality of clock signals synchronously.Traditional clock signal skew (skew) is by clock signal generator and load decision, that is it is an open loop (open loop), long more when the path that the clock signal is delivered to load by clock signal, or load is when increasing, and the signal bias meeting becomes more serious.For example computer motherboard is a splendid example, the same clock signal of the common use of many devices is arranged on computer motherboard, and the storer on the computer motherboard can change with user's demand, in addition, also there are many peripheral device slots that required various peripheral interfaces can be installed with the need, therefore the quantity that changes storer and peripheral interface all can change the load of clock signal, so provide clock signal in the mode of open loop, the problem of suitable refractory signal skew.On the other hand, need to change the frequency of some clock signals sometimes, if all clock signals all provide by the clock signal generator of outside because reset (reset) afterwards in system, the frequency of clock signal promptly immobilizes, and unlikely optionally changes the frequency of clock signal.
As shown in Figure 1, be the synoptic diagram of known clock signal framework.As shown in the figure, system architecture with a computer motherboard is an example, in this circuit, provide system required all clock signal C PU_CLK and SYS_CLK by single clock signal generator 150, wherein clock signal C PU_CLK provides CPU 110 and wafer set (chipset) 120, and clock signal SYS_CLK then provides wafer set 120 and uses through bus (bus) 130 supplying apparatus 141～14N.Because wafer set 120 is integration wafers of the control circuit of whole computer motherboard, so wafer set 120 needs reference clock signal CPU_CLK and SYS_CLK.Device 141～the 14N that wherein sees through the bus connection can be the device of peripheral interface and so on, because the peripheral interface of different quantity can be installed on computer motherboard, therefore the load meeting of clock signal SYS_CLK changes with the peripheral interface quantity of installing, therefore also will influence its signal bias, and when the situation of signal bias is serious, will influence the degree of stability of total system.
If provide a plurality of clock signals in the inside of wafer set, use in order to the circuit that is provided itself and other devices of system, the system designer skew situation of control clock signal effectively then, and can make system have better stability and tolerance.Can dynamically change the frequency of signal on the other hand via sequencing control.
Comprehensive above-mentioned discussion, known as can be known clock signal generating circuit has following shortcoming:
1. the clock signal generator by the outside provides system required clock signal, and the frequency of the clock signal that is provided is not easy to change, and especially can not dynamically change the frequency of signal with sequencing.
2. the mode of use open loop provides the clock signal of system, along with the load variations of clock signal in the system, is difficult to the skew situation of control clock signal, will influence the stability of system.
Therefore the fundamental purpose of the present invention pll clock that provides a kind of programmable frequency produces circuit, uses the clock generation circuit of PLL mode, can sequencing dynamically changes the frequency of signal.
The pll clock that another object of the present invention provides the skew of a kind of programmable produces circuit, uses the clock generation circuit of closed loop (close loop) mode of PLL, can sequencing dynamically adjusts the skew of signal.
For reaching above-mentioned and other purposes of the present invention, the pll clock that the present invention proposes a kind of programmable frequency and skew produces circuit, in order to produce a clock signal according to a reference signal, this clock circuit comprises a plurality of first delay elements, first traffic pilot, a plurality of second delay element, second traffic pilot, reaches the PLL signal generating circuit.
Wherein each this first delay element has one first end and two end points of one second end, those first delay elements connect in the serial connection mode, be first end that second end of previous first delay element is connected to back one first delay element, and first end of first first delay element is coupled to this reference signal.
This first traffic pilot has a plurality of input ends and an output terminal, each this input end is coupled to second end and this reference signal of each this first delay element respectively, and accept one first control of selecting signal, in order to select that one of those input ends are connected to this output terminal.
Each this second delay element has one first end and two end points of one second end, those second delay elements connect with series system, be first end that second end of previous second delay element is connected to back one second delay element, and first end of first second delay element is coupled to a feedback signal.
This second traffic pilot has a plurality of input ends and an output terminal, each this input end is coupled to second end and this feedback signal of each this second delay element respectively, and accept one second control of selecting signal, in order to select that one of those input ends are connected to this output terminal.
This PLL signal generating circuit has a first input end, one second input end, reaches an output terminal, this first input end is coupled to the output terminal of this first traffic pilot, this second input end is coupled to the output terminal of this second traffic pilot, this output terminal is exported this clock signal, and this clock signal is sent this feedback signal back to through a lead.
According to a preferred embodiment of the present invention, this clock signal is coupled to a circuit arrangement in half of this lead, for the reference clock of this circuit arrangement as running.
The PLL signal generating circuit that above-mentioned pll clock produces in the circuit comprises a plurality of first dividers, the 3rd traffic pilot, a plurality of second divider, the 4th traffic pilot, PLL core circuit, a plurality of the 3rd divider, reaches the 5th traffic pilot.
Wherein the input end of each this first divider is coupled to the output terminal of this first traffic pilot through this first end.The 3rd traffic pilot has a plurality of input ends and an output terminal, and each input end is accepted the output of each this first divider respectively, and accepts the control of one the 3rd selection signal, in order to select that one of those input ends are connected to this output terminal.
The input end of each this second divider is coupled to the output terminal of this second traffic pilot through this second input end.The 4th traffic pilot has a plurality of input ends and an output terminal, and each input end is accepted the output of each this second divider respectively, and accepts the control of one the 4th selection signal, in order to select that one of those input ends are connected to this output terminal.
This PLL core circuit has a reference input, a back coupling input end, reaches an output terminal, the signal that this PLL core circuit is produced by this output terminal according to this reference input and this signal phase difference of feedbacking input end, this reference input is coupled to the output terminal of the 3rd traffic pilot, and this back coupling input end is coupled to the output terminal of the 4th traffic pilot.
The input end of each the 3rd divider is coupled to the output terminal of this PLL core circuit.The 5th traffic pilot has a plurality of input ends and an output terminal, and each input end is accepted the output of each the 3rd divider respectively, and this output terminal is exported this clock signal.
For above-mentioned and other purposes of the present invention, feature and advantage can be become apparent, a preferred embodiment cited below particularly, and conjunction with figs. are described in detail below.
Brief Description Of Drawings:
Fig. 1 is the synoptic diagram of known clock signal framework;
Fig. 2 is the block scheme of the PLL signal generating circuit of programmable frequency of the present invention;
Fig. 3 is the block scheme that the pll clock of programmable frequency and skew produces circuit;
Fig. 4 is that pll clock produces circuit application in the synoptic diagram of a computer motherboard system.
Please refer to Fig. 2, it illustrates the block scheme according to the PLL signal generating circuit of a kind of programmable frequency of a preferred embodiment of the present invention, and PLL signal generating circuit 200 can produce the clock signal clk 2 of variable frequency according to reference signal REF_CLK.
As shown in the figure, PLL signal generating circuit 200 comprises divider 211～21N, traffic pilot 220, divider 231～23N, traffic pilot 240, PLL core (core) circuit 250, divider 261～26N, traffic pilot 270, reaches traffic pilot 280.
Wherein reference signal REF_CLK delivers to the input end of divider 211～21N, each divider respectively with the input reference signal REF_CLK divided by different ratios.Reference signal REF_CLK is after divider 211～21N is divided by different ratios, deliver to the input end of traffic pilot 220 respectively, and traffic pilot 220 accepts to select the control of signal REF_SEL, in order to select that one of those input ends are connected to output terminal, with the signal REF_CLK ' of generation different frequency, so the ratio between reference signal REF_CLK and the signal REF_CLK ' can be via selecting signal REF_SEL select.
The input end of divider 231～23N is all accepted feedback signal FB_CLK, with feedback signal FB_CLK divided by different ratios.Feedback signal FB_CLK is after divider 231～23N is divided by different ratios, deliver to the input end of traffic pilot 240 respectively, and traffic pilot 240 accepts to select the control of signal FB_SEL, in order to select that one of those input ends are connected to output terminal, with generation signal FB_CLK ', so the ratio between feedback signal FB_CLK and the signal FB_CLK ' can be via selecting signal FB_SEL select.
The major function of whole PLL circuit is responsible for reaching by PLL core circuit (PLL core) 250, PLL core circuit 250 has reference input R_IN, back coupling input end F_IN, reaches output terminal PO, wherein signal REF_CLK ' delivers to the reference input R_IN of PLL core circuit 250, signal FB_CLK ' delivers to the back coupling input end F_IN of PLL core circuit 250, the output terminal PO output signal CLK of PLL core circuit 250.PLL core circuit 250 can reduce signal REF_CLK ' and the phase differential of signal FB_CLK ' according to frequency and the phase place of signal REF_CLK ' with phase place (phase) the difference change output signal CLK of signal FB_CLK ' as far as possible.
The signal CLK that PLL core circuit 250 output terminal PO produce delivers to the input end of divider 261～26N, and signal CLK delivers to the input end of traffic pilot 270 and traffic pilot 280 respectively after output divider 261～26N is divided by different ratios.And traffic pilot 280 accepts to select the control of signal SEL, and in order to select that one of those input ends are connected to this output terminal, to produce clock signals of different frequencies CLK2, clock signal clk 2 can use for circuit external.
The output terminal of traffic pilot 270 is sent signal CLK1, and signal CLK1 is delivered to the back coupling input end F_IN of PLL core circuit 250 as feedback signal FB CLK via divider 231～23N and traffic pilot 240, constitutes the phase-locked loop of a sealing.The purpose of traffic pilot 270 does not really want to select the feedback signal of different frequency, but in order to make signal CLK1 consistent as far as possible with the time delay of CLK2, with the skew of control signal.
According to above PLL signal generating circuit 200, under situation by the reference signal REF_CLK of the outside fixed frequency that provides, can be via selecting signal REF_SEL, FB_SEL, and the frequency of SEL setting clocking CLK2.The frequency of hypothetical reference signal REF_CLK is fr, and by selecting signal REF_SEL to determine that the ratio between reference signal REF_CLK and the signal REF_CLK ' is N, by selecting signal FB_SEL to determine that the ratio between feedback signal FB_CLK and the signal FB_CLK ' is D, the fixed ratio of synchronous signal CLK and CLK1 is 1, and the frequency of controlling the signal CLK that is produced via the closed loop of PLL signal generating circuit 200 is f
r *N/D.280 of traffic pilots can be selected clock signals of different frequencies CLK2, and can increase a plurality of traffic pilots, use for different circuit with the clock signal that multiple frequency is provided.
Can produce clock signals of different frequencies via above PLL signal generating circuit 200, will do discussion at signal bias control with next.
Please refer to Fig. 3, its illustrate is the block scheme of the pll clock generation circuit of a kind of programmable frequency and skew (skew), and pll clock produces circuit 300 in order to produce a clock signal CLK1 according to a reference signal REF_CLK 0, uses so that external circuit to be provided.
As shown in the figure, pll clock generation circuit 300 comprises delay element 311～31N, traffic pilot 320, delay element 331～33N, traffic pilot 340, reaches PLL signal generating circuit 200.
Delay element 311～31N links together in the serial connection mode, and reference signal FEF_CLK 0 is coupled to the input endpoint of first delay element 311.Traffic pilot 320 has a plurality of input ends and an output terminal, each input end is coupled to output terminal and the reference signal REF_CLK0 of delay element 311～31N respectively, and traffic pilot 320 accepts to select the control of signal S1, in order to select that one of those input ends are connected to output terminal, to produce the signal REF_CLK of different time delays, again signal REF_CLK is delivered to PLL signal generating circuit 200.
As the connected mode of reference signal input end, delay element 331～33N links together in the serial connection mode, and feedback signal FB_CLK 0 is coupled to the input endpoint of first delay element 331.Traffic pilot 340 has a plurality of input ends and an output terminal, each input end is coupled to output terminal and the feedback signal FB_CLK0 of delay element 331～33N respectively, and traffic pilot 340 accepts to select the control of signal S2, in order to select that one of those input ends are connected to output terminal, to produce the reference signal FB_CLK of different time delays, again signal FB_CLK is delivered to PLL signal generating circuit 200.
The inside structure of PLL signal generating circuit 200 is the block scheme that Fig. 2 illustrates, PLL signal generating circuit 200 has reference input, back coupling input end, reaches output terminal, reference input is coupled to the output terminal of traffic pilot 320, accept the signal REF_CLK of its output, the back coupling input end is coupled to the output terminal of traffic pilot 340, accept the signal FB_CLK of its output, output terminal clock signal CLK1, and clock signal clk 1 is sent feedback signal FB_CLK 0 back to through lead 350.As previously mentioned, PLL signal generating circuit 200 can be according to setting, and produce output signal CLK 1 according to the relation of reference signal REF_CLK and feedback signal FB_CLK so that the reference input R_IN of the PLL core circuit 250 in the PLL signal generating circuit 200 with feedback the phase differential of signal REF_CLK ' and signal FB_CLK ' of input end F_IN and reduce as far as possible.
Lead 350 is the path of institute's warp on the circuit board, in order to consider the signal delay that routing path caused of circuit board, for so the skew of control signal is sent the back coupling end that pll clock produces circuit 300 back to just clock signal clk 1 is a lead 350 on circuit board.
Produce circuit 300 according to above-mentioned pll clock, can be via the control of selecting signal S1 and S2, adjust the time delay of the insertion between reference signal REF_CLK 0 and REF_CLK and feedback signal FB_CLK 0 and the FB_CLK, thus the skew of control output signal CLK 1.
Please refer to Fig. 4, its illustrate produces circuit application in the synoptic diagram of a computer motherboard system into pll clock.
As shown in the figure, have pll clock among the wafer set 420 and produce circuit 421 and 422, reference signal generation circuit 450 generation reference signal SREF by the outside give wafer set 420, again by the pll clock in the wafer set 420 produce circuit 421 and 422 provide respectively clock signal C PU_CLK to CPU410 and clock signal SYS_CLK to bus 430, wherein clock signal SYS_CLK provides multiple arrangement to use through bus 430 again, for example installs 441～44N.Wherein pll clock produces circuit 421 and 422 structure promptly as shown in Figure 3 block scheme is the same, and all with reference to reference signal SREF by reference signal generation circuit 450 outputs, pll clock produces circuit 421 and 422 can set its frequency and skew respectively, to produce needed frequency, and adjust its side-play amount, so that minimum is reduced in the skew between two clocks.In order to make the signal of delivering to load can fully be reflected into feedback signal, therefore by output terminal half taking-up feedback signal to the total length lead of load, the skew of therefore sending the feedback signal of back coupling end back to will be consistent with the skew of delivering to load.For example, clock signal C PU_CLK delivers to CPU410 via lead 461, and its feedback signal is then taken out and sent back to pll clock through lead 462 by point among the lead 461 and produces circuit 421.Clock signal SYS_CLK then delivers to bus 430 through lead 471, and feedback signal is then sent pll clock generation circuit 422 back to by the suitable some taking-up of bus 430 and through lead 472.
Therefore as above-mentioned computer motherboard, can adjust the frequency of CPU CLK by the running speed of CPU 410, and the frequency of adjusting SYS_CLK by the running speed of system, and the actual range of visual CPU 410 and wafer set 420 is adjusted the skew of CPU_CLK, and by the load variations that connects on the bus 430, that is the device quantity that connects, adjust the skew of clock signal SYS_CLK.The skew of the clock signal of delivering to CPU and each device is minimized.
Therefore produce circuit via above pll clock of the present invention, this pll clock produces circuit and can be included within the wafer set on the computer motherboard, and provide system required clock signal through wafer set thus, and signal bias can obtain good control via the closed loop framework that pll clock produces circuit.In addition, can be according to different conditions, adjust the skew of signal with program, when more memory module for example being installed or plugging more interface card, make signal load increase, and make skew become big, at this moment, can increase the time delay of reference clock importation, with the variation of compensating signal skew.And, need not change the setting of the jumper switch (jumper) on the motherboard by the user with manual mode, can be by (the Basic Input Output System of the Basic Input or Output System (BIOS) in the computer system, abbreviation BIOS) program detects the variation situation of load automatically, changes offset setting automatically.
From above discussion, the pll clock of programmable frequency of the present invention as can be known and skew produces circuit and the known practice compares, and has following advantage:
1. producing circuit by pll clock provides system required clock signal, can sequencing dynamically changes the frequency of signal.
2. use the pll clock of closed loop mode to produce circuit, the effective problem that is offset of control signal, and can sequencing dynamically adjust the skew of signal.
Though the present invention discloses as above with a preferred embodiment; right its is not in order to limiting the present invention, anyly has the knack of this skill person, without departing from the spirit and scope of the present invention; when the change that can do a little and retouching, so protection scope of the present invention is as the criterion when looking the accompanying Claim person of defining.
Claims (6)
1. the pll clock of a programmable frequency produces circuit, in order to produce a clock signal according to a reference signal, it is characterized in that this pll clock produces circuit and comprises:
A plurality of first dividers, the input end of each this first divider is accepted this reference signal;
One first traffic pilot has a plurality of input ends and an output terminal, and each input end is accepted the output of each this first divider respectively, and accepts the control of one first selection signal, in order to select that one of those input ends are connected to this output terminal;
A plurality of second dividers, the input end of each this second divider is accepted a feedback signal;
One second traffic pilot has a plurality of input ends and an output terminal, and each input end is accepted the output of each this second divider respectively, and accepts the control of one second selection signal, in order to select that one of those input ends are connected to this output terminal;
One PLL core circuit, have a reference input, a back coupling input end, reach an output terminal, this PLL core circuit produces a signal according to the signal phase difference of this reference input and this back coupling input end by this output terminal, this reference input is coupled to the output terminal of this first traffic pilot, and this back coupling input end is coupled to the output terminal of this second traffic pilot;
A plurality of the 3rd dividers, the input end of each the 3rd divider is coupled to the output terminal of this PLL core circuit;
One the 3rd traffic pilot has a plurality of input ends and an output terminal, and each input end is accepted the output of each the 3rd divider respectively, and this output terminal is exported this feedback signal; And
One the 4th traffic pilot, have a plurality of input ends and an output terminal, each input end is accepted the output of each the 3rd divider respectively, and accepts the control of one the 3rd selection signal, in order to select that one of those input ends are connected to this output terminal, this output terminal is exported this clock signal.
2. the pll clock of programmable frequency and skew produces circuit, in order to produce a clock signal according to a reference signal, it is characterized in that this clock circuit comprises:
A plurality of first delay elements, each this first delay element has one first end and two end points of one second end, those first delay elements connect in the serial connection mode, be first end that second end of previous first delay element is connected to back one first delay element, and first end of first first delay element is coupled to this reference signal;
One first traffic pilot, have a plurality of input ends and an output terminal, each this input end is coupled to second end and this reference signal of each this first delay element respectively, and accepts the control of one first selection signal, in order to select that one of those input ends are connected to this output terminal;
A plurality of second delay elements, each this second delay element has one first end and two end points of one second end, those second delay elements connect in the serial connection mode, be first end that second end of previous second delay element is connected to back one second delay element, and first end of first second delay element is coupled to a feedback signal;
One second traffic pilot, have a plurality of input ends and an output terminal, each this input end is coupled to second end and this feedback signal of each this second delay element respectively, and accepts the control of one second selection signal, in order to select that one of those input ends are connected to this output terminal; And
One PLL signal generating circuit, have a first input end, one second input end, reach an output terminal, this first input end is coupled to the output terminal of this first traffic pilot, this second input end is coupled to the output terminal of this second traffic pilot, this output terminal is exported this clock signal, and this clock signal is sent this feedback signal back to through a lead.
3. the pll clock with programmable frequency and skew as claimed in claim 2 produces circuit, it is characterized in that this clock signal is coupled to a circuit arrangement in half of this lead, for the reference clock of this circuit arrangement as running.
4. the pll clock with programmable frequency and skew as claimed in claim 2 produces circuit, it is characterized in that this PLL signal generating circuit comprises:
A plurality of first dividers, the input end of each this first divider are coupled to the output terminal of this first traffic pilot through this first end;
One the 3rd traffic pilot has a plurality of input ends and an output terminal, and each input end is accepted the output of each this first divider respectively, and accepts the control of one the 3rd selection signal, in order to select that one of those input ends are connected to this output terminal;
A plurality of second dividers, the input end of each this second divider are coupled to the output terminal of this second traffic pilot through this second input end;
One the 4th traffic pilot has a plurality of input ends and an output terminal, and each input end is accepted the output of each this second divider respectively, and accepts the control of one the 4th selection signal, in order to select that one of those input ends are connected to this output terminal;
One PLL core circuit, have a reference input, a back coupling input end, reach an output terminal, this PLL core circuit produces a signal according to the signal phase difference of this reference input and this back coupling input end by this output terminal, this reference input is coupled to the output terminal of the 3rd traffic pilot, and this back coupling input end is coupled to the output terminal of the 4th traffic pilot;
A plurality of the 3rd dividers, the input end of each the 3rd divider is coupled to the output terminal of this PLL core circuit; And
One the 5th traffic pilot has a plurality of input ends and an output terminal, and each input end is accepted the output of each the 3rd divider respectively, and this output terminal is exported this clock signal.
5. the pll clock of a programmable skew produces circuit, in order to produce a clock signal according to a reference signal, it is characterized in that this clock circuit comprises:
A plurality of first delay elements, each this first delay element has one first end and two end points of one second end, those first delay elements connect in the serial connection mode, be first end that second end of previous first delay element is connected to back one first delay element, and first end of first first delay element is coupled to this reference signal;
One first traffic pilot, have a plurality of input ends and an output terminal, each this input end is coupled to second end and this reference signal of each this first delay element respectively, and accepts the control of one first selection signal, in order to select that one of those input ends are connected to this output terminal;
A plurality of second delay elements, each this second delay element has one first end and two end points of one second end, those second delay elements connect in the serial connection mode, be first end that second end of previous second delay element is connected to back one second delay element, and first end of first second delay element is coupled to a feedback signal;
One second traffic pilot, have a plurality of input ends and an output terminal, each this input end is coupled to second end and this feedback signal of each this second delay element respectively, and accepts the control of one first selection signal, in order to select that one of those input ends are connected to this output terminal; And
One PLL signal generating circuit, have a first input end, one second input end, reach an output terminal, this first input end is coupled to the output terminal of this first traffic pilot, this second input end is coupled to the output terminal of this second traffic pilot, this PLL signal generating circuit produces this clock signal according to the signal relation of this first input end and this second input end by this output terminal, and this clock signal is sent this feedback signal back to through a lead.
6. the pll clock with programmable skew as claimed in claim 5 produces circuit, and this clock signal is coupled to a circuit arrangement in half of this lead, for the reference clock of this circuit arrangement as running.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 99123241 CN1202450C (en) | 1999-10-28 | 1999-10-28 | Circuit for generating programmable frequency and diflective phase-locked loop clock |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 99123241 CN1202450C (en) | 1999-10-28 | 1999-10-28 | Circuit for generating programmable frequency and diflective phase-locked loop clock |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1294327A true CN1294327A (en) | 2001-05-09 |
| CN1202450C CN1202450C (en) | 2005-05-18 |
Family
ID=5282849
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 99123241 Expired - Lifetime CN1202450C (en) | 1999-10-28 | 1999-10-28 | Circuit for generating programmable frequency and diflective phase-locked loop clock |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1202450C (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100340941C (en) * | 2002-12-06 | 2007-10-03 | 哉英电子股份有限公司 | Frequency modulator apparatus of phase selection type, and frequency synthesizer of phase selection type |
| CN100362522C (en) * | 2006-03-31 | 2008-01-16 | 北京飞天诚信科技有限公司 | Real time clock correcting method in soft ware protecter |
| CN100371850C (en) * | 2004-12-17 | 2008-02-27 | 华为技术有限公司 | Method for realizing compatibility of different clock circuits on printed circuit board |
| US7411906B2 (en) | 2003-04-29 | 2008-08-12 | Via Technologies, Inc. | Method for optimizing frequency of clock signal and network switch using same |
| CN101419483B (en) * | 2008-11-27 | 2010-07-07 | 华亚微电子（上海）有限公司 | Clock generator based on phase-locked loop and clock generating method |
| CN101729063B (en) * | 2008-10-16 | 2012-05-30 | 北京兆易创新科技有限公司 | Delay phase locked loop circuit and method for adjusting output clock signal phase |
| CN106067288A (en) * | 2015-04-22 | 2016-11-02 | 联发科技股份有限公司 | The method and apparatus adjusting the skew of virtual period timing control signal |
-
1999
- 1999-10-28 CN CN 99123241 patent/CN1202450C/en not_active Expired - Lifetime
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100340941C (en) * | 2002-12-06 | 2007-10-03 | 哉英电子股份有限公司 | Frequency modulator apparatus of phase selection type, and frequency synthesizer of phase selection type |
| US7411906B2 (en) | 2003-04-29 | 2008-08-12 | Via Technologies, Inc. | Method for optimizing frequency of clock signal and network switch using same |
| CN100371850C (en) * | 2004-12-17 | 2008-02-27 | 华为技术有限公司 | Method for realizing compatibility of different clock circuits on printed circuit board |
| CN100362522C (en) * | 2006-03-31 | 2008-01-16 | 北京飞天诚信科技有限公司 | Real time clock correcting method in soft ware protecter |
| CN101729063B (en) * | 2008-10-16 | 2012-05-30 | 北京兆易创新科技有限公司 | Delay phase locked loop circuit and method for adjusting output clock signal phase |
| CN101419483B (en) * | 2008-11-27 | 2010-07-07 | 华亚微电子（上海）有限公司 | Clock generator based on phase-locked loop and clock generating method |
| CN106067288A (en) * | 2015-04-22 | 2016-11-02 | 联发科技股份有限公司 | The method and apparatus adjusting the skew of virtual period timing control signal |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1202450C (en) | 2005-05-18 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6587534B2 (en) | Delay lock loop with clock phase shifter | |
| US6687320B1 (en) | Phase lock loop (PLL) clock generator with programmable skew and frequency | |
| JP2636677B2 (en) | Semiconductor integrated circuit | |
| US6788156B2 (en) | Adaptive variable frequency clock system for high performance low power microprocessors | |
| US20020079937A1 (en) | Digital delay locked loop with wide dynamic range and fine precision | |
| US7650521B2 (en) | Semiconductor integrated circuit having a first power supply region and a second power supply region in which power supply voltage changes | |
| US7308592B2 (en) | Redundant oscillator distribution in a multi-processor server system | |
| US6944780B1 (en) | Adaptive voltage scaling clock generator for use in a digital processing component and method of operating the same | |
| US8170168B2 (en) | Clock data recovery circuit | |
| EP0929155A2 (en) | Coupled phase locked loops | |
| KR19980086434A (en) | Clock Generation Circuits and Semiconductor Devices | |
| US6466073B1 (en) | Method and circuitry for generating clock | |
| JP2000101425A (en) | Delayed synchronization loop circuit of semiconductor memory device and control method for the same | |
| US6999547B2 (en) | Delay-lock-loop with improved accuracy and range | |
| US5638019A (en) | Accurately generating precisely skewed clock signals | |
| CN1202450C (en) | Circuit for generating programmable frequency and diflective phase-locked loop clock | |
| KR20040050539A (en) | Delay time compensation circuit with delay cells having various unit delay time | |
| US6777990B2 (en) | Delay lock loop having an edge detector and fixed delay | |
| WO1995030947A1 (en) | High precision clock distribution circuits | |
| US6653875B2 (en) | Method and apparatus for a delay lock loop | |
| EP1618461B1 (en) | Deskew system in a clock distribution network using a pll and a dll | |
| US6271696B1 (en) | Phase adjustment circuit | |
| US6977539B1 (en) | Clock signal generators having programmable full-period clock skew control and methods of generating clock signals having programmable skews | |
| KR20030010467A (en) | Semiconductor integrated circuit device | |
| JP4553428B2 (en) | Phase-locked loop (PLL) clock generator with programmable offset and frequency |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| BB1A | Publication of application | ||
| C06 | Publication | ||
| PB01 | Publication | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term | ||
| CX01 | Expiry of patent term |
Granted publication date: 20050518 |