CN1293614C - Method for improving interface kink between pure silicate glass and phosphorosilicate glass and phosphor containing structure thereof - Google Patents
Method for improving interface kink between pure silicate glass and phosphorosilicate glass and phosphor containing structure thereof Download PDFInfo
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- CN1293614C CN1293614C CNB031484484A CN03148448A CN1293614C CN 1293614 C CN1293614 C CN 1293614C CN B031484484 A CNB031484484 A CN B031484484A CN 03148448 A CN03148448 A CN 03148448A CN 1293614 C CN1293614 C CN 1293614C
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Abstract
The present invention discloses a method for overcoming the interface kink of pure silicon dioxide (USG) and phosphosilicate glass (PSG). The flow quantity of phosphine is increased in stages from 0 until a final set value so as to slowly lead out residual phosphine on a valve port of a flow controller, and thus, the overshooting of the phosphine is avoided so as to overcome the interface kink of the USG and the PSG, wherein the flow quantity of phosphine (PH3) gas is increased in stages according to arithmetic progressions, geometric progressions or irregular modes. The phosphorus content of the interface layer containing phosphorus positioned between a USG layer and a PSG layer is increased by 100% from 0% in stages, and the total thickness of the interface layer containing phosphorus is at least larger than 100*.
Description
Technical Field
The present invention relates to a method for improving the interface defect between pure silica glass (USG) and phosphosilicate glass (PSG) and a phosphorus-containing structure formed by the method, and more particularly, to a method for improving the interface defect between USG and PSG by controlling the flow of phosphine in a stepwise manner.
Background
Silicon is used in a wide variety of semiconductor manufacturing processes. Many materials commonly used in manufacturing processes, whether conductive, semiconductive, or dielectric, are associated with the element "silicon". Such as tungsten silicide in a conductor (WSi)x) Tungsten (W) and titanium (Ti), polysilicon in semiconductors, and silicon dioxide (SiO) in dielectric materials2) And silicon nitride (Si)3N4) Etc. are derived on the basis of "silicon". Taking dielectric materials (dielectrics) as an example, Undoped Silicate Glass (USG), Phospho-silicate glass (PSG) and borophosphosilicate glass (BPSG) are the most widely used dielectric materials at present.
Referring to fig. 1, a schematic diagram of a location of a silicon element applied to a mos transistor is shown. In a Metal-Oxide-Semiconductor Transistor (MOS) 100, a Transistor Gate (Gate) on a silicon substrate 102 is formed of a Gate Oxide (Gate Oxide)103, a Polysilicon (Polysilicon)104, and a tungsten silicide (WSi)x)106 are stacked. Generally, the silicon on the surface of the active region on the cleaned silicon substrate 102 is oxidized into a thickness of about 100 to 250A by dry oxidationAnd siliciding the gate oxide layer 103 to serve as a MOS. The polysilicon 104 formed on the gate oxide layer 103 has a thickness of about 2000-3000A. A metal silicide layer (typically tungsten silicide 106 is preferred) having a higher conductivity than polysilicon 104 is deposited over polysilicon 104. Since the adhesion of the metal silicide layer to the silicon dioxide is not good and interface compounds are easily generated, a polysilicon layer 104 is required to be added between the tungsten silicide 106 and the gate oxide layer 103, so that two layers of polysilicon 104 and tungsten silicide 106 are used as the gate conductive layer. In addition, a Spacer Oxide (Spacer Oxide)107 located on both sides of the gate conductive layer is also applied to the silicon element. Inter-Layer Dielectrics (110) before MOS metallization is made of phosphorus silicate glass(PSG)。
The right half of fig. 1 shows a contact structure provided in the MOS. The Contact for connecting the lower metal line 112 and the drain of the silicon substrate 102 to the source PN junction is called Contact metal or Contact Plug (Contact Plug)114, and the portion connecting the upper and lower metal lines is called Via Plug (Via Plug) (not shown). In the MOS process, a portion of the ild layer llO is typically etched to the Liner Oxide layer (Liner Oxide)108 and then filled with metal tungsten to form the tungsten plug. The substrate oxide layer 108 is a silicon oxide layer formed by oxidizing a silicon surface at a high temperature (about 900-1100 ℃) by dry oxygen to a thickness of about 200-400 angstroms, and is made of Undoped Silicate Glass (USG).
In the conventional MOS manufacturing process, when a portion of the interlayer dielectric layer 110 is etched to the substrate oxide layer 108, the interface (interface) between the two layers has a defect (interface k) after etching because the PSG has a high phosphorus content. The phosphorus content of the PSG at the interface of ild layer 1lO and substrate oxide layer 108 is related to the PSG formation process.
Phosphosilicate glass (PSG), a silica containing phosphorus. It can be used in the reaction for producing silicon dioxide by adding small amount of Phosphine (Phospholine, PH)3) And obtaining the compound. The reaction formula is as follows:
this reaction is generally carried out at Atmospheric Pressure and at a temperature of about 400 ℃, and is one application of Atmospheric Pressure Chemical Vapor Deposition (APCVD). The reaction can also be carried out in a low pressure environment using a plasma enhanced chemical vapor deposition process. Wherein Silane (SiH)4) Reacting with oxygen to generate silicon dioxide; and Phosphine (PH)3) Reacting with oxygen to form phosphorus oxide (P)205) And contained within a deposited film of silicon dioxide. As for the phosphorus content in PSG, the phosphorus content can be controlled by controlling the Phosphine (PH)3) Is regulated. Phosphine is typically passed through a Mass Flow Controller (MFC) whose by-pass valve arrangement (by-pass valve) is opened or closed to determine whether phosphine is added to the reaction.
However, due to Phosphine (PH)3) The gas has a relatively high viscosity and thus will have little side leakage if the valve means is closed after it has passed through the mass flow controller for a period of time. When phosphine gas is introduced again, the phosphine gas accumulated at the valve port originally is flushed out with the phosphine gas introduced later due to the opening of the valve device, so that an excess amount (overheating) is caused. Fig. 2A shows the reaction gas versus time in the conventional method for generating PSG by reaction. Wherein the ring part represents the occurrence of the over-dosage of phosphine gas. Referring to FIG. 2B, the phosphine content and the thickness of the deposited glass in FIG. 2A are shown. When phosphorus is presentHydrogen oxide gas not yet added to the reaction (i.e. phosphorus content 0%), Silane (SiH)4) And oxygen to produce pure silica, i.e., Undoped Silicate Glass (USG) 208. When phosphine gas is added to the reaction, a phosphosilicate glass (PSG)210 is formed. While the interface between USG 208 and PSG 210 (in excess of phosphine gas) produces PSG 212 with a higher phosphorus content. Such an over-dosing problem is exacerbated when the mass flow controller is deactivated for a period of time and then reactivated.
In subsequent processes, such as etching contacts in the PSG (fig. 1), the higher phosphorus content PSG 212 has lower hardness, which increases the etching rate, resulting in over-etching and formation of so-called Interface sink (Interface knk) therein, which affects the device characteristics. As shown in fig. 3, which is an electron micrograph of PSG after etching in a conventional process. In the electron micrographs (SEM micrographs), the dark lines are the depressions in the interface.
Disclosure of Invention
Accordingly, the present invention is directed to provide a method for improving interface defects between pure silicon dioxide (USG) and phosphosilicate glass (PSG), which gradually increases the flow rate of phosphine to a final set value to slowly bring out phosphine remaining at a valve port of a flow controller, thereby avoiding excessive phosphine (overheating) and further improving interface defects between the USG and the PSG.
To solve the above problems, the present invention provides a method for improving the interface defect between a pure silicon dioxide (USG) layer and a phosphosilicate glass (PSG) layer, wherein the PSG layer is deposited on the pure silicon dioxide layer, and Phosphine (PH) is adjusted by a flow control device3) Forming a phosphosilicate glass layer by the flow of the gas, and performing a Main deposition process (Main Dep), hydrogen Phosphide (PH)3) The flow rate of the gas needs to reach X sccm (X is a positive number more than 1), and the method of the invention comprises the following steps:
adding Phosphine (PH)3) The flow rate of the gas is increased stepwise from 0sccm until the flow rate reaches Xsccm.
Wherein, Phosphine (PH)3) The flow rate of the gas may be increased stepwise in an arithmetic progression (elementary progression), a geometric progression (geometric progression), or a random manner.
In addition, according to the invention, a phosphorus-containing interface layer is produced between the pure silicon dioxide (USG) layer and the phosphosilicate glass (PSG) layer, the phosphorus content of which increases stepwise from 0% to 100%, and the total thickness of the interface layer is at least greater than 100 ℃.
Drawings
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, preferred embodiments accompanied with figures are described in detail as follows:
FIG. 1 is a schematic diagram of a silicon device applied to a MOS transistor;
FIG. 2A is a graph of reaction gas versus time for the reaction to produce PSG in a conventional process;
FIG. 2B is a graphical representation of the phosphine gas content of FIG. 2A in relation to the thickness of the deposited glass;
FIG. 3 is an electron micrograph of PSG after etching in a conventional process;
FIG. 4A is a graph of reactant gases versus time for the reaction to produce PSG in the process of the present invention;
FIG. 4B is a graphical representation of the phosphine gas content of FIG. 4A as a function of deposited glass thickness;
FIG. 5 is an electron micrograph of PSG after etching using the method of the present invention.
Description of the reference numerals
102: silicon substrate
103: grid Oxide layer (Gate Oxide)
104: polycrystalline silicon (Polysilicon)
106: tungsten silicide (WSi)x)
107: spacer Oxide (Spacer Oxide)
108: substrate Oxide layer (Liner Oxide)
110: inner dielectric Layer (Inter-Layer Dielectrics)
112: lower metal wire
114: contact window Plug (Contact Plug)
208. 408: pure silicon glass (USG)
210. 410: phosphosilicate glass (PSG)
212. 412: PSG with higher phosphorus content
Detailed Description
The method of the invention is to add Phosphine (PH)3) The flow rate of the water is gradually increased from small to largeAnd the phenomenon of phosphorus excess (overheating) caused by the fact that the flow rate of phosphine reaches a set value (servo value) in the beginning in the traditional method is improved. The present invention will be described in detail with reference to a preferred embodiment.
The reaction formula for forming phosphosilicate glass (PSG) is as follows:
the reaction was carried out at normal pressure and the reaction temperature was about 400 ℃. The reaction can also be accomplished in a low pressure environment using a plasma enhanced chemical vapor deposition process. Wherein Silane (SiH)4) React with oxygenGenerating silicon dioxide; and Phosphine (PH)3) Reacting with oxygen to form phosphorus oxide (P)2O5) And contained within a deposited film of silicon dioxide. Phosphine is passed through a Mass Flow Controller (MFC), and the opening or closing of a by-pass valve (by-pass valve) determines whether phosphine is added to the reaction. Thus, the phosphorus content in the phosphosilicate glass (PSG) can be controlled by controlling the Phosphine (PH)3) Is regulated.
In a conventional manufacturing process, when deposition of phosphosilicate glass (PSG) is performed (hereinafter referred to as Main deposition (Main Dep)), if the flow rate of phosphine needs to reach 10sccm, a MassFlow Controller (MFC) is directly set at 10sccm, so that the phosphorous content is changed from 0 to 10sccm in a short time, and phosphine gas originally remaining in a valve port is taken out, resulting in an excess phosphorous content (overheating), as shown in fig. 2A and 2B. The test results show that: if the phosphorus content increases dramatically from 0 to 10sccm within 1 second, the interface thickness formed at the boundary between the USG and the PSG (i.e., the PSG 212 with the higher phosphorus content in FIG. 2B) is about 100. ANG.
In the present invention, when Main deposition (Main Dep.) is performed, if the flow rate of phosphine needs to reach 10sccm, a Mass Flow Controller (MFC) is set in stages, and the flow rate is gradually increased from 0 to 10 sccm. For example:
0sccm→2sccm→5sccm→10sccm
wherein, when the flow rate of phosphine is set to be 2sccm, the time is set to be 2 seconds; then, setting the flow rate of phosphine to be 5sccm for 4 seconds; finally, the phosphine flow is increased to 10sccm, and the main deposition step is performed. The test results show that: the interface formed at the interface of USG 408 and PSG 410 (i.e., PSG 412 with the higher phosphorus content in FIG. 4B) is about 600A thick.
By applying the method of the invention, the flow of phosphine is gradually increased in a staged manner, and phosphine gas originally remained at the valve port is gradually brought out, so as to avoid the excess (overheating) of phosphine caused by the traditional method. As shown in FIG. 4A, this figure is a graph of reaction gas versus time for the reaction to produce PSG in the process of the present invention. The excess of phosphine originally present in FIG. 4A is already moderate compared to FIG. 2A. Referring to FIG. 4B, the relationship between the phosphine gas content and the thickness of the deposited glass shown in FIG. 4A is shown. Silane (SiH) when phosphine gas has not been added to the reaction (i.e. phosphorus content 0%)4) And oxygen to form pure silica, i.e., Undoped Silicate Glass (USG) 408. When phosphine gas is added to the reaction, a phosphosilicate glass (PSG)410 is formed. And the junction of USG 408 and PSG 410 produces PSG 412 with higher phosphorus content. In comparison to fig. 2B, the PSG 412 with higher phosphorus content of the present invention has a greater thickness than the conventional PSG 212 with higher phosphorus content.
FIG. 5 is an electron micrograph of PSG after etching using the method of the present invention. The electron Micrograph (SEM Micrograph) of FIG. 5 shows that the phenomenon of Interface dishing (Interface Kink), which is a dark line as shown in FIG. 3, is not observed, and is improved by the method of the present invention.
Although the above description has been made by taking 0sccm-2sccm-5sccm-10sccm as an example, the method of the present invention is not limited to this set combination. Other combinations, such as 0sccm-2sccm-5sccm-8sccm-10sccm, or other combinations may also be used. The present invention is consistent with the technical features of the present invention, as long as the flow rate is increased to the set value of the main deposition process step by step, whether the set value is an arithmetic progression (arithmetic progression) mode, a geometric progression (geometric progression) mode, or a step-by-step increase without any special rules. If the time is slightly prolonged, the phenomenon of excessive phosphine can be further eliminated.
Before the phosphine flow reaches the final set value, the method of the invention increases the phosphine flow by stages or slightly prolongs the time, can slowly take out the residual phosphine at the valve port, avoids the phosphine surge phenomenon caused by flushing the phosphine out of the valve port in a short time, and further achieves the purpose of improving the interface defect of the USG substrate oxide and the PSG. Therefore, the method of the present invention can avoid the contact window from being cracked due to over etching, thereby improving the output of the device per unit time (WPH) in the semiconductor manufacturing process.
In summary, although the present invention has been disclosed in the preferred embodiments, it is not limited to the above embodiments, and any person skilled in the art can make various modifications and decorations without departing from the spirit and scope of the invention, therefore, the scope of the invention should be determined by the protection scope of the appended claims.
Claims (21)
1. A method for improving interface defect of pure silicon dioxide layer and phosphorus silicon glass layer, wherein, the phosphorus silicon glass layer is deposited on the pure silicon dioxide layer, a flow control device is used to adjust the flow of hydrogen phosphide gas to form the phosphorus silicon glass layer, when the main deposition process is carried out, the flow of hydrogen phosphide gas is required to reach Xsccm, wherein X is a positive number more than 1, wherein,
the flow rate of the phosphine gas is increased stepwise from 0sccm until the flow rate reaches Xsccm.
2. The method of claim 1, wherein the flow rate of phosphine gas is set to a1sccm, a2sccm, Xsccm in stages from 0sccm, and 0<a1<X/4, a2 being X/2.
3. The method according to claim 2, wherein the flow rate of the phosphine gas is 10sccm, and the flow rate of the phosphine gas is adjusted by the flow rate control means so that: 0sccm-2sccm-5sccm-10 sccm.
4. The method according to claim 3, wherein the holding time is 2 seconds when the flow rate of the phosphine gas is 2 sccm; when the flow rate of phosphine gas was 5sccm, the holding time was 4 seconds.
5. The method of claim 4, wherein the interface thickness of the pure silicon dioxide layer and the phosphosilicate glass layer is formed to be about 600 a.
6. The method of claim 1, wherein the flow rate of phosphine gas is set to a1sccm, a2sccm, a3sccm, Xsccm in stages from 0sccm, and 0<a1<X/4, a2 is X/2, X/2<a3<X.
7. The method of claim 1, wherein the flow rate of phosphine gas is set to a1sccm, a2sccm, a3sccm, Xsccm in a stepwise manner from 0sccm, and 0<a1<X/4, a2 is X/2, 3X/4<a3<X.
8. The method according to claim 7, wherein the flow rate of the phosphine gas is 10sccm, and the flow rate control means adjusts the flow rate of the phosphine gas to: 0sccm-2sccm-5sccm-8sccm-10 sccm.
9. The method of claim 1 wherein said flow control device is a mass flow controller.
10. A method for improving interface defect of pure silicon dioxide layer and phosphorus silicon glass layer, wherein, the phosphorus silicon glass layer is deposited on the pure silicon dioxide layer, a flow control device is used to adjust the flow of hydrogen phosphide gas to form the phosphorus silicon glass layer, when the main deposition process is carried out, the flow of hydrogen phosphide gas is required to reach Xsccm, wherein X is a positive number more than 1, wherein,
the flow rate of phosphine gas is increased from 0sccm to Xsccm in a stepwise manner, and the aeration time is increased as the gas flow rate is increased.
11. The method of claim 10, wherein the flow rate of phosphine gas is increased from 0sccm to Xsccm stepwise in a differential manner.
12. The method of claim 10, wherein the flow rate of phosphine gas is increased from 0sccm to Xsccm stepwise in an geometric progression.
13. The method of claim 10, wherein the flow rate of phosphine gas is increased to Xsccm in a random manner in steps starting from 0 sccm.
14. The method of claim 10 wherein said flow control device is a mass flow controller.
15. A phosphorus-containing interfacial layer at an interface between a pure silica layer and a phosphosilicate glass layer, wherein the phosphosilicate glass layer is deposited on top of the pure silica layer, and the phosphosilicate glass layer is formed by adjusting a flow rate of phosphine gas by a flow control device, the phosphorus-containing interfacial layer characterized by:
the phosphorus content of the phosphorus-containing interface layer increases stepwise from 0% to 100% in a cross section from the pure silicon dioxide layer to the phosphosilicate glass layer, and the total thickness of the phosphorus-containing interface layer is at least greater than 100.
16. The phosphorus-containing interfacial layer of claim 15, wherein the phosphoruscontent increases from 0% to 25% to 100% and the total thickness of the phosphorus-containing interfacial layer is at least greater than 100 a.
17. The phosphorus-containing interfacial layer according to claim 15, wherein the phosphorus content is increased stepwise from 0sccm to Xsccm by the flow rate control device, wherein the phosphorus content is increased to 100% at the Xsccm.
18. The phosphorus-containing interfacial layer of claim 17, wherein the flow of phosphine gas is increased from 0sccm to Xsccm in a stepwise manner in a manner of a differential order.
19. The phosphorus-containing interfacial layer of claim 17, wherein the flow rate of phosphine gas is increased from 0sccm to Xsccm in a stepwise manner in an geometric progression.
20. The phosphorus-containing interfacial layer of claim 17, wherein the flow of phosphine gas is increased from 0sccm to Xsccm in a random stepwise manner.
21. The phosphorus-containing interfacial layer of claim 17, wherein said flow control device is a mass flow controller.
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| CNB031484484A CN1293614C (en) | 2003-06-30 | 2003-06-30 | Method for improving interface kink between pure silicate glass and phosphorosilicate glass and phosphor containing structure thereof |
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| CNB031484484A CN1293614C (en) | 2003-06-30 | 2003-06-30 | Method for improving interface kink between pure silicate glass and phosphorosilicate glass and phosphor containing structure thereof |
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| CN101593724B (en) * | 2008-05-30 | 2012-04-18 | 中芯国际集成电路制造(北京)有限公司 | Method for forming via |
| CN103560080A (en) * | 2013-11-13 | 2014-02-05 | 上海华力微电子有限公司 | Method for reducing high-density plasma phosphorosilicate glass particles |
| CN105448706A (en) * | 2014-07-09 | 2016-03-30 | 中芯国际集成电路制造(上海)有限公司 | Boron phosphorous doped silicate glass (BPSG) dielectric layer preparation method, semiconductor device and electronic device |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0212916A (en) * | 1988-04-26 | 1990-01-17 | Siemens Ag | Manufacture of boron-doped and/or phosphorus-doped silicate glass layer for semiconductor super integrated circuit |
| JPH1050955A (en) * | 1996-07-31 | 1998-02-20 | Nec Corp | Manufacturing method of semiconductor device |
| JP2000058851A (en) * | 1998-08-17 | 2000-02-25 | Sanyo Electric Co Ltd | Thin film transistor, its manufacture, and display device |
| JP2000164885A (en) * | 1990-11-10 | 2000-06-16 | Semiconductor Energy Lab Co Ltd | Manufacture of insulated-gate type semiconductor device |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0212916A (en) * | 1988-04-26 | 1990-01-17 | Siemens Ag | Manufacture of boron-doped and/or phosphorus-doped silicate glass layer for semiconductor super integrated circuit |
| JP2000164885A (en) * | 1990-11-10 | 2000-06-16 | Semiconductor Energy Lab Co Ltd | Manufacture of insulated-gate type semiconductor device |
| JPH1050955A (en) * | 1996-07-31 | 1998-02-20 | Nec Corp | Manufacturing method of semiconductor device |
| JP2000058851A (en) * | 1998-08-17 | 2000-02-25 | Sanyo Electric Co Ltd | Thin film transistor, its manufacture, and display device |
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