CN1292330C

CN1292330C - A circuit for implementing communication for interface of wireless network card

Info

Publication number: CN1292330C
Application number: CN 200310114448
Authority: CN
Inventors: 乔明胜; 刘永波; 王瑞生; 杨亚军; 王文希
Original assignee: Hisense Group Co Ltd
Current assignee: Hisense Group Co Ltd
Priority date: 2003-12-09
Filing date: 2003-12-09
Publication date: 2006-12-27
Anticipated expiration: 2023-12-09
Also published as: CN1627234A

Abstract

The present invention relates to a circuit for implementing the interface communication of a wireless network card. A programmable logic device (PLD) of the circuit adopts an XC9572XL-10 chip of an XILINX corporation as an execution element (EE) of an MCF5272 core processor and provides a circuit design for the interface communication with a PCMCIA (Personal Computer Memory Card International Association) wireless network card; thus, the present invention can be adaptive to the compatibility of a PCMCIA interface chip and fully accord with the requirements of PC CARD standards.

Description

Circuit for realizing communication of wireless network card interface

Technical Field

The invention relates to a circuit for realizing the interface communication of a wireless network card, in particular to a circuit design for realizing the interface communication with a PCMCIA wireless network card by using a programmable logic device CPLD.

Background

With the improvement of office conditions and the development of large-scale integrated circuit technology, various notebook computers are widely used due to the characteristics of convenience in carrying, flexibility in use and the like. Like the USB interface, the PCMCIA interface is almost one of the necessary interfaces of all notebook computers, and is mainly used to plug a PCMCIA wireless network card to support random access to the wlan.

Currently, wireless local area networks (WLAN for short) based on 802.11 protocol technology are mainly applied, and wireless channels are used as data file transmission media. Aiming at the application of the existing wireless network, the high efficiency and the security of key resources such as application programs, e-mails and the like provided by the network are required to be increased continuously, and particularly, for mobile and handheld devices such as notebook computers, mobile phones and the like, the communication capacity and the time efficiency become main limiting factors.

A Programmable Logic device (cpld) having a reprogrammable characteristic. On the interconnection characteristic, the CPLD adopts a continuous interconnection mode, so that the CPLD can ensure high-speed performance in the aspect of designing time sequence. Meanwhile, the more mature PCMCIA interface standard is the 7.0 version formulated in 2 months in 99 years, and because the content of the version lacks enough public data at present, the interface circuit on the basis needs to carry out a large amount of targeted interface circuit design work, and the design applicability of the existing wireless network card is poor, and the corresponding design cost is high.

Disclosure of Invention

The circuit design is based on 7.0 version of PCMCIA interface standard, and the adopted programmable logic device is XC9572XL-10 chip of XILINX company, which is used as an execution unit of MCF5272 core processor and provides the circuit design for communicating with the PCMCIA wireless network card interface.

The circuit for realizing the communication of the wireless network card interface mainly comprises a processor core board, a CPLD programmable logic device, a power supply control chip and a PCMCIA interface.

Wherein, the MCF5272 processor of Motorola is integrated on the processor core board.

The CPLD programmable logic device adopts XC9572XL-10 chip of XILINX company, uses an ISE5.1 development tool of XILINX company, and uses a hardware description language VHDL to program the logic and the time sequence design of the PCMCIA interface into the CPLD programmable logic device 2, namely, the PCMCIA interface is written into the CPLD through a JTAG test interface to complete the port setting of the CPLD and the PCMCIA interface.

The power control chip adopts an MAX1602 chip, and is a power control chip of a one-way CARDBUS and PCMCIA card.

The PCMCIA interface is a standard 68-pin jack that can be plugged into a PCMCIA card compatible with different companies.

As mentioned above, the circuit for realizing the communication of the wireless network CARD interface has the compatibility of adapting PCMCIA interface and completely meets the requirement of PC CARD standard.

Drawings

Fig. 1 is a block diagram of a communication structure of a wireless network card interface according to the present invention;

FIG. 2 is a schematic circuit diagram of a wireless network card interface communication implemented using programmable logic devices;

fig. 3 is a flowchart of the operation of the embodiment.

Detailed Description

As shown in fig. 1-3, the circuit for implementing communication of the wireless network card interface according to the present invention is a circuit design for providing MCF5272 core processor of MOTOROLA corporation with communication of PCMCIA wireless network card interface.

The circuit design is based on an interface application structure of PCMCIA standard, and the adopted programmable logic device is an XC9572XL-10 chip of XILINX company and is used as an execution unit of an MCF5272 core processor, so that the circuit design has strong expandability and can be automatically modified.

As shown in fig. 1, the wireless network card interface communication circuit of the present invention mainly includes a processor core board 1, a CPLD programmable logic device 2, a power control chip 3 and a PCMCIA interface socket 4. Wherein,

the processor core board 1 adopts a MCF5272 processor of Motorola, SDRAM memory with 16M capacity and FLASH memory with 4M capacity; the processor core board 1 has embedded within it a V2ColdFire core, which has a 1KB instruction cache and 4KBSRAM memory.

The CPLD programmable logic device 2 adopts XC9572XL-10 chips of XILINX company, and is provided with 72 logic macro units and 72I/O interfaces, and the highest system clock reaches 200 MHZ; the test circuit comprises a JTAG test interface circuit and has testability; having system-programmable (ISP) capability;

the PCMCIA interface logic and time sequence design are programmed into the CPLD programmable logic device 2 by using a hardware description language VHDL (hardware description language) through a XILINX development tool ISE5.1, namely, the PCMCIA interface logic and time sequence design are written into the CPLD through a JTAG test interface so as to complete the port setting of the CPLD and the PCMCIA interface chip.

The power control chip 3 adopts MAX1602 chip, which is a power control chip of one-way CARDBUS and PCMCIA card, and 16PIN QSOP package, which can realize the output of different voltages such as 12V, 5V and 3.3V by programming the PINs thereof, thereby being capable of adapting to the requirements of different PCMCIA cards.

The PCMCIA interface 4 has a standard 68-pin socket, and can be inserted into a PCMCIA card compatible with different companies, wherein part of pins are connected in series with pull-up resistors with different resistances, so as to ensure that wireless network cards of different models can work normally.

As shown in fig. 2, in the wireless network card interface communication circuit according to the present invention,

d19 is the XC9572XL-10 chip of the CPLD programmable logic device 2, in which the I/O interface is mostly connected to the pins of the PCMCIA card and the signal terminal of the MCF5272 core board.

Wherein, 22-pin GCK1 of CPLD is connected with clock signal C _ CLK, and in FIG. 2, is connected with a clock signal of 66MHZ from MCF5272 core board;

the signal pins are connected with the scanning signal end of the JTAG test interface circuit of the CPLD, and are led to a download socket of CON6, namely the signal pins can be connected with a computer cable adopting the circuit of the invention to carry out online writing, erasing and simulation.

D20 is the power control chip MAX1602, which has three input voltages: 12V, 5V and 3.3V; by programming the four pins, A1VPP, A0VPP, A1VCC, and A0VCC, different voltages are output from the VCC and VPP output pins to the PCMCIA interface 4.

The card slot of the PCMCIA interface 4 is a 68-PIN socket, and the remaining PINs are control signal terminals except for the power supply, address lines a0-a25 and data lines D0-D15 shown in fig. 2, wherein:

the VPP pin is set to 3.3V by the CIS;

VS1 and VS2 pins are output signal terminals, are effective when outputting low voltage, and are used for providing VCC voltage required by initializing power-on of a PC card of a host computer and reading CIS information;

VS1 and VS2 pins, which are respectively connected in series with R28 and R29 pull-up resistors with 10K resistance values to connect with VCC.

The CD1 and CD2 pins are used as output I/O of CPLD to detect whether PC card is inserted into slot, and the CD1 and CD2 pins are directly grounded in PCMCIA. Therefore, when the PC card has been inserted into the slot, the two PINs will be forced to ground.

Meanwhile, the CD1 and CD2 pins are respectively connected in series with a pull-up resistor R62 and a pull-up resistor R63 with the resistance value of 22K to be connected with VCC.

The WAIT pin is used to be set to enable the PCMCIA interface 4 to insert a WAIT period. The time length CPLD of the WAIT # signal is programmed to adapt to the wireless network card interface circuit to process different time sequences.

The WAIT pin is connected to VCC through R61 with a resistance of 10K.

As shown in fig. 3, the working flow of the wireless network card interface communication circuit according to the present invention is as follows:

starting a development tool ISE5.1 of XILINX, compiling and simulating a control sequence and logic code written by VHDL language, and writing the control sequence and logic code into an XC9572XL chip through a JTAG cable after determining that no error exists;

the PCMCIA card is inserted, the voltage of VCC and VPP pins is cut off, and all slot I/O (address and data lines) are set as high-resistance input;

judging whether the PCMCIA card is inserted into the card slot or not according to the level of the pins of the CD1# and the CD2 #;

detecting VS1#, VS2# to determine the VCC voltage required by the system in initializing and reading CIS information and to control the output of MAX 1602;

after the system is reset, the PCMCIA card is operated after waiting for more than 20 ms;

reading configuration information and various index parameters of PC cards such as CIS and the like, thereby accurately positioning the VPP voltage of the card, confirming whether the VPP value needs to be changed or not, and electrifying again;

checking whether the CIS information is correct, and reconfiguring various register and parameters of the PCMCIA card according to the CIS information, so as to complete the initialization of the PCMCIA card, and enable the processor and the PCMCIA wireless network card to normally communicate.

Claims

1. A circuit for realizing wireless network card interface communication mainly comprises a processor core board, a CPLD programmable logic device, a power supply control chip and a PCMCIA interface, and is characterized in that: the processor core board adopts an MCF5272 processor; the CPLD programmable logic device adopts an XC9572XL-10 chip which is provided with a JTAG test interface circuit; the power control chip adopts MAX1602 chip, PCMCIA interface has standard 68-pin socket;

the MCF5272 processor is connected with data line pins (0, 32), address line pins (0, 22), a write data pin (WR), a read data pin (RD), a chip selection pin (CS), an interrupt pin (INT) and a clock pin (CLK) of an XC9572XL-10 chip;

XC9572XL-10 chip is connected with data line pins (0, 16), address line pins (0, 22), CONTROL pin (CONTROL), WAIT pin (WAIT) and STATE pin (STATE) of PCMCIA interface;

the direct current positive pin (HVCC) and the direct current negative pin (HVPP) of the MAX1602 chip are respectively connected with the PCMCIA interface and the power supply pin of the XC9572XL-10 chip.

2. The circuit according to claim 1, wherein the circuit further comprises: the pin (GCK1) of the CPLD programmable logic device XC9572XL-10 chip is connected with a clock signal line (C _ CLK), and the frequency of the clock signal is 66 MHZ; pins (TMS), (TDI), (TDO), and (TCK) connect the scan signal terminals of the JTAG test interface circuitry and lead these four signal pins to the download socket of CON 6.

3. The circuit according to claim 2, wherein the circuit further comprises: the power control chip MAX1602 has three input voltages: 12V, 5V and 3.3V;

through control pins (A1VPP), (A0VPP), (A1VCC) and (A0VCC), pins (VCC) and (VPP) output direct current positive and negative voltage to PCMCIA interface.

4. The circuit according to claim 3, wherein the circuit further comprises: the PCMCIA interface card slot is a 68PIN socket;

pins (VS1) and (VS2) are respectively connected with resistors (R28) and (R29) in series to connect VCC; pins (CD1) and (CD2) are input I/O of the CPLD, pins (CD1) and (CD2) in the PCMCIA interface wireless network card are directly grounded, and pins (CD1) and (CD2) are respectively connected with resistors (R62) and (R63) in series to be connected with VCC;

the pin (WAIT) is connected with VCC through a resistor (R61), and the WAIT pin is set to realize the insertion waiting period of the PCMCIA interface 4;

the time length CPLD of the WAIT # signal is programmed to adapt to the wireless network card interface circuit to process different time sequences.