CN1291576C - Adaptive clock recovery method used for packet switching metwork - Google Patents

Abstract

The present invention discloses a self-adaptive clock recovering method for packet switching networks. The method comprises the procedures that the data buffer size of a receiving end is sampled time and again in a clock frequency regulating period, and a group of buffer sampling series in the clock frequency regulating period is obtained and linearized, so that the deviation estimation of clock frequency at a source end and the receiving end can be obtained so as to adjust the clock frequency of the receiving end. The linearization process can use the method of least square linear regression. Since the delay jitter in an identical clock frequency regulating period at different sampling time can be partially balanced out, the method can effectively restrain the influence of the delay jitter, so that the clock frequency adjustment at the receiving end can follow the source clock frequency fast and quickly.

Description

A kind of adaptive clock recovery method that is used for packet network

(1) technical field

The present invention relates to a kind of network clocking restoration methods that is used for packet switch, relate in particular to a kind of packet network adaptive clock recovery method based on receiving terminal data buffering region measurement.

(2) background technology

At present, packet network have low price, agreement flexibly, advantage such as technology maturation, just obtaining using widely.Many real time business, for example IP phone, TDM (time division multiplexing) circuit emulation service etc. or are soon attempted transmitting on packet network.Packet network adopts Asynchronous Transfer Mode, and most real time business requires clock synchronization end to end, and this requires receiving terminal clock and source end clock to be consistent.When the clock of receiving terminal and source end is not that receiving terminal needs to take out source end clock information according to the sequence of data packet that receives when being taken from same common clock Synchronization Network, promptly clock recovers.Real-time period is professional through the packet network transmission, because influences such as queuing, congested, different Path selection, the propagation delay time of packet is constantly in change at random.As shown in Figure 1, the time delay that produces in the transmission course in the packet network mainly comprises two parts: one is the propagation delay time A that fixes, i.e. propagation delay of signal etc.; Another part is uncertain time delay B, and it comprises the randomness time delay that queuing, congested, different Path selection etc. are caused.So, the packet of the real-time period that the source end sends is uncertain in the time of advent of receiving terminal, bring difficulty for like this clock recovery of receiving terminal, the main task of clock recovery is the clock information of correct extraction source end under the network delay effect of jitter.

At present, clock recovery method mainly contain based on the time target clock recovery method and the adaptive clock recovery method measured based on buffering area.Based on the time target clock recovery method be exactly that the clock information explicitly of source end is sent to receiving terminal, its shortcoming is to need to keep special clock information field in packet.The adaptive clock recovery method of measuring based on buffering area is exactly to recover the clock information of source end according to the speed of receiving terminal data buffer zone packet arrival sequence, thus the influence of inhibition delay variation.

As shown in Figure 2, basic structure principle based on the adaptive clock recovery method of receiving terminal data buffering region measurement is as follows: receiving terminal is put into a data buffering area with the packet that arrives, the speed that packet enters this data buffer zone depends on the clock frequency of transmitting terminal and the influence of network delay shake, simultaneously, receiving terminal is taken data in the data buffer zone away according to local clock.Receiving terminal has a detector period that the data buffering area is sampled.Sampled result is sent to controller, sets down in limited time when the data buffer zone data volume reduces to arrive, local clock is described faster than source end clock, controller reduces the local clock frequency; When the data buffer zone data volume increases the arrival capping, illustrate that local clock is slower than the transmitting terminal clock, controller increases the local clock frequency.Like this, adjust the local clock frequency in the centre position of data buffer zone and make it by keeping the data that receive near the source clock.U.S. Pat 6400683, in open day on June 4th, 2002, invention and created name is that " a kind of asynchronous transmission network adaptive clock recovery " (Adaptive clock recovery inasynchronous transfer mode networks) discloses a kind of similar approach.

Usually, in the adaptive clock recovery method of measuring based on buffering area, the variation of receiving terminal data buffer zone is by the frequency deviation of clock of source end and receiving terminal and two factors decisions of delay variation.As shown in Figure 3, abscissa k represents sampling instant, ordinate φ (k) expression k sampling instant receiving terminal data buffer zone sampled value, wherein Fig. 3 (a) expression is not considered under the situation of delay variation, only the receiving terminal data buffer zone that is caused by frequency deviation of clock changes.At short notice frequency deviation of clock can think constant, so this data buffer zone transformation period sequence satisfies linear function.And generally frequency deviation of clock is very little, and it is a slow process that the data buffer zone that frequency deviation of clock causes changes.Fig. 3 (b) expression is only changed by the receiving terminal data buffer zone that delay variation causes, the data buffer zone variation that delay variation causes is considered to noise, the frequency height, and the delay variation influence can the positive and negative counteracting of part for a long time.Frequency deviation of clock and two factors of delay variation are taken all factors into consideration in Fig. 3 (c) expression, and the data buffer zone of receiving terminal reality changes.As can be seen from the figure, when sampling period during long enough, the influence of delay variation can the positive and negative counteracting of part, and receiving terminal data buffer zone variation tendency can reflect frequency deviation of clock.

In May, 1994, IEEE Trans.Commun the 42nd volume 2189-2196 page or leaf disclosed one piece of article, the author is R.P.Singh, S.-H.Lee etc., article name is " jitter phenomenon and the clock recovery method of cyclical signal transmission in the packet communication network of broadband " (Jitter and clock recovery for periodic traffic in broadbandpacket networks), provided a kind of adaptive clock recovery method of measuring based on buffering area, its basic step is described below:

1), receiving terminal is with designated time intervals (l _Inter) size of sampled data buffering area, the data buffer zone size φ (n) of current sampling instant and the difference DELTA φ (n) of the data buffer zone size φ (n-1) of previous moment have reflected that the receiving terminal data buffer zone changes;

2), Δ φ (n) is divided by l _InterJust obtain packet and arrived and left the estimation of data buffer zone velocity deviation, and can calculate the estimated value of source end, receiving terminal frequency deviation of clock thus

3), basis

Adjust the receiving terminal clock frequency $f_2(n+1)=f_2\left(n\right)+\mathrm{\δ}\·\mathrm{\Δ}\hat{f}\left(n\right),$ Wherein, δ is a weight coefficient, f ₂(n) be receiving terminal current time clock frequency.

In this clock recovery method, the variation of data buffer zone is to be described by the difference of sampling instant data buffer zone size, is subjected to the delay variation of sampling instant to influence very big.In the short time interval, do not match with respect to source end, receiving terminal clock frequency, delay variation is much bigger for the variable effect of data buffer zone, its influence even can flood fully that caused data buffer zone changes because clock frequency matches.More than only come recovered clock based on the adaptive clock recovery method of data buffering region measurement by the variation of observation data buffering area current time, do not consider not suppress delay variation effectively, its effect for clock recovery is had a significant impact.When delay variation is big, in order to obtain clock jitter information, can only strengthen the off time of sampling, just increase the time interval that frequency is adjusted, consequently make receiving terminal can't in time follow the source clock and change.

(3) summary of the invention

The present invention is starting point to suppress delay variation for receiving terminal clock recovery influence, proposes a kind of packet network communication adaptive clock recovery method.

The present invention is achieved through the following technical solutions, comprises the steps:

1), at receiving terminal, the sampling time interval in the clock frequency adjustment cycle, clock frequency adjustment cycle is set, obtain the initial time clock frequency, receive data packet length;

2), in a clock frequency adjustment cycle, with defined sampling time interval the data buffer size is repeatedly sampled, obtain pool of buffer sample sequence in this clock frequency adjustment cycle;

3), to step 2) the buffered sample sequence that obtained, carry out linearization process, the slope reflection data buffer zone of obtained linear function changes speed;

4), utilize slope to carry out the estimation of source end, receiving terminal frequency deviation of clock to the described obtained linear function of step 3);

5), adjust the clock frequency of receiving terminal according to the estimation of current time receiving terminal clock frequency and the described source of step 4) end, receiving terminal frequency deviation of clock;

At next clock frequency adjustment cycle, repeat above-mentioned steps 2)-5).

The inventive method is by repeatedly sampling to the data buffer size in a clock frequency adjustment cycle, the buffered sample sequence that obtains is carried out linearization process, obtain the estimation of source end, receiving terminal frequency deviation of clock then, to adjust the clock frequency of receiving terminal.Because the delay variation of different sampling instants can fall by partial offset in the same clock frequency adjustment cycle,, make the adjustment of receiving terminal clock frequency can follow source clock frequency quickly and accurately so this method can effectively suppress the delay variation influence.

(4) description of drawings

Periodic data bag propagation delay time in Fig. 1, the packet network;

Fig. 2, based on the adaptive clock recovery structure principle chart of data buffering region measurement;

Fig. 3, frequency deviation of clock and delay variation are to receiving terminal data buffering variable effect schematic diagram;

Fig. 4, the inventive method schematic flow sheet;

Delay variation schematic diagram in Fig. 5 a, the inventive method and the traditional clock recovery method emulation experiment contrast;

Fig. 5 b, the inventive method and traditional clock recovery method emulation experiment comparing result schematic diagram.

(5) embodiment

The present invention is described in further detail below in conjunction with the accompanying drawing illustrated embodiment.

Referring to Fig. 4, Fig. 4 is the inventive method schematic flow sheet, and it comprises following concrete steps:

1), system parameter setting: here, need adjust computing cycle, sampling time interval, local clock frequency etc. to the receiving terminal clock frequency and define or extract.For ease of understanding, we represent to adjust (n 〉=0) the n time of the receiving terminal clock frequency with n, be defined in a clock frequency simultaneously and adjust in the computing cycle, according to certain sampling time interval sampling m time, obtain this locality initially clock frequency be f ₂And receive length of data package l (0), _Packet

2), data buffer zone sampling: in n clock frequency adjustment cycle, the data buffer size is sampled for m time with the defined time interval, obtain the interior pool of buffer sample sequence φ of this clock frequency adjustment cycle n _n(i), its corresponding sampling time is expressed as t _n(i).Wherein, φ _nData buffer zone size when (i) the i time in the expression clock frequency adjustment cycle n sampled, here, we represent with bps, t _n(i) (0≤i＜m) of the i time sampling time in the expression clock frequency adjustment cycle n.

3), the buffered sample sequence φ that sampling is obtained _n(i), carry out linearization process:

In the present embodiment, we adopt least-squares linear regression method (LSLR) calculating to carry out linearization process, and calculate the slope of curve  (n) of linear function, and this value reflection data buffer zone changes speed:

$\hat{a}\left(n\right)=\frac{m\·\underset{i=0}{\overset{m-1}{\mathrm{\Σ}}}({\mathrm{\φ}}_n\left(i\right)\·t_n\left(i\right))-\underset{i=0}{\overset{m-1}{\mathrm{\Σ}}}{\mathrm{\φ}}_n\left(i\right)\·\underset{i=0}{\overset{m-1}{\mathrm{\Σ}}}{t}_n\left(i\right)}{m\·\underset{i=0}{\overset{m-1}{\mathrm{\Σ}}}{t}_n{\left(i\right)}^2-{\left(\underset{i=0}{\overset{m-1}{\mathrm{\Σ}}}{t}_n\left(i\right)\right)}^2}$

4), frequency deviation of clock is estimated: the estimation of calculating source end, receiving terminal frequency deviation of clock in n the clock frequency adjustment cycle

(bag/second):

$\mathrm{\Δ}\hat{f}\left(n\right)=-\hat{a}\left(n\right)/l_{\mathrm{packet}}$

For ease of understanding, we define f ₁(n) be n the source end clock frequency (bag/second) in the clock frequency adjustment cycle, f ₂(n) be n the receiving terminal clock frequency (bag/second) in the clock frequency adjustment cycle,, can think f because the clock adjustment cycle is short and drift clock frequency is a slow process ₁(n) and f ₂(n) be constant in a clock frequency adjustment cycle, Δ f (n) representative is the frequency deviation of clock (bag/second) of source end and receiving terminal in n the clock frequency adjustment cycle, that is:

Δf(n)＝f ₂(n)-f ₁(n)

Then be our estimation to source end, receiving terminal frequency deviation of clock, because the deviation of the variation of data buffer zone and clock frequency is the changing inversely process, negative sign is necessary.

5) the receiving terminal clock frequency is adjusted: in the finish time of n clock frequency adjustment cycle, adjust the clock frequency adjustment receiving terminal clock frequency of receiving terminal according to the estimation of present clock frequency and source end, receiving terminal frequency deviation of clock:

$f_2(n+1)=f_2\left(n\right)+\mathrm{\δ}\·\mathrm{\Δ}\hat{f}\left(n\right),$

Wherein δ is a weight coefficient.

In next clock frequency adjustment cycle n+1, repeat above-mentioned steps 2)--5).

Fig. 5 a has provided delay variation schematic diagram in the inventive method and the contrast of traditional clock recovery method emulation experiment.It has very big randomness, and in emulation, we are applied in it and imitate delay variation in the packet network in emulation experiment.

At first, providing simulation model of the present invention describes:

Definition source clock frequency: f ₁(n)=and 29.4117647Hz, 0＜n＜∞, promptly source clock frequency is constant.

The initial moment clock frequency of receiving terminal: f ₂(0)=and 29.3944738Hz, promptly initial moment clock frequency of receiving terminal and source clock have frequency departure;

The sampling time frequency of data buffer zone: and receiving terminal recovered clock frequency f ₂(n) unanimity, initial value promptly are clock frequency f of the initial moment of receiving terminal ₂(0), promptly 29.3944738Hz changes along with the adjustment of receiving terminal clock frequency later on;

The receiving terminal clock frequency is adjusted computing cycle: with per 5000 sampled points is an adjustment cycle;

Receiving packet is fixed length 1024bits, simulation time 4800s, emulation zero-time 100s, δ=0.8;

Linearization technique adopts least-squares linear regression method (LSLR).

The method of contrast adopts R.P.Singh, the clock recovery method of describing in the S.-H.Lee article.

Fig. 5 b has provided the inventive method and traditional clock recovery method The simulation experiment result contrast schematic diagram.Among the figure, straight line a is a source clock frequency; Curve b is R.P.Singh, the clock recovery method institute clock recovered frequency of describing in the S.-H.Lee article; Curve c is a receiving terminal clock frequency of utilizing the inventive method to recover.From simulation result as can be seen, the present invention be feasible effectively, with respect to traditional clock recovery method receiving terminal tracing source clock more quick and precisely.

Below embodiment has been described in detail the present invention in conjunction with the accompanying drawings, and those skilled in the art can make the many variations example to the present invention according to the above description.Thereby some details among the embodiment should not constitute limitation of the invention, and the scope that the present invention will define with appended claims is as protection scope of the present invention.

Claims (4)

1, a kind of packet network adaptive clock recovery method is characterized in that its employing following steps:

1), at receiving terminal, the sampling time interval in the clock frequency adjustment cycle, clock frequency adjustment cycle is set, obtain initial time clock frequency f ₂(0), receives data packet length l _Packet

2), in a clock frequency adjustment cycle, with defined sampling time interval the data buffer size is repeatedly sampled, obtain pool of buffer sample sequence in this clock frequency adjustment cycle;

3), to step 2) the buffered sample sequence that obtained, carry out linearization process, the slope of obtained linear function The reflection data buffer zone changes speed;

4), utilization is to the slope of the obtained linear function of step 3) Carry out the estimation of source end, receiving terminal frequency deviation of clock

5), according to the estimation of current time receiving terminal clock frequency and the described source of step 4) end, receiving terminal frequency deviation of clock Adjust the clock frequency of receiving terminal;

At next clock frequency adjustment cycle, repeat above-mentioned steps 2)-5).

2, packet network adaptive clock recovery method as claimed in claim 1 is characterized in that described step 3) linearization process adopts least-squares linear regression method, the slope of obtained linear function Satisfy equation:

$\hat{a}\left(n\right)=\frac{m\·\underset{i=0}{\overset{m-1}{\mathrm{\Σ}}}({\mathrm{\φ}}_n\left(i\right)\·t_n\left(i\right))-\underset{i=0}{\overset{m-1}{\mathrm{\Σ}}}{\mathrm{\φ}}_n\left(i\right)\·\underset{i=0}{\overset{m-1}{\mathrm{\Σ}}}{t}_n\left(i\right)}{m\·\underset{i=0}{\overset{m-1}{\mathrm{\Σ}}}{t}_n{\left(i\right)}^2-{\left(\underset{i=0}{\overset{m-1}{\mathrm{\Σ}}}{t}_n\left(i\right)\right)}^2}$

Wherein, n represents n clock frequency adjustment cycle, and m represents to sample m time φ in the clock frequency adjustment cycle _nData buffer zone size when (i) the i time in n clock frequency adjustment cycle of expression sampled, t _n(i) the i time sampling time in n clock frequency adjustment cycle of expression, wherein, 0≤i＜m.

3, packet network adaptive clock recovery method as claimed in claim 1 is characterized in that the source end in the described step 4), the estimation of receiving terminal frequency deviation of clock Satisfy equation: $\mathrm{\Δ}\hat{f}\left(n\right)=-\hat{a}\left(n\right)/l_{\mathrm{packet}}.$

4, packet network adaptive clock recovery method as claimed in claim 1 is characterized in that the clock frequency of described adjustment receiving terminal satisfies equation:

$f_2(n+1)=f_2\left(n\right)+\mathrm{\δ}\·\mathrm{\Δ}\hat{f}\left(n\right),$ Wherein, δ is a weight coefficient, f ₂(n) be n the receiving terminal clock frequency in the clock frequency adjustment cycle.

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