CN1291309C - Quick divider - Google Patents
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- CN1291309C CN1291309C CN 03144205 CN03144205A CN1291309C CN 1291309 C CN1291309 C CN 1291309C CN 03144205 CN03144205 CN 03144205 CN 03144205 A CN03144205 A CN 03144205A CN 1291309 C CN1291309 C CN 1291309C
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Abstract
The present invention relates to top a quick divider of which the divisors are 3*2n (n is any positive integer in 0, 1, 2, 3,...), which belongs to the technical field of an electronic device. The present invention mainly solves the problems of the existing divider of slow operation speed and many devices. The present invention has the technical scheme that the quick divider is formed by connecting an adder that a two-bit binary number adds a two-bit binary number, an adder that a two-bit binary number adds a one-bit binary number, an AND gate and an NOT-AND gate. The calculation speed of the quick divider is almost identical to the calculation speed of an adder with the same bit number, and used devices are also a few. The present invention has a non replacing function in occasions using specific division.
Description
Technical field
The invention belongs to the divider in the electron device, particularly a kind of divisor is 3 * 2
nFast divider, wherein n be 0,1,2,3 ... any positive integer.
Background technology
In the various computings of digital signal processing, division is the most complicated, also is the most potential a kind of computing that can excavate.But often do not realize a divider with hardware specially in general CPU, DSP, reason is in general application scenario, and the shared ratio of division is very little; And the design of divider wants complicated a lot of than other arithmetic units.So common way is at other arithmetic units, writes software on the basis as ALU and/or multiplier, constitute the division arithmetic subroutine.But in specific application, as in numeral system conversion, when data unpack, situation is different, and division arithmetic occupies suitable proportion.If using software to do division arithmetic merely often can't meet the demands.
A kind of redundant code high-speed array divider is disclosed in the ZL89106625.X patent document, a kind of high radix divider and method are disclosed in the ZL00121760.7 patent document, a kind of low jitter rate fractional divider of low speed limit is disclosed in the ZL99121853.1 patent document, in the ZL01110397.3 patent document, disclose a kind of array combinational logic divider of overlength degree, in the ZL01132302.7 patent document, disclose a kind of divider.Its common drawback is a complex structure, uses components and parts many, and arithmetic speed is slow.Especially require the occasion of special high speed division arithmetic, existing divider can't be satisfied the demand.
Summary of the invention
The present invention will solve the complex structure that exists in the prior art, uses components and parts many, and the problem that arithmetic speed is slow is 3 * 2 thereby a kind of divisor is provided
n(n is 0,1,2,3 ... integer) fast divider.
Technical solution of the present invention is as follows:
A kind of divider of being made up of electronic devices and components is characterized in that: it is 0～11 that this divider can carry out dividend, and divisor is 3 * 2
nQuick computing, n=0 wherein; The annexation of its circuit is the X2 pin that input end A connects totalizer ADD2, connects the X2 pin of totalizer ADD11 simultaneously; Input end B connects the X1 pin of totalizer ADD2, connects the X1 pin of totalizer ADD11 simultaneously; Input end C connects the Y2 pin of totalizer ADD2; Input end D connects the Y1 pin of totalizer ADD2; The F3 pin of totalizer ADD2 connects the Y1 pin of totalizer ADD11, connects the Y1 pin of totalizer ADD12 simultaneously; The F2 pin of totalizer ADD2 connects the X2 pin of totalizer ADD12; The F1 pin of totalizer ADD2 connects the X1 pin of totalizer ADD12; The F1 pin of totalizer ADD11 connects the X1 pin of totalizer ADD13; The F2 pin of totalizer ADD11 connects the X2 pin of totalizer ADD13, is connected the Y1 pin of totalizer ADD13 with output 3 pin of door A1, connects input 1 pin of not gate N simultaneously; The F1 pin of totalizer ADD13 connects binary merchant O2 end of result of division; The F2 pin of totalizer ADD13 connects binary merchant O1 end of result of division; The F1 pin of totalizer ADD12 connects 1 pin with door A3, connects 1 pin with door A1 simultaneously; The F2 pin of totalizer ADD12 connects 1 pin with door A2, connects 2 pin with door A1 simultaneously; Output 2 pin of not gate N connect simultaneously with 2 pin of door A2 and with 2 pin of door A3; Be connected binary remainder O4 end of result of division with output 3 pin of door A3, the binary remainder O3 that is connected result of division with output 3 pin of door A2 holds.
Dividend is 0 ~ 11, and divisor is 3 * 2
n, the fast divider when n=0 as shown in Figure 1.A, B, C, D are 4 binary dividends, as 4 input ends; Implicit divisor is 3 * 2
n, n=0; O1, O2 are binary merchants of result of division; O3, O4 are binary remainders of the result of division; ADD2, ADD11, ADD12, ADD13 are arbitrarily more than two binary adder.The input end X of binary adder represents first addend, and Y represents second addend; The output terminal of binary adder represents that with F the coefficient of X, Y, F back is represented the power of binary number, 1 expression power be 2
0Position, 2 expression power be 2
1Position, 3 expression power be 2
2Position, 4 expression power be 2
3The position.
Its circuit connecting relation as shown in Figure 1, input end A connects the X2 pin of ADD2, connects the X2 pin of ADD11 simultaneously; Input end B connects the X1 pin of ADD2, connects the X1 pin of ADD11 simultaneously; Input end C connects the Y2 pin of ADD2, and input end D connects the Y1 pin of ADD2; The F3 pin of ADD2 connects the Y1 pin of ADD11, connects the Y1 pin of ADD12 simultaneously; The F1 pin of ADD2 connects the X1 pin of totalizer ADD12; The F2 pin of totalizer ADD2 connects the X2 pin of totalizer ADD12; The F1 pin of totalizer ADD11 connects the X1 pin of totalizer ADD13, and the F2 pin of totalizer ADD11 connects the X2 pin of totalizer ADD13, is connected the Y1 pin of totalizer ADD13 with output 3 pin of door A1, connects input 1 pin of not gate N simultaneously; The F1 pin of totalizer ADD13 connects binary merchant O2 end of result of division, and the F2 pin of totalizer ADD13 connects binary merchant O1 end of result of division; The F1 pin of totalizer ADD12 connects 1 pin with door A3, connects 1 pin with door A1 simultaneously; The F2 pin of totalizer ADD12 connects 1 pin with door A2, connects 2 pin with door A1 simultaneously; Output 2 pin of not gate N connect simultaneously with 2 pin of door A2 and with 2 pin of door A3; The binary remainder O4 end that is connected result of division with output 3 pin of door A3, the binary remainder O3 end that is connected result of division with output 3 pin of door A2, beyond two everybody of first addend of totalizer ADD2, ADD11, ADD12, ADD13 minimum imports 0, beyond two everybody of second addend of ADD2 minimum imports 0, and beyond minimum one of second addend of ADD11, ADD12, ADD13 everybody imports 0.Minimum 3 output terminals are only used in the output of ADD2, and minimum 2 output terminals are only used in the output of ADD11, ADD12, ADD13.
Dividend is 0 ~ 15, and divisor is 3 * 2
n, the circuit connecting relation of the fast divider when n=0 as shown in Figure 2.
Increase by one and a door A4 on the basis of Fig. 1, be connected input end B with input 1 pin of door A4,2 pin connect input end A, and 3 pin connect binary remainder O0 end of result of division.
Dividend is 0～11 * 2
n+ 1, divisor is 3 * 2
n, when n=0,2,3 ... arbitrarily the circuit connecting relation of the fast divider during positive integer as shown in Figure 3.On the basis of Fig. 1, increase the n bar from being input to the line E of output
1-O5
1E
n-O5
n
Dividend is 0～15 * 2
n+ 1, divisor is 3 * 2
n, when n=1,2,3 ... arbitrarily the circuit connecting relation of the fast divider during positive integer as shown in Figure 4.Its right on the basis of Fig. 1 increases by one and a door A4; Be connected input end B with input 1 pin of door A4,2 pin connect input end A, and 3 pin connect binary remainder O0 end of result of division.The left side increases the line E that the n bar is input to output on the basis of Fig. 1 simultaneously
1-O5
1E
n-O5
n
Totalizer ADD2, ADD11, ADD12, ADD13 can be all or wherein any one or any two or any three are to finish the totalizer that two bits add two bit functions.
Two bits add two bits totalizer circuit connecting relation as shown in Figure 5: input end Y1 connects the input end 2 of rejection gate NR1, the input end 1 of Sheffer stroke gate NA1, the input end 1 of XOR gate XR1 simultaneously; Input end X1 connects another input end 1 of rejection gate NR1, another input end 2 of Sheffer stroke gate NA1, another input end 2 of XOR gate XR1 simultaneously; Input end Y2 connects the input end 1 of rejection gate NR2, the input end 1 of Sheffer stroke gate NA2, the input end 2 of XOR gate XR2 simultaneously; Input end X2 connects the input end 2 of rejection gate NR2, the input end 2 of Sheffer stroke gate NA2, the input end 1 of XOR gate XR2 simultaneously; The output terminal 3 of XOR gate XR1 connects output terminal F1; The output terminal 3 of Sheffer stroke gate NA1 connect simultaneously rejection gate NR3 an input end 1, with the door A5 an input end 2; The output terminal 3 of rejection gate NR1 connect simultaneously rejection gate NR3 an input end 2, with the door A6 an input end 2; The output terminal 3 of Sheffer stroke gate NA2 connect simultaneously with the door A5 another input end 1, with the door A6 another input end 1; The output terminal 3 of rejection gate NR2 connects the input end 1 of rejection gate NR4; The output terminal 3 of rejection gate NR3 connects the input end 2 of XOR gate XR3; The output terminal 3 of XOR gate XR2 connects another input end 1 of XOR gate XR3; Another input end 2 that is connected rejection gate NR4 with the output terminal 3 of door A6; Another input end 3 that is connected rejection gate NR4 with the output terminal 3 of door A5; The output terminal 3 of XOR gate XR3 connects output terminal F2; The output terminal 3 of rejection gate NR4 connects output terminal F3.
Totalizer ADD11, ADD12, ADD13 all or wherein any one or any two are to finish the totalizer that two bits add a bit function.
Two bits add a bit totalizer circuit connecting relation as shown in Figure 6:
Input end Y1 connects the input end 1 of XOR gate XR5, connects the input end 2 with door A7 simultaneously; Input end X2 connects the input end 1 of XOR gate XR4, and input end X1 connects the input end 2 of XOR gate XR5, connects the input end 1 with door A7 simultaneously; The output terminal 3 of XOR gate XR5 connects output terminal F1, and the output terminal 3 of XOR gate XR4 connects output terminal F2.
The present invention compared with prior art has following beneficial effect:
1. divider of the present invention is simple in structure, and the components and parts of use are few, and cost is low;
2. it is 3 * 2 that divider of the present invention can carry out divisor
n, wherein n be 0,1,2,3 ... the quick division arithmetic of positive integer under some special occasion, has irreplaceable effect arbitrarily.
Description of drawings
Fig. 1 is that dividend of the present invention is 0～11, and divisor is 3 * 2
n, the circuit theory diagrams of the fast divider when n=0;
Fig. 2 is that dividend of the present invention is 0～15, and divisor is 3 * 2
n, the circuit theory diagrams of the fast divider when n=0;
Fig. 3 is that dividend of the present invention is 0～11 * 2
n+ 1, divisor is 3 * 2
n, as n=0,1,2,3 ... the any circuit theory diagrams of the fast divider during positive integer;
Fig. 4 is that dividend of the present invention is 0～15 * 2
n+ 1, divisor is 3 * 2
n, as n=0,1,2,3 ... the circuit theory diagrams of the fast divider of any positive integer;
Fig. 5 is the adder circuit schematic diagram that the present invention's two bits add two bits;
Fig. 6 is the adder circuit schematic diagram that the present invention's two bits add a bit.
Embodiment
Dividend is 0～11, and divisor is 3 * 2
n, the divider of the quick computing when n=0.Its circuit connecting relation as shown in Figure 1, input end A connects the X2 pin of totalizer ADD2, connects the X2 pin of totalizer ADD11 simultaneously; Input end B connects the X1 pin of totalizer ADD2, connects the X1 pin of totalizer ADD11 simultaneously; Input end C connects the Y2 pin of totalizer ADD2, and input end D connects the Y1 pin of totalizer ADD2; The F3 pin of totalizer ADD2 connects the Y1 pin of totalizer ADD11, connects the Y1 pin of totalizer ADD12 simultaneously; The F1 pin of totalizer ADD2 connects the X1 pin of totalizer ADD12; The F2 pin of totalizer ADD2 connects the X2 pin of totalizer ADD12; The F1 pin of totalizer ADD11 connects the X1 pin of totalizer ADD13, and the F2 pin of totalizer ADD11 connects the X2 pin of totalizer ADD13; The F1 pin of totalizer ADD13 connects binary merchant O2 end of result of division, and the F2 pin of totalizer ADD13 connects binary merchant O1 end of result of division; The F1 pin of totalizer ADD12 connects 1 pin with door A3, connects 1 pin with door A1 simultaneously; The F2 pin of totalizer ADD12 connects 2 pin with door A1, connects 1 pin with door A2 simultaneously; Output terminal 2 ends of not gate N connect simultaneously with 2 pin of door A2 and with 2 pin of door A3; Be connected binary remainder O4 end of result of division with output 3 ends of door A3, the binary remainder O3 that is connected result of division with output 3 ends of door A2 holds.
When ABCD=(1010) B=(10) D, because the X2 of ADD2 and X1 constitute first addend of ADD2, the Y2 of ADD2 and Y1 constitute second addend of ADD2, first addend of ADD2 is (10) B like this, second addend is (10) B, (10) B+ (10) B=(100) B is so the F3 of ADD2, F2, F1 are respectively 1,0,0;
First addend of ADD11 is (10) B like this, and second addend of ADD11 is (1) B, and (10) B+ (1) B=(11) B so the F2 of ADD11, F1 are respectively 1,1, makes the X2 of ADD13 and X1 be respectively 1,1, and promptly first addend of ADD13 is (11) B;
F2 by ADD2, F1 is respectively 0,0, make X2 and the X1 of ADD12 be respectively 0,0, F3 by ADD2 is 1, make that the Y1 of ADD12 is 1, first addend of ADD12 is (00) B like this, second addend of ADD11 is (1) B, and so (00) B+ (1) B=(01) B is the F2 of ADD12, F1 is respectively 0,1, make 2 pin and 1 pin of A1 be respectively 0,1, so the output terminal 3 of A1 is 0, make that the Y1 of ADD13 is 0, second addend of ADD13 is (0) B, first addend by ADD13 is (11) B, (11) B+ (0) B=(11) B, be exactly O1 be 1, O2 is 1, and promptly the merchant is (11) B=(3) D
So (1010) B is divided by 3 merchant (11) B=(3) D surplus (01) B=(1) D.
Dividend is 0～15, and divisor is 3 * 2
n, the divider of the quick computing when n=0.Its circuit connecting relation increases by one and a door A4 as shown in Figure 2 on the basis of Fig. 1, be connected input end B with input 1 pin of door A4, and 2 pin connect input end A, and 3 pin connect binary remainder O0 end of result of division.
When ABCD=(1110) B=(14) D, because the X2 of ADD2 and X1 constitute first addend of ADD2, the Y2 of ADD2 and Y1 constitute second addend of ADD2, first addend of ADD2 is (11) B like this, second addend is (10) B, (11) B+ (10) B=(101) B is so the F3 of ADD2, F2, F1 are respectively 1,0,1;
First addend of ADD11 is (11) B like this, and second addend of ADD11 is (1) B, and (11) B+ (1) B=(00) B so the F2 of ADD11, F1 are respectively 0,0, makes the X2 of ADD13 and X1 be respectively 0,0, and promptly first addend of ADD13 is (00) B;
F2 by ADD2, F1 is respectively 0,1, make X2 and the X1 of ADD12 be respectively 0,1, F3 by ADD2 is 1, make that the Y1 of ADD12 is 1, first addend of ADD12 is (01) B like this, and second addend of ADD11 is (1) B, (01) B+ (1) B=(10) B, so F2 of ADD12, F1 is respectively 1,0, make that 2 and 1 of A1 is respectively 1,0, so the output terminal 3 of A1 is 0, make that the Y1 of ADD13 is 0, second addend of ADD13 is (0) B, is (00) B by first addend of ADD13, (00) B+ (0) B=(00) B, be exactly O1 be 0, O2 is 0, by A=1, B=1, then 2 of A4 is 1,1 of A4 is 1, so 3 of A4 is 1, getting O0 is 1, and promptly the merchant is (100) B=(4) D
Dividend is 0～23, and divisor is 3 * 2
n, work as n=1, promptly divisor is the divider of 6 o'clock quick computing.Its circuit connecting relation increases by one as shown in Figure 3 from being input to the line E of output on the basis of Fig. 1
1-O5
1
Work as ABCDE
1During=(10101) B=(21) D, because the X2 of ADD2 and X1 constitute first addend of ADD2, the Y2 of ADD2 and Y1 constitute second addend of ADD2, first addend of ADD2 is (10) B like this, second addend is (10) B, (10) B+ (10) B=(100) B is so the F3 of ADD2, F2, F1 are respectively 1,0,0;
First addend of ADD11 is (10) B like this, and second addend of ADD11 is (1) B, and (10) B+ (1) B=(11) B so the F2 of ADD11, F1 are respectively 1,1, makes the X2 of ADD13 and X1 be respectively 1,1, and promptly first addend of ADD13 is (11) B;
F2 by ADD2, F1 is respectively 0,0, make X2 and the X1 of ADD12 be respectively 0,0, F3 by ADD2 is 1, make that the Y1 of ADD12 is 1, first addend of ADD12 is (00) B like this, second addend of ADD11 is (1) B, and so (00) B+ (1) B=(01) B is the F2 of ADD12, F1 is respectively 0,1, make 2 and 1 of A1 be respectively 0,1, so the output terminal 3 of A1 is 0, make that the Y1 of ADD13 is 0, second addend of ADD13 is (0) B, first addend by ADD13 is (11) B, (11) B+ (0) B=(11) B, be exactly O1 be 1, O2 is 1, and promptly the merchant is (11) B=(3) D
So (10101) B=(21) D is divided by 6 merchant (11) B=(3) D surplus (011) B=(3) D.
Embodiment 4
Dividend is 0～31, and divisor is 3 * 2
n, work as n=1, promptly divisor is the divider of 6 o'clock quick computing, its circuit connecting relation increases by one and a door A4 as shown in Figure 4 on the basis of Fig. 1; Be connected input end B with input 1 pin of door A4,2 pin connect input end A, and 3 pin connect binary remainder O0 end of result of division.On the basis of Fig. 1, increase a line E who is input to output simultaneously
1-O5
1
As ABCD E
1During=(11101) B=(29) D, because the X2 of ADD2 and X1 constitute first addend of ADD2, the Y2 of ADD2 and Y1 constitute second addend of ADD2, first addend of ADD2 is (11) B like this, second addend is (10) B, (11) B+ (10) B=(101) B is so the F3 of ADD2, F2, F1 are respectively 1,0,1;
First addend of ADD11 is (11) B like this, and second addend of ADD11 is (1) B, and (11) B+ (1) B=(00) B so the F2 of ADD11, F1 are respectively 0,0, makes the X2 of ADD13 and X1 be respectively 0,0, and promptly first addend of ADD13 is (00) B;
F2 by ADD2, F1 is respectively 0,1, make X2 and the X1 of ADD12 be respectively 0,1, F3 by ADD2 is 1, make that the Y1 of ADD12 is 1, first addend of ADD12 is (01) B like this, and second addend of ADD11 is (1) B, (01) B+ (1) B=(10) B, so F2 of ADD12, F1 is respectively 1,0, make that 2 and 1 of A1 is respectively 1,0, so the output terminal 3 of A1 is 0, make that the Y1 of ADD13 is 0, second addend of ADD13 is (0) B, is (00) B by first addend of ADD13, (00) B+ (0) B=(00) B, be exactly O1 be 0, O2 is 0, by A=1, B=1, then 2 of A4 is 1,1 of A4 is 1, so 3 of A4 is 1, getting O0 is 1, and promptly the merchant is (100) B=(4) D
So (11101)=(29) divided by 6 merchant (100) B=(4) D surplus (101) B=(5) D.
Embodiment 5
Dividend is 0～63, and divisor is 3 * 2
n, work as n=2, promptly divisor is the divider of 12 o'clock quick computing, its circuit connecting relation increases by one and a door A4 as shown in Figure 4 on the basis of Fig. 1; Be connected input end B with input 1 pin of door A4,2 pin connect input end A, and 3 pin connect binary remainder O0 end of result of division.On the basis of Fig. 1, increase by two line E that are input to output simultaneously
1-O5
1, E
2-O5
2
As ABCD E
1E
2During=(111010) B=(58) D, because the X2 of ADD2 and X1 constitute first addend of ADD2, the Y2 of ADD2 and Y1 constitute second addend of ADD2, first addend of ADD2 is (11) B like this, second addend is (10) B, (11) B+ (10) B=(101) B is so the F3 of ADD2, F2, F1 are respectively 1,0,1;
First addend of ADD11 is (11) B like this, and second addend of ADD11 is (1) B, and (11) B+ (1) B=(00) B so the F2 of ADD11, F1 are respectively 0,0, makes the X2 of ADD13 and X1 be respectively 0,0, and promptly first addend of ADD13 is (00) B;
F2 by ADD2, F1 is respectively 0,1, make X2 and the X1 of ADD12 be respectively 0,1, F3 by ADD2 is 1, make that the Y1 of ADD12 is 1, first addend of ADD12 is (01) B like this, and second addend of ADD11 is (1) B, (01) B+ (1) B=(10) B, so F2 of ADD12, F1 is respectively 1,0, make that 2 and 1 of A1 is respectively 1,0, so the output terminal 3 of A1 is 0, make that the Y1 of ADD13 is 0, second addend of ADD13 is (0) B, is (00) B by first addend of ADD13, (00) B+ (0) B=(00) B, be exactly O1 be 0, O2 is 0, by A=1, B=1, then 2 of A4 is 1,1 of A4 is 1, so 3 of A4 is 1, getting O0 is 1, and promptly the merchant is (100) B=(4) D
So (111010) B=(58) D is divided by (12) D merchant (100) B=(4) D surplus (1010) B=(10) D.
Embodiment 6
Two bits add two bits totalizer circuit connecting relation as shown in Figure 5, input end Y1 connects the input end 2 of rejection gate NR1, the input end 1 of Sheffer stroke gate NA1, the input end 1 of XOR gate XR1 simultaneously; Input end X1 connects another input end 1 of rejection gate NR1, another input end 2 of Sheffer stroke gate NA1, another input end 2 of XOR gate XR1 simultaneously; Input end Y2 connects the input end 1 of rejection gate NR2, the input end 1 of Sheffer stroke gate NA2, the input end 2 of XOR gate XR2 simultaneously; Input end X2 connects the input end 2 of rejection gate NR2, the input end 2 of Sheffer stroke gate NA2, the input end 1 of XOR gate XR2 simultaneously; The output terminal 3 of XOR gate XR1 connects output terminal F1; The output terminal 3 of Sheffer stroke gate NA1 connect simultaneously rejection gate NR3 an input end 1, with the door A5 an input end 2; The output terminal 3 of rejection gate NR1 connect simultaneously rejection gate NR3 an input end 2, with the door A6 an input end 2; The output terminal 3 of Sheffer stroke gate NA2 connect simultaneously with the door A5 another input end 1, with the door A6 another input end 1; The output terminal 3 of rejection gate NR2 connects the input end 1 of rejection gate NR4; The output terminal 3 of rejection gate NR3 connects the input end 2 of XOR gate XR3; The output terminal 3 of XOR gate XR2 connects another input end 1 of XOR gate XR3; Another input end 2 that is connected rejection gate NR4 with the output terminal 3 of door A6; Another input end 3 that is connected rejection gate NR4 with the output terminal 3 of door A5; The output terminal 3 of XOR gate XR3 connects output terminal F2; The output terminal 3 of rejection gate NR4 connects output terminal F3.
When the 1st addend be (10) B, when the 2nd addend when (11) B, X1=0, X2=1, Y1=1, Y2=1, an input end 1 that draws XR1 is 1, the input end 2 of XR1 is 0, so the output terminal 3 of XR1 is 1, promptly F1 is 1; An input end 1 that draws NA1 is 1, and the input end 2 of NA1 is 0, so the output terminal 3 of NA1 is 1; An input end 1 that draws NR1 is 0, and the input end 2 of NR1 is 1, so the output terminal 3 of NR1 is 0; An input end 1 that draws NA2 is 1, and the input end 2 of NA2 is 1, so the output terminal 3 of NA2 is 0; An input end 1 that draws NR2 is 1, and the input end 2 of NR2 is 1, so the output terminal 3 of NR2 is 0; An input end 1 that draws XR2 is 1, and the input end 2 of XR2 is 1, so the output terminal 3 of XR2 is 0; An input end 1 that draws NR3 is 1, and the input end 2 of NR3 is 0, so the output terminal 3 of NR3 is 0; An input end 1 that draws XR3 is 0, and the input end 2 of XR3 is 0, so the output terminal 3 of XR2 is 0; Be that F2 is 0; An input end 1 that draws A5 is 0, and the input end 2 of A5 is 1, so the output terminal 3 of A5 is 0; An input end 1 that draws A6 is 0, and the input end 2 of A6 is 1, so the output terminal 3 of A6 is 0; An input end 1 that draws NR4 is 0, and the input end 2 of NR4 is 0, and the input end 3 of NR4 is 0, so the output terminal 4 of NR4 is 1; Be that F3 is 1; So (10) B+ (11) B=(101) B.
Embodiment 7
The adder circuit annexation that two bits add a bit as shown in Figure 6, input end Y1 connects the input end 1 of XOR gate XR5, connects the input end 2 with door A7 simultaneously; Input end X2 connects the input end 1 of XOR gate XR4, and input end X1 connects the input end 2 of XOR gate XR5, connects the input end 1 with door A7 simultaneously; The output terminal 3 of XOR gate XR5 connects output terminal F1, and the output terminal 3 of XOR gate XR4 connects output terminal F2.
Work as X1=0, X2=1, during Y1=1, an input end 1 that draws XR5 is 1, the input end 2 of XR5 is 0, so the output terminal 3 of XR2 is 1; Be F1=1; An input end 1 that draws A7 is 0, and the input end 2 of A7 is 1, so the output terminal 3 of A7 is 0; An input end 1 that draws XR4 is 1, and the input end 2 of XR4 is 0, so the output terminal 3 of XR2 is 1; Be that F2 is 1; So (10) B+ (1) B=(11) B.
More than () B represent in the bracket it is binary number, () D represents in the bracket it is metric number.
Following table is the value and the corresponding decimal numeral value of the possible binary number of each end points of this divider.
This divider left side can directly connect the line E that the n bar is input to output
1-O5
1E
n-O5
n, can make dividend and divisor enlarge 2n doubly like this, here n output O1 ... On is the low n position of remainder, n can be for 0,1,2,3 ... any positive integer.
BCS2 represents the input of dividend binary number in the table, BCS2-10 represents the decimal number of dividend binary number correspondence, S2 represents the binary number discussed, S2-10 represents the decimal number of the binary number correspondence discussed, YS2 represents the binary number of remainder, and YS2-10 represents the decimal number of the binary number correspondence of remainder.
| BCS2 | BCS2-10 | S2 | S2-10 | YS2 | YS2-10 | ||||||
| A | B | C | D | O0 | O1 | O2 | O3 | O4 | |||
| 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
| 0 | 0 | 1 | 0 | 2 | 0 | 0 | 0 | 0 | 1 | 0 | 2 |
| 0 | 0 | 1 | 1 | 3 | 0 | 0 | 1 | 1 | 0 | 0 | 0 |
| 0 | 1 | 0 | 0 | 4 | 0 | 0 | 1 | 1 | 0 | 1 | 1 |
| 0 | 1 | 0 | 1 | 5 | 0 | 0 | 1 | 1 | 1 | 0 | 2 |
| 0 | 1 | 1 | 0 | 6 | 0 | 1 | 0 | 2 | 0 | 0 | 0 |
| 0 | 1 | 1 | 1 | 7 | 0 | 1 | 0 | 2 | 0 | 1 | 1 |
| 1 | 0 | 0 | 0 | 8 | 0 | 1 | 0 | 2 | 1 | 0 | 2 |
| 1 | 0 | 0 | 1 | 9 | 0 | 1 | 1 | 3 | 0 | 0 | 0 |
| 1 | 0 | 1 | 0 | 10 | 0 | 1 | 1 | 3 | 0 | 1 | 1 |
| 1 | 0 | 1 | 1 | 11 | 0 | 1 | 1 | 3 | 1 | 0 | 2 |
| 1 | 1 | 0 | 0 | 12 | 1 | 0 | 0 | 4 | 0 | 0 | 0 |
| 1 | 1 | 0 | 1 | 13 | 1 | 0 | 0 | 4 | 0 | 1 | 1 |
| 1 | 1 | 1 | 0 | 14 | 1 | 0 | 0 | 4 | 1 | 0 | 2 |
| 1 | 1 | 1 | 1 | 15 | 1 | 0 | 1 | 5 | 0 | 0 | 0 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Claims (9)
1, a kind of divider is characterized in that: it is 0～11 that this divider can carry out dividend, and divisor is 3 * 2
nQuick computing, n=0 wherein; The annexation of its circuit is the X2 pin that input end A connects totalizer ADD2, connects the X2 pin of totalizer ADD11 simultaneously; Input end B connects the X1 pin of totalizer ADD2, connects the X1 pin of totalizer ADD11 simultaneously; Input end C connects the Y2 pin of totalizer ADD2; Input end D connects the Y1 pin of totalizer ADD2; The F3 pin of totalizer ADD2 connects the Y1 pin of totalizer ADD11, connects the Y1 pin of totalizer ADD12 simultaneously; The F2 pin of totalizer ADD2 connects the X2 pin of totalizer ADD12; The F1 pin of totalizer ADD2 connects the X1 pin of totalizer ADD12; The F1 pin of totalizer ADD11 connects the X1 pin of totalizer ADD13; The F2 pin of totalizer ADD11 connects the X2 pin of totalizer ADD13, is connected the Y1 pin of totalizer ADD13 with output 3 pin of door A1, connects input 1 pin of not gate N simultaneously; The F1 pin of totalizer ADD13 connects binary merchant O2 end of result of division; The F2 pin of totalizer ADD13 connects binary merchant O1 end of result of division; The F1 pin of totalizer ADD12 connects 1 pin with door A3, connects 1 pin with door A1 simultaneously; The F2 pin of totalizer ADD12 connects 1 pin with door A2, connects 2 pin with door A1 simultaneously; Output 2 pin of not gate N connect simultaneously with 2 pin of door A2 and with 2 pin of door A3; Be connected binary remainder O4 end of result of division with output 3 pin of door A3, the binary remainder O3 that is connected result of division with output 3 pin of door A2 holds.
2, according to the said divider of claim 1, it is characterized in that: the annexation of its circuit is to increase by one and a door A4, be connected input end B with input 1 pin of door A4,2 pin connect input end A, 3 pin connect binary remainder O0 end of result of division, it is 0～15 that this divider can carry out dividend, and divisor is 3 * 2
nQuick computing, n=0 wherein.
3, according to claim 1 or 2 said dividers, it is characterized in that: the annexation of its circuit is to increase the n bar from being input to the line E of output
1-O5
1E
n-O5
n, it is 0～11 * 2 that this divider can carry out dividend
n+ 1 or 0～15 * 2
n+ 1, divisor is 3 * 2
nQuick computing, wherein n=0 1 or 2 or 3 or ... any positive integer.
4, according to claim 1 or 2 said dividers, it is characterized in that: totalizer ADD2, ADD11, ADD12, ADD13 all or wherein any one or any two or any three are to finish the totalizer that two bits add two bit functions.
5, according to the said divider of claim 3, it is characterized in that: totalizer ADD2, ADD11, ADD12, ADD13 all or wherein any one or any two or any three are to finish the totalizer that two bits add two bit functions.
6, according to claim 1 or 2 said dividers, it is characterized in that: the circuit connecting relation of said totalizer is an input end Y1 input end 2 connecting rejection gate NR1 simultaneously, the input end 1 of Sheffer stroke gate NA1, the input end 1 of XOR gate XR1; Input end X1 connects another input end 1 of rejection gate NR1, another input end 2 of Sheffer stroke gate NA1, another input end 2 of XOR gate XR1 simultaneously; Input end Y2 connects the input end 1 of rejection gate NR2, the input end 1 of Sheffer stroke gate NA2, the input end 2 of XOR gate XR2 simultaneously; Input end X2 connects the input end 2 of rejection gate NR2, the input end 1 of Sheffer stroke gate NA2, the input end 1 of XOR gate XR2 simultaneously; The output terminal 3 of XOR gate XR1 connects output terminal F1; The output terminal 3 of Sheffer stroke gate NA1 connect simultaneously rejection gate NR3 an input end 1, with the door A5 an input end 2; The output terminal 3 of rejection gate NR1 connect simultaneously rejection gate NR3 an input end 2, with the door A6 an input end 2; The output terminal 3 of Sheffer stroke gate NA2 connect simultaneously with the door A5 another input end 1, with the door A6 another input end 1; The output terminal 3 of rejection gate NR2 connects the input end 1 of rejection gate NR4; The output terminal 3 of rejection gate NR3 connects the input end 2 of XOR gate XR3; The output terminal 3 of XOR gate XR2 connects another input end 1 of XOR gate XR3; Another input end 2 that is connected rejection gate NR4 with the output terminal 3 of door A6; Another input end 3 that is connected rejection gate NR4 with the output terminal 3 of door A5; The output terminal 3 of XOR gate XR3 connects the output terminal F2 of ADD2; The output terminal 3 of rejection gate NR4 connects output terminal F3.
7, according to claim 1 or 2 said dividers, it is characterized in that: totalizer ADD11, ADD12, ADD13 all or wherein any one or any two are to finish the totalizer that two bits add a bit function.
8, according to the said divider of claim 3, it is characterized in that: totalizer ADD11, ADD12, ADD13 all or wherein any one or any two are to finish the totalizer that two bits add a bit function.
9, according to claim 1 or 2 said dividers, it is characterized in that: the circuit connecting relation of said totalizer is the input end 1 that input end Y1 connects XOR gate XR5, connects the input end 2 with door A7 simultaneously; Input end X2 connects the input end 1 of XOR gate XR4, and input end X1 connects the input end 2 of XOR gate XR5, connects the input end 1 with door A7 simultaneously; The output terminal 3 of XOR gate XR5 connects output terminal F1, and the output terminal 3 of XOR gate XR4 connects output terminal F2.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 03144205 CN1291309C (en) | 2003-08-29 | 2003-08-29 | Quick divider |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 03144205 CN1291309C (en) | 2003-08-29 | 2003-08-29 | Quick divider |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1515996A CN1515996A (en) | 2004-07-28 |
| CN1291309C true CN1291309C (en) | 2006-12-20 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN 03144205 Expired - Fee Related CN1291309C (en) | 2003-08-29 | 2003-08-29 | Quick divider |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101499001B (en) * | 2009-03-13 | 2010-09-29 | 天津工程师范学院 | Fast divider with 127 multiplied with 2n as divisor |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110147217B (en) * | 2018-02-12 | 2024-07-30 | 北京忆芯科技有限公司 | Divider |
-
2003
- 2003-08-29 CN CN 03144205 patent/CN1291309C/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101499001B (en) * | 2009-03-13 | 2010-09-29 | 天津工程师范学院 | Fast divider with 127 multiplied with 2n as divisor |
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| Publication number | Publication date |
|---|---|
| CN1515996A (en) | 2004-07-28 |
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