CN1288728C - 晶片的封装方法 - Google Patents

晶片的封装方法 Download PDF

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CN1288728C
CN1288728C CNB021420920A CN02142092A CN1288728C CN 1288728 C CN1288728 C CN 1288728C CN B021420920 A CNB021420920 A CN B021420920A CN 02142092 A CN02142092 A CN 02142092A CN 1288728 C CN1288728 C CN 1288728C
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唐光辉
刘洪民
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Fujian Jinhua Integrated Circuit Co Ltd
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United Microelectronics Corp
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Abstract

一种晶片的封装方法，首先提供一表面具有多个接合垫的晶片，以一环氧化合物固定于一具有多个凸块焊垫的基底的一开口上方；先以金线将各该接合垫与相对应的该凸块焊垫相连接，再将一密封物涂于该基底表面；接着进行一压模加热工序以固化该密封物，并进行一压盖工序，将一顶盖通过与该密封物固定的方式以覆盖该基底、该晶片与该金线，再进行一单块切割工序；本发明利用一粘着物将该顶盖覆盖于该基底、该晶片上方，因此当对该晶片进行电性缺陷分析时，可轻易将该顶盖移除而不伤及该晶片的表面，此外除可对该晶片的上表面进行顶面测试，还可对该晶片的下表面进行底面测试，而确保该电性缺陷分析结果的可信度，进而大幅增进工序的品管效能。

Description

晶片的封装方法
技术领域
本发明提供一种晶片的封装方法，尤指一种便于针对该晶片的顶面与底面进行一电性缺陷测试的封装方法。
背景技术
随着IC技术的发展，半导体晶片的集成度(integration)逐渐提高，而封装晶片输出输入的引脚数(信号、电源、接地)也随之增加，导致各种高密度的封装基板不断地开发出来，球栅阵列(ball grid array，BGA)封装基板就是一例。目前市场上的BGA封装基板由于具有良好的散热能力，故被大量地使用于BGA封装工序中。
请参考图1至图3，图1至图3为传统BGA封装的方法示意图。如图1所示，一基底10表面形成有多个凸块焊垫(solder bump pad)12，而一表面具有多个接合垫(bonding pad)16的晶片(chip)14则利用一环氧化合物(epoxy compound)18，被固定(attached)于基底10上。
如图2所示，接着进行一接线(wire bonding)工序，以金线20将每一接合垫16与各相对应的凸块焊垫12相连接。随后以一由一铸模化合物(molding compound)所形成的顶盖22覆盖于金线20、晶片14与基底10之上，以防止金线20、晶片14及基底10与外界的水气接触。
如图3所示，随后将多个焊锡球(solder balls)24焊接至基底10的下表面。除此之外，焊锡球24亦可由多个引脚(pin)所取代。最后进行一单块切割(singulation)工序，以完成由传统BGA封装方法所制作的球栅阵列封装体(BGA package)26。
除了BGA封装方法，导线架(leadframe)封装方法亦为一经常被运用于工序中的技术。请参考图4，图4为一适用于传统导线架封装方法的导线架28的上视图。如图4所示，导线架28包含有一晶片垫(diepad)31以及多个引脚(terminal)33，且导线架28表面形成有多个凸块焊垫34。
参考图5至图7，图5至图7为传统导线架封装方法的工序示意图。如图5所示，一晶片32表面具有多个接合垫35。首先利用一铸模化合物36，将晶片32的至少两侧与晶片垫31相连接，以将晶片32固定于晶片垫31之上。接着进行一接线工序，以金线37将每一接合垫35与引脚33上各相对应的凸块焊垫34相连接。随后，将一支撑架30粘着于导线架28的下表面。
如图6所示，之后以由铸模化合物36所形成的一上盖38a与一底盖38b将金线37、晶片32与晶片垫31完全包覆，以避免金线37、晶片32及晶片垫31与与外界的水气接触。
如图7所示，最后进行一修剪(trimming)工序将引脚33的过长部份截断，并随即进行一单块切割工序，以完成由传统leadframe封装方法所制作的导线架封装体(leadframe package)39。
此时为确保BGA封装体26或导线架封装体39的封装品质，通常会利用一测试基座与一光谱显微镜(emission microscope)，于晶片14与32的上表面进行一电性缺陷分析(failure analysis)程序。一测试者先通过该测试基座对晶片14与32导入一预定电流时，再通过该光谱显微镜侦测出晶片14与32的缺陷。
由于晶片14与32的上表面分别由以无法被轻易拆除的铸模化合物36所形成的顶盖22与上盖38a所包覆，因此在进行该电性缺陷分析程序时，必须借助一车床(lathe)或一工具机(computer numerical control，CNC)以将顶盖22与上盖38a移除，以曝露出晶片14与32的上表面供该测试者测试。另一种方法，则以硫酸蚀刻并移除顶盖22与上盖38a，以利该电性缺陷分析程序的进行。然而无论是采用此两种方法中的任何一种，皆容易致使晶片14与32的表面因遭工具机刮伤或硫酸的过度蚀刻而损坏，降低该电性缺陷分析结果的准确性。此外，由于测试者仅能针对传统的球栅阵列封装体26与导线架封装体39的上表面进行该电性缺陷分析程序，故往往因无法侦测出发生于晶片14与32的下表面处的电性缺陷，而造成生产良率下降。
发明内容
因此本发明的主要目的在于提供一种封装方法，针对被封装晶片的上、下表面分别进行一顶面测试(top analysis)与一底面测试(backanalysis)，以确保该晶片的封装品质。
在本发明的最佳实施例中，一基底具有一开口以及多个位于该基底表面的凸块焊垫(solder bump pad)。首先利用一环氧化合物(epoxycompound)，将一表面具有多个接合垫(bonding pad)，且表面积大于该开口的表面积的晶片(chip)的至少两侧与该基底相连接，以将该晶片固定(attach)于该基底的该开口上方。接着进行一接线(wire bonding)工序，以金线将每一该接合垫与相对应的该凸块焊垫相连接，并将一密封物(liquid compound)涂于各该凸块焊垫旁的该基底表面。随即进行一压模加热(post mold curing)工序以固化该密封物，并进行一压盖(encapsulation)工序，将一顶盖(cap)通过与该密封物固定的方式以覆盖于该基底、该晶片与该金线上方。最后进行一单块切割(singulation)工序，以完成由本发明的封装方法所制作的球栅阵列封装体。
由于本发明的制作方法利用一粘着物将该顶盖置于该密封物上方以覆盖于该基底、该晶片与该金线上方，而非以传统技术中的铸模化合物包覆该基底、该晶片与该金线，因此当一测试者于后续工序中欲针对该晶片进行一电性缺陷分析(failure analysis)程序时，可轻易将该顶盖移除以进行该电性缺陷分析程序而不伤及该晶片的表面。此外，当该测试者在针对本发明的封装方法所制作的该球栅阵列封装体进行该电性缺陷分析程序时，除了可以如传统技术般针对该晶片的上表面进行一顶面测试(topside analysis)外，更可利用该晶片的该开口，针对该晶片的下表面进行一底面测试(backside analysis)，而确保该电性缺陷分析结果的可信度，进而大幅增进工序的品管效能。
附图说明
图1至图3为传统球栅阵列(ball grid array，BGA)封装的方法示意图；
图4为一适用于传统导线架封装方法的导线架的上视图；
图5至图7为传统导线架封装方法的工序示意图；
图8为一适用于本发明BGA封装方法的基底的上视图；
图9与图10为本发明BGA封装方法的工序示意图；
图11为一适用于本发明导线架封装方法的导线架的上视图；
图12与图13为本发明导线架封装方法的工序示意图。
图示的符号说明
10    基底                  12    凸块焊垫
14    晶片                  16    接合垫
18    氧化合物            20    金线
22    顶盖                24    焊锡球
26    球栅阵列封装体      28    导线架
30    支撑架              31    晶片垫
32    晶片                33    引脚
34    凸块焊垫            35    接合垫
36    铸模化合物          37    金线
38a   上盖                38b   底盖
39    导线架封装体        40    基底
42    开口                44    凸块焊垫
46    晶片                48    环氧化合物
50    接合垫              52    金线
54    密封物              56    顶盖
58    粘着物              60    球栅阵列封装体
70    导线架              71    晶片垫
72    开口                73    引脚
74    凸块焊垫            76    晶片
78    环氧化合物          79    支撑架
80    接合垫              82    金线
84    密封物              86    顶盖
88    粘着物              90    导线架封装体
具体实施方式
请参考图8，图8为一适用于本发明球栅阵列(ball grid array，BGA)封装方法的基底40的上视图。如图8所示，基底40具有多个凸块焊垫(solder bump pad)44，亦包含有一利用一车床(lathe)或一工具机(computer numerical control，CNC)所切割而成的开口42。除此之外，凸块焊垫44亦可由多个引脚(pin)所取代。
请参考图9与图10，图9与图10为本发明BGA封装方法的工序示意图。如图9所示，一晶片(chip)46表面具有多个接合垫(bonding pad)50，且晶片46的表面积大于开口42的表面积。首先利用一环氧化合物(epoxy compound)48，将晶片46的至少两侧与基底40相连接，以将晶片46固定(attach)于基底40的开口42之上方。接着进行一接线(wirebonding)工序，以金线52将每一接合垫50与各相对应的凸块焊垫44相连接。
如图10所示，随后将一由一银胶(silver paste)或一环氧化合物所构成的密封物(liquid compound)54涂于各凸块焊垫44旁的基底40表面，并进行一压模加热(post mold curing)工序，以固化密封物54。接着利用一粘着物(adhesive material)58进行一压盖(encapsulation)工序，将一顶盖(cap)56置于密封物54上方并覆盖于基底40、晶片46与金线52之上，以达到防止晶片46及基底40与外界水气接触的目的。
最后进行一单块切割(singulation)工序，以完成由本发明的BGA封装方法所制作的球栅阵列封装体(BGA package)60。
此时为确保球栅阵列封装体60的封装品质，通常会利用一测试基座(test socket)，进行一包含有一顶面测试(topside analysis)与一底面测试(backside analysis)的电性缺陷分析(failure analysis)程序。由于顶盖56利用粘着物58置于密封物54上方，一测试者可轻易地通过进行一移盖(decaping)步骤而将顶盖56自密封物54上方移除，以曝露出晶片46的上表面。至于晶片46的下表面则因基底40的开口42，亦直接曝露在外。接着该测试者可利用一光谱显微镜(emissionmicroscope)，分别于晶片46所曝露出之上、下表面进行该顶面测试与该底面测试。当该测试者通过该测试基座对晶片46导入一预定电流时，可立即通过该光谱显微镜侦测出晶片46的缺陷。
请参考图11，图11为一适用于本发明导线架(leadframe)封装方法的导线架70的上视图。如图11所示，导线架70包含有一晶片垫(diepad)71以及多个引脚(terminal)73，且导线架70表面形成有多个凸块焊垫74，而晶片垫71又包含一利用一车床或一工具机所切割而成的开口72。
请参考图12与图13，图12与图13为本发明导线架封装方法的工序示意图。如图12所示，一晶片76表面具有多个接合垫80，且晶片76的表面积大于开口72的表面积。首先利用一环氧化合物78，将晶片76的至少两侧与晶片垫71相连接，以将晶片76固定于晶片垫71的开口72之上方。接着进行一接线工序，以金线82将每一接合垫80与各相对应的凸块焊垫74相连接。随后将一亦具有一与开口72大小相等的开口的支撑架79，粘着于导线架70的下表面。
如图13所示，随后将一由一银胶(silver paste)或一环氧化合物所构成的密封物84涂于各凸块焊垫74旁的引脚73表面，并进行一压模加热工序以固化密封物84。接着利用一粘着物88进行一压盖工序，将一顶盖86置于密封物84上方并覆盖于晶片垫71、引脚73、晶片76与金线82之上，以达到防止晶片76、引脚73及晶片垫71与外界水气接触的目的。
最后进行一修剪(trimming)工序将引脚73的过长部份截断，并随即进行一单块切割工序，以完成由本发明的leadframe封装方法所制作的导线架封装体(leadframe package)90。
此时为确保导线架封装体90的封装品质，通常会利用一测试基座，进行一包含有一顶面测试与一底面测试的电性缺陷分析程序。由于顶盖86利用粘着物88置于密封物84上方，一测试者可轻易地通过进行一移盖步骤而将顶盖86自密封物84上方移除，以曝露出晶片76的上表面。至于晶片76的下表面则因晶片垫71的开口72，亦直接曝露在外。接着该测试者可利用一光谱显微镜，分别于晶片76所曝露出之上、下表面进行该顶面测试与该底面测试。当该测试者通过该测试基座对晶片76导入一预定电流时，可立即通过该光谱显微镜侦测出晶片76的缺陷。
相较于传统技术，本发明利用粘着物58与88将顶盖56与86而被分别置于密封物54与84上，而非利用传统技术中的铸模化合物包覆图10中的基底40、晶片46与金线52或图13中的晶片垫71、引脚73、晶片76与金线82之上。因此当该测试者于后续工序中欲针对晶片46与76进行该电性缺陷分析(failure analysis)程序时，可轻易将顶盖56与86移除以进行该电性缺陷分析程序而不伤及晶片46与76的表面。此外，当该测试者在针对本发明的封装方法所制作的球栅阵列封装体60与导线架封装体90进行该电性缺陷分析程序时，除了可以如传统技术般针对晶片46与76的上表面进行该顶面测试外，更可利用晶片46的开口42与晶片垫71的开口72，针对晶片46与76的下表面进行该底面测试，而确保该电性缺陷分析结果的可信度，进而大幅增进工序的品管效能。
以上所述仅本发明的较佳实施例，凡依本发明申请专利范围所做的均等变化与修饰，皆应属本发明专利的涵盖范围。

Claims (12)

1.一种球栅阵列封装的方法，其特征是：该方法包含有下列步骤：
提供一具有一开口以及多个凸块焊垫的基底；
利用一环氧化合物，将一表面具有多个接合垫且表面积大于该开口的表面积的晶片的至少两侧与该基底相连接，以将该晶片固定于该基底的该开口上方，且晶片底部通过开口暴露出来；
进行一接线工序，以金线将每一该接合垫与相对应的该凸块焊垫相连接；
将一密封物涂于各该凸块焊垫旁的该基底表面；
进行一压模加热工序，以固化该密封物；
进行一压盖工序，将一顶盖通过与该密封物固定的方式以覆盖于该基底、该晶片与该金线上方，且顶盖与晶片间存在间隔；以及
进行一单块切割工序。
2.如权利要求1所述的方法，其特征是：该开口利用一车床或一工具机所切割而成。
3.如权利要求1所述的方法，其特征是：该密封物由一银胶或一环氧化合物所构成。
4.如权利要求1所述的方法，其特征是：该压盖工序利用一粘着物将该顶盖置于该密封物上方。
5.如权利要求1所述的方法，其特征是：在进行完该单块切割工序后，需再进行一电性缺陷分析程序，该程序包含有下列步骤：
进行一移盖步骤，以将该顶盖自该密封物上方移除；
于该晶片的上表面进行一顶面测试；以及
于该晶片的下表面进行一底面测试。
6.如权利要求5所述的方法，其特征是：该电性缺陷分析利用一测试基座来进行。
7.如权利要求5所述的方法，其特征是：该顶面测试与该底面测试利用一光谱显微镜来进行。
8.一种导线架封装的方法，其特征是：该方法包含有下列步骤：
提供一具有一晶片垫以及多个引脚的导线架，其中该晶片垫包含有一开口以及多个凸块焊垫；
利用一环氧化合物，将一表面具有多个接合垫且表面积大于该开口的表面积的晶片的至少两侧与该晶片垫相连接，以将该晶片固定于该晶片垫的该开口上方，且晶片底部通过开口暴露出来；
进行一接线工序，以金线将每一该接合垫与相对应的该凸块焊垫相连接；
将一密封物涂于各该凸块焊垫旁的该晶片垫表面；
进行一压模加热工序，以固化该密封物；
进行一压盖工序，将一顶盖通过与该密封物固定的方式以覆盖于该晶片垫、该晶片与该金线上方，且顶盖与晶片间存在间隔；
进行一修剪工序；以及
进行一单块切割工序。
9.如权利要求8所述的方法，其特征是：该开口利用一车床或一工具机所切割而成。
10.如权利要求8所述的方法，其特征是：该密封物由一银胶或一环氧化合物所构成。
11.如权利要求8所述的方法，其特征是：该压盖工序利用一粘着物将该顶盖置于该密封物上方。
12.如权利要求8所述的方法，其特征是：在进行完该单块切割工序后，需再进行一电性缺陷分析程序，该程序包含有下列步骤：
进行一移盖步骤，以将该顶盖自该密封物上方移除；
于该晶片的上表面进行一顶面测试；以及
于该晶片的下表面进行一底面测试。
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