CN1285179C - System and method for control clock recovery unit locking switching in 40Gb/s optical transmission - Google Patents
System and method for control clock recovery unit locking switching in 40Gb/s optical transmission Download PDFInfo
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- CN1285179C CN1285179C CNB2004101012360A CN200410101236A CN1285179C CN 1285179 C CN1285179 C CN 1285179C CN B2004101012360 A CNB2004101012360 A CN B2004101012360A CN 200410101236 A CN200410101236 A CN 200410101236A CN 1285179 C CN1285179 C CN 1285179C
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Abstract
The present invention provides a system and a method for controlling the locking and the switching of a clock recovery unit in a 40 Gb/s optical transmission system. The method comprises: 40 Gb/s optical receiving signals are converted into 40 Gb/s electrical signals; the 40 Gb/s electrical signals are divided into four paths of 10 Gb/s electrical signals; the four paths of serial 10 Gb/s electrical signals are respectively divided into parallel low speed electrical signals and low speed timing clocks, and state locking signals of each path of electrical signals are generated; the generated state locking signals of four paths of electrical signals are processed by logical combination to generate control signals; the output of the timing clocks is controlled by the generated control signals, and the timing clocks are locked on reference clocks or receiving data. The present invention utilizes loosing lock errors of the four paths of 10G electrical signals which are divided by the 40 Gb/s receiving signals as a basis which judges whether the 40 Gb/s receiving data is usable, and consequently, the present invention simply realizes the reversed process for controlling the locking of the clock recovery unit in the 40 Gb/s optical transmission system.
Description
Technical field
The present invention relates to the automatic clock recovery of 40Gb/s optical receiver in the 40Gb/s optical transmission system, relate in particular to a kind of system and method for control clock recovery unit locked switching in the 40Gb/s optical transmission system.
Background technology
Clock recovery is the required critical function of communication system, and the core circuit of clock recovery is phase-locked loop (Phase-Locked Loop).The effect of phase-locked loop is to recover synchronised clock from data, supplies follow-up data timing usefulness again, suppresses shake and drift that received signal produces in transmission course.
Phase-locked loop is a reponse system, theory diagram as shown in Figure 1, generally form by phase discriminator (Phase Detector), low pass filter (LPF) and voltage controlled oscillator (VCO), the phase discriminator rising edge that relatively F REF imports and F B imports, if F REF input appears at before the F B input, represent that then voltage controlled oscillator (VCO) moves too slowly, PD produces Pump Up signal, and this signal lasts till the rising edge of F B input always.If F B input appears at before the FREF input, PD produces Pump Down signal, and this signal is triggered at the rising edge of F B input, and lasts till the rising edge of FREF input always.The VCO slow running is forced in this Pump Down pulse.Like this, PD forces VCO to move sooner according to the relation of F REF and F B input or is slower.Phase-locked loop is designed in the frequency band of certain limit and operates, if incoming frequency outside this frequency band, then circuit will can not followed the tracks of input signal, F REF and F OUT are with inequality.Need only F REF and remain in the following range of circuit, then F REF=F OUT.If but F REF has shifted out scope, then circuit is with losing lock.
Under the normal condition, clock recovery circuitry is from receiving the extracting data clock, i.e. PLL output clock lock is receiving on the data.When receiving loss of data or receiving data and reference clock frequency deviation when overruning, the output clock of PLL and the frequency deviation of reference clock will exceed locking range, and PLL is in out-of-lock condition.Because the output clock of PLL and the frequency deviation of reference clock have exceeded the pullin banwidth of loop, recover just often when receiving data, PLL can't enter lock-out state once more by catching.In order to address this problem, to contain in the chip of clock and data recovery (CDR) function and generally all designed the locking detection circuit, as shown in Figure 2.Under the normal operation, the output of PLL is locked in input data Din, the output clock that the locking detection circuit can be monitored PLL continuously 1. with reference clock frequency deviation 2., when the input data failure, when frequency deviation surpasses preset range, this circuit will be controlled phase frequency detector (PFD) and switch to PLL, makes the output clock lock of PLL on reference clock.Because the participation of PFD, the PLL loop has bigger pullin banwidth, and reference clock can be exported clock to PLL and be drawn to lock-in range.Like this, but recover the time spent when data, the frequency deviation of the output clock of PLL and reception data is less than the pullin banwidth of loop, switch to the PLL loop with phase discriminator (PD) this moment again, like this, can be by catching, the output clock of PLL is locked in again receives on the data.The locking detection circuit also can produce a lock-out state output (LOCK), and the user can judge that PLL is in out-of-lock condition or is locked in the reception data mode among the CDR according to the height of lock-out state pin level.For example contain a locking detection circuit in the CDR function of the 10Gbit/s deserializer LXT16706 of Intel, the frequency deviation that detects the output clock of PLL and reference clock when it will produce losing lock alarm (LOCK ERROR) when surpassing 500ppm, and control PLL will export clock lock on reference clock, realize the frequency pulling process.
At present, the research work of 40Gb/s optical transmission system is just carrying out like a raging fire, this has wherein run into considerable technical barrier, raising along with data rate, the locking detection of reliable design and the difficulty of control circuit increase thereupon in clock recovery module, also do not have chip can finish locking detection and the controlled function of 40Gb/s signal CDR.And, the producer of the 40Gb/s speed CRU that can provide on the market is also few in number, the clock recovery unit that adopts in system (CRU) module uses the 2.5GHz clock as the reference clock, can recover the 20GHz clock with data sync from the 40Gb/s signal, this module principle block diagram as shown in Figure 3.The input of 40Gb/s signal, phase discriminator PD, charge pump CP, low pass filter LPF, voltage controlled oscillator VCO output feedback are formed a phase-locked loop.Under the normal condition, the output of VCO is locked on the 40Gb/s signal of input.Module provides the another one phase-locked loop by selector, and different with previous loop is, phase frequency detector PFD has substituted phase discriminator PD, and the input signal of PFD is the reference clock of 2.5GHz, and the output of VCO is locked on the reference clock in this loop.This module can not provide the locking detection circuit, and the control pin of selector only is provided, and is used to control the output clock lock of phase-locked loop in data or reference clock.Control PLL is locked in data, no matter then whether the input data are effective, the output clock is locked in the input data always, the frequency of the output clock in the time of data failure is unpredictable, and and reference clock frequency between frequency difference excessive, recover just often in data, because this big frequency difference exists, the PLL loop can't enter locking once more by catching.In order to finish normal clock recovery function, need design and a kind ofly can judge voluntarily whether receive data available, and whether PLL output clock surpass lock-in range with the reference clock frequency deviation, realize that in correct PLL exports the system of clock distraction procedure.This realizes the key of 40Gb/s system development just at present.
Summary of the invention
The object of the invention provides a kind of system and method for control clock recovery unit locked switching in the 40Gb/s optical transmission system, in the 40Gb/s optical transmission system, when but data return to the time spent from unavailable, when PLL output clock frequency deviation goes beyond the scope, in the time of can't recovering automatically, how to control PLL and be locked in reference clock, eliminate the frequency deviation that the output clock surpasses the PLL catching range, and then PLL is exported clock lock to receiving on the data.In this process, how to realize whether automatic judgment data lost efficacy, when control CRU output be locked in reference to and when be locked in data,, be the problem that must solve just for the function of CRU solution auto switching.
The system of a kind of control clock recovery unit locked switching in the 40Gb/s optical transmission system provided by the invention comprises being used for the 40Gb/s light receiving signal is converted to the 40Gb/s optical receiver of the 40Gb/s signal of telecommunication; It is characterized in that this system further comprises:
The 1:4 Demultiplexing module is used for 40Gb/s signal of telecommunication branch is connected into 4 road 10Gb/s signals of telecommunication;
Deserializer is used for the 10Gb/s signal of telecommunication branch of serial is connected into parallel the low speed signal of telecommunication and low-speed clock, and produces the lock-out state signal of the signal of telecommunication;
Single-chip microcomputer, the lock-out state signal that 4 tunnel deserializer modules are produced carries out the incompatible generation control signal of logical groups;
The 40Gb/s clock recovery module is used for being locked on reference clock or the reception data based on the control signal control clock output that single-chip microcomputer produces;
Wherein, whether judged by single-chip microcomputer in 4 road signals of telecommunication of deserializer output has one road 10Gb/s signal of telecommunication not have the losing lock alarm, if have, then control the 40Gb/s clock recovery module and lock onto the reception data, and judge further whether the reception data are available, unavailable, then control the 40Gb/s clock recovery module and lock onto the enterprising line frequency traction of reference clock, available, then finish whole clock recovery process;
If single-chip microcomputer is judged 4 road 10Gb/s signals of telecommunication losing lock alarm is arranged entirely, show that then the reception data are unavailable, and lock onto the enterprising line frequency traction of reference clock by Single-chip Controlling 40Gb/s clock recovery module.
Its feature of said system also is: described deserializer inside further comprises phase-locked loop; Also comprise the frame process chip, be used for low speed signal and clock that the deserializer module is sent here are carried out the framing processing.
The method of a kind of control clock recovery unit locked switching in the 40Gb/s optical transmission system provided by the invention is characterized in that comprising the steps:
(1) converts the 40Gb/s light receiving signal to the 40Gb/s signal of telecommunication;
(2) 40Gb/s signal of telecommunication branch is connected into 4 road 10Gb/s signals of telecommunication;
(3) the 10Gb/s signal of telecommunication of 4 tunnel serials is divided respectively be connected into parallel the low speed signal of telecommunication and low-speed clock, and produce the lock-out state signal of every road signal of telecommunication;
(4) carry out the incompatible generation control signal of logical groups by lock-out state signal to 4 road signals of telecommunication that produce;
(5) be locked on reference clock or the reception data based on the control signal control clock output that produces;
(6) when clock output is locked on the reference clock, judged whether that one road signal of telecommunication does not have the losing lock alarm, if having, then lock onto the reception data, otherwise, the locking reference clock;
(7) be locked in when receiving on the data when clock output, judge whether receive data available, unavailablely then be locked on the reference clock and carry out the frequency pulling process, available this clock lock process that then finishes.
Its feature of said method also is: the logical combination process in the step (4) is: when the losing lock alarm all appears in the lock-out state signal of 4 road signals of telecommunication, produce the output of control clock and be locked on the reference clock; In addition, producing the output of control clock is locked on the reception data.
Whether available the losing lock alarm (LOCK ERROR) of the present invention by 4 road 10G signals of telecommunication that pick out with 40Gb/s received signal branch receive data basis for estimation as 40Gb/s, thereby realized control clock recovery unit locked switching process in the 40Gb/s optical transmission system simply.Realized output stable clock when 40Gb/s reception data are unavailable, realized VCO output frequency distraction procedure automatically, when recovering after outage of 40Gb/s dwdm system or the line fault, need not Artificial Control like this, system can recover available automatically.
Description of drawings
Fig. 1 is a principle of phase lock loop block diagram in the prior art;
Fig. 2 contains clock and data recovery (CDR) the chip theory diagram that locks detection circuit in the prior art;
Fig. 3 is a 40Gb/s clock recovery unit theory diagram;
Fig. 4 is a 40Gb/s system receiving terminal theory diagram of the present invention;
Fig. 5 is a 40Gb/s CRU locked switching program flow diagram of the present invention;
Fig. 6 is a technical scheme theory diagram of the present invention;
Fig. 7 is the experimentation figure of verification technique scheme;
Fig. 8 is that the 40Gb/s receiving optical signals is lost or signal frequency deviation optical receiver output electric eye figure when going beyond the scope;
Fig. 9 is the 20GHz clock schematic diagram that the 40Gb/s receiving optical signals is lost or signal frequency deviation recovers when going beyond the scope;
Figure 10 is that the 40Gb/s receiving optical signals is lost or the signal frequency deviation 10Gb/s signal electric eye figure that the time-division picks out that goes beyond the scope;
But Figure 11 recovers the time spent at the 40Gb/s receiving optical signals, because the VCO of CRU output has exceeded lock-in range, CRU can not recover 20GHz clock schematic diagram;
Figure 12 is the CRU output schematic diagram that is locked on the reference clock;
Figure 13 is the 10Gb/s signal eye diagram of CRU output clock lock to reference clock the time;
But Figure 14 recovers the time spent through being locked in the 20GHz clock schematic diagram on the data after the frequency pulling again when data;
Figure 15 be the 40Gb/s receiving optical signals continue unavailable during, the eye pattern of the output clock lock of CRU continual 10Gb/s signal when switching back and forth between reference clock and data.
Embodiment
The theory diagram of enforcement system of the present invention as shown in Figure 4.Receiving terminal optical signals 40Gb/s optical receiver converts the signal of telecommunication to; One road 40Gb/s signal of telecommunication P is connected into 4 road 10Gb/s signals of telecommunication by branch, one road 4Gb/s signal of telecommunication N is imported into 40Gb/s CRU, judge through the locking detection circuit whether the reception data of 4 road 40Gb/s signals of telecommunication are available, when data are unavailable, locking detection circuit control CRU locks onto and realizes frequency pulling on the reference clock, but recover the time spent when data, lock detection circuit control CRU and recover to lock onto on the reception data, guarantee that CRU correctly recovers the 20GHz clock from the reception data.
The flow chart of enforcement the inventive method as shown in Figure 5.The losing lock alarm (LOCK ERROR) of 4 road 10Gb/s signals of telecommunication that pick out with 40Gb/s received signal branch receives the disabled basis for estimation of data as 40Gb/s.When 4 road 10Gb/s signals of telecommunication have losing lock when alarm simultaneously, the output of 40Gb/s CRU is locked on the reference clock; As long as when having the losing lock alarm of one road 10Gb/s signal of telecommunication to disappear, the output that is about to 40Gb/s CRU recovers to lock onto and receives on the data.
Below in conjunction with Fig. 6 specific embodiments of the invention are described.As shown in Figure 6, each functions of components is described below:
Parts are 1.: the 40Gb/s optical receiver converts the 40Gb/s light receiving signal to the 40Gb/s signal of telecommunication;
Parts are 2.: the 1:4 Demultiplexing module, divide 40Gb/s signal of telecommunication P to be connected into 4 road 10Gb/s signals of telecommunication;
Parts are 3.: deserializer (Demux), the 10Gb/s signal of telecommunication branch of serial is connected into parallel the low speed signal of telecommunication and low-speed clock, give single-chip microcomputer with the lock-out state signal reporting of inner phase-locked loop, show inner phase-locked loop-locking on the serial 10Gb/s signal of telecommunication if lock-out state is a high level, the low speed data of output and clock lock are in the 10Gb/s serial input data; If lock-out state is a low level, show the losing lock alarm to occur that the VCO output frequency of inner phase-locked loop has departed from reference clock and surpassed preset range;
Parts are 4.: the frame process chip, and low speed signal that deserializer (Demux) module is sent here and clock carry out framing to be handled;
Parts are 5.: single-chip microcomputer, the lock-out state signal that 4 tunnel deserializer (Demux) module is reported carry out output CRU locked switching control signal behind the logical combination.If losing lock alarm (low level) all appears in 4 road lock-out state signals, then single-chip microcomputer output CRU locked switching control signal is a low level, and control CRU output clock lock is on reference clock; If having one road lock-out state signal at least is high level, then single-chip microcomputer output CRU locked switching control signal is a high level, and control CRU output locking receives on the data;
Parts are 6.: 40Gb/s clock recovery module (CRU), finish from the function of the reception extracting data 20GHz synchronised clock of 40Gb/s signal of telecommunication N, its output of CRU locked switching control signal control of single-chip microcomputer output is locked on the reference clock or receives on the data, if the locked switching control signal is a low level, then its output is locked on the reference clock; If the locked switching control signal is a high level, its output is locked in and receives on the data.
Will judge at first in technical scheme of the present invention whether receive data available, it is excessive to receive unavailable 40Gb/s Received Loss Of Signal (LOS) and the receive clock frequency deviation of comprising of data.This function is finished by single-chip microcomputer.Single-chip microcomputer is judged the level height of the lock-out state signal that 4 tunnel deserializer (Demux) module reports, if 4 road lock-out state signals be low entirely, shows that then 4 road 10Gb/s data have the losing lock alarm entirely, and it is unavailable to be judged as 40Gb/s reception data this moment; As long as it is high level that one road lock-out state signal is arranged, show to have at least the alarm of one road 10Gb/s data losing lock to disappear, it is available being judged as 40Gb/s reception data this moment.
Secondly, to solve exactly and receive data when unavailable, the inside PLL of CRU be realized the problem of frequency pulling, as previously mentioned, if the frequency difference between the output clock of PLL and the correct data clock surpasses the catching range of PLL, PLL can not enter seizure once more up to final locking.This function is to finish by Single-chip Controlling CRU.To receive data unavailable if single-chip microcomputer detects, and then CRU locked switching control signal put lowly, and the inside PLL of control CRU locks onto on the reference clock, carries out the frequency pulling process.
Be that the inside PLL of CRU output clock is recovered to lock onto in correct on the reception data at last.Carry out after the frequency pulling process, the losing lock alarm of 4 road 10Gb/s data disappears, at this moment single-chip microcomputer is judged as 40Gb/s to receive data is available, so locking onto, control CRU receives on the data, if the 40Gb/s receiving optical signals of this moment has recovered available, the automatic clock recovery process of then whole 40Gb/s optical receiver is finished; If the 40Gb/s receiving optical signals of this moment is still unavailable, at this moment the losing lock alarm of 4 road 10Gb/s signals of telecommunication will can appear again simultaneously, it is unavailable that this moment, single-chip microcomputer was judged as 40Gb/s reception data, and the output of therefore controlling CRU is switched to and locks onto on the reference clock.During the 40Gb/s receiving optical signals is lasting unavailable, the output clock lock of CRU will continually between reference clock and data be switched back and forth, but recover the time spent up to the 40Gb/s data, CRU locks onto on the data once more, the losing lock alarm no longer appears in the deserializer of 10Gb/s, switch and stop, this just finishes the automatic clock recovery process of whole 40Gb/s optical receiver.
In order to verify technical scheme of the present invention, we have done following experiment, and experimentation as shown in Figure 7.
The optical receiver of 40Gb/s system receives light signal and converts to after the signal of telecommunication, and 40Gb/s signal of telecommunication branch is connected into the signal of telecommunication of 4 road 10Gb/s, gives 4 deserializer.Lose or signal frequency deviation when going beyond the scope when the 40Gb/s receiving optical signals, the data of optical receiver output will be that a slice is fuzzy, as shown in Figure 8.The 20GHz clock that recover this moment from data also will be that a slice is fuzzy, as shown in Figure 9.Dividing 4 road 10Gb/s signal electric eye figure that pick out this moment also will be that a slice is fuzzy, as shown in figure 10.4 tunnel deserializer receive such 10Gb/s signal, can produce the LOCKERROR alarm simultaneously.Even this moment, the 40Gb/s receiving optical signals recovered available, because the output of CRU has exceeded lock-in range, CRU recovers circuit 20GHz clock, and still a slice is fuzzy, as shown in figure 11.Therefore need draw CRU with reference clock, then with the output clock lock of 40Gb/s CRU to reference clock, make the output of VCO enter lock-in range, the output of 20GHz clock is arranged, as shown in figure 12 this moment.The 10Gb/s signal electric eye figure of this moment as shown in figure 13.Then, the LOCK ERROR alarm of 4 tunnel deserializer all can disappear, the output clock recovery that program can be controlled CRU locks onto on the reception data, there are this moment 20GHz clock output that recovers and the 20GHz clock that is locked on the reference clock to export the difference that has on frequency and the phase place, because data and reference clock have little frequency deviation, as shown in figure 14.If the 40Gb/s receiving optical signals of this moment has recovered available, the automatic clock recovery process of then whole 40Gb/s optical receiver is finished; If the 40Gb/s receiving optical signals of this moment is still unavailable, at this moment will can occur the losing lock alarm of 4 road 10Gb/s signals of telecommunication again simultaneously, so the output of CRU can be switched to again and is locked on the reference clock; During the 40Gb/s receiving optical signals was lasting unavailable, the output clock lock of CRU will continually between reference clock and data be switched back and forth, and the eye pattern of the 10Gb/s signal of this moment is fuzzy a little while clear a little while, as shown in figure 15.But recover the time spent up to data, CRU locks onto on the data once more, and the losing lock alarm no longer appears in the deserializer of 10Gb/s, switches to stop, and this just finishes the automatic clock recovery process of then whole 40Gb/s optical receiver.This process similar with other ce circuits in the function of locking detection circuit, this locking detection circuit is monitored the output clock of VCO and the frequency deviation of reference clock continuously, when frequency deviation surpasses preset range, will allow reference clock that the VCO output frequency is drawn in the lock-in range.
Experiment showed, to have reached design object fully, successfully realized the automatic clock recovery function of 40Gb/s optical receiver.
Claims (5)
1, a kind of system of control clock recovery unit locked switching in the 40Gb/s optical transmission system comprises being used for the 40Gb/s light receiving signal is converted to the 40Gb/s optical receiver of the 40Gb/s signal of telecommunication; It is characterized in that this system further comprises:
The 1:4 Demultiplexing module is used for 40Gb/s signal of telecommunication branch is connected into 4 road 10Gb/s signals of telecommunication;
Deserializer is used for the 10Gb/s signal of telecommunication branch of serial is connected into parallel the low speed signal of telecommunication and low-speed clock, and produces the lock-out state signal of the signal of telecommunication;
Single-chip microcomputer, the lock-out state signal that 4 tunnel deserializer modules are produced carries out the incompatible generation control signal of logical groups;
The 40Gb/s clock recovery module is used for being locked on reference clock or the reception data based on the control signal control clock output that single-chip microcomputer produces;
Wherein, whether judged by single-chip microcomputer in 4 road signals of telecommunication of deserializer output has one road 10Gb/s signal of telecommunication not have the losing lock alarm, if have, then control the 40Gb/s clock recovery module and lock onto the reception data, and judge further whether the reception data are available, unavailable, then control the 40Gb/s clock recovery module and lock onto the enterprising line frequency traction of reference clock, available, then finish whole clock recovery process;
If single-chip microcomputer is judged 4 road 10Gb/s signals of telecommunication losing lock alarm is arranged entirely, show that then the reception data are unavailable, and lock onto the enterprising line frequency traction of reference clock by Single-chip Controlling 40Gb/s clock recovery module.
2,, it is characterized in that described deserializer inside further comprises phase-locked loop according to the system of claim 1.
3, according to the system of claim 1 or 2, it is characterized in that further comprising the frame process chip, be used for low speed signal and clock that the deserializer module is sent here are carried out the framing processing.
4, a kind of method of control clock recovery unit locked switching in the 40Gb/s optical transmission system is characterized in that may further comprise the steps:
(1) converts the 40Gb/s light receiving signal to the 40Gb/s signal of telecommunication;
(2) 40Gb/s signal of telecommunication branch is connected into 4 road 10Gb/s signals of telecommunication;
(3) the 10Gb/s signal of telecommunication of 4 tunnel serials is divided respectively be connected into parallel the low speed signal of telecommunication and low-speed clock, and produce the lock-out state signal of every road signal of telecommunication;
(4) carry out the incompatible generation control signal of logical groups by lock-out state signal to 4 road signals of telecommunication that produce;
(5) be locked on reference clock or the reception data based on the control signal control clock output that produces;
(6) when clock output is locked on the reference clock, judged whether that one road signal of telecommunication does not have the losing lock alarm, if having, then lock onto the reception data, otherwise, the locking reference clock;
(7) be locked in when receiving on the data when clock output, judge whether receive data available, unavailablely then be locked on the reference clock and carry out the frequency pulling process, available this clock lock process that then finishes.
5, according to the method for claim 4, it is characterized in that the logical combination process in the step (4) is: when the losing lock alarm all appears in the lock-out state signal of 4 road signals of telecommunication, produce the output of control clock and be locked on the reference clock; In addition, producing the output of control clock is locked on the reception data.
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| CNB2004101012360A CN1285179C (en) | 2004-12-17 | 2004-12-17 | System and method for control clock recovery unit locking switching in 40Gb/s optical transmission |
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| CNB2004101012360A CN1285179C (en) | 2004-12-17 | 2004-12-17 | System and method for control clock recovery unit locking switching in 40Gb/s optical transmission |
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| US7467335B2 (en) * | 2005-07-01 | 2008-12-16 | Alcatel-Lucent Usa Inc. | Method and apparatus for synchronizing data channels using an alternating parity deskew channel |
| CN1983888B (en) * | 2006-06-07 | 2010-10-27 | 华为技术有限公司 | Device and method for restoring clock |
| EP2137847B1 (en) * | 2007-02-28 | 2018-06-27 | Finisar Corporation | Multi-mode integrated circuit for use in optoelectronic devices |
| CN118100915B (en) * | 2024-04-28 | 2024-07-02 | 成都电科星拓科技有限公司 | CDR circuit |
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