CN1283060C - Data receiving method based on clock signal and apparatus thereof - Google Patents
Data receiving method based on clock signal and apparatus thereof Download PDFInfo
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- CN1283060C CN1283060C CN 03102893 CN03102893A CN1283060C CN 1283060 C CN1283060 C CN 1283060C CN 03102893 CN03102893 CN 03102893 CN 03102893 A CN03102893 A CN 03102893A CN 1283060 C CN1283060 C CN 1283060C
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Abstract
The present invention relates to a data receiving method based on a clock signal and a device thereof. A high-frequency clock is used by the present invention for sampling and inputting signals, phases of input signals are adjusted according to sampling results of the input signals, and then data reception is carried out according to the adjusted input signals. Thus, the present invention achieves the automatic adjustment of an input clock phase or an input data phase, satisfactory data sampling effects are obtained under the condition of poor signal quality and application environment, and the ability for adapting various environments of a communication controller is enhanced. The present invention does not need software intervention in the process of application, and the difficulty of software development and the possibility of making mistakes are greatly lowered.
Description
Technical field
The present invention relates to network communications technology field, relate in particular to a kind of data receive method and device thereof based on clock signal.
Background technology
At present, in the network communications technology to the reception of data normally according to the clock signal sampled data signal, obtain data.For example, the communication controler that is used for receiving data information in the network service at present is in the design application process, often running into by plate level or opposite equip. provides the situation of port clock and port data to it, and the active data signal is collected from circuit according to clock signal by the synchronous port of communication controler and to do further processing; And the delay difference that clock signal and data-signal produce in transmission course will cause clock signal to change with respect to the phase place of data-signal, i.e. clock rising edge bias data steady component, thus can't carry out the sampling of data according to this clock signal.
As shown in Figure 1, when clock rising edge correspondence the stabilization sub stage of data, communication controler is sampled data well.If but because the time delay in the transmission course, make the phase relation appearance situation as shown in Figure 2 of clock and data, be the unstable stage that clock rising edge correspondence data, will cause normally sampled data of communication controler port, promptly communication controler can't operate as normal.
For the method that addresses the above problem common employing is to utilize software control that clock is anti-phase.If find that promptly the input clock phase place is not ideal enough, cause the data sampling instability after, with software control that clock is anti-phase in advance.As shown in Figure 3, clock 1 is original input clock, can't normally sample in the range of instability of its rising edge corresponding data.After software control is anti-phase with clock 1, just can obtain clock 2, and clock 2 just in time is in desired phase, can guarantee the normal sampling of data.
But address the above problem the complexity that increases software design greatly by software design.Because no matter whether clock phase is desirable, can obtain the value of or " 0 " or " 1 " to the sampling of data-signal.Be to judge whether and carry out reverse process to clock only many times by this sampled value software.Normally in the circuit debugging process, do according to the actual result who measures by the designer and subjective to judge, artificially on software, be made as anti-phase or inversion clock not then to a certain road port.When software application during in different circuit design, will judge one by one according to different RSTs, revise software one by one.When design is very big, and the software application environment is miscellaneous the time, and this work will consume a large amount of time of designer, and increases greatly and wrong chance occurs.
In some designs, the phase place of input data and clock is not changeless.Same circuit and software all can be exported the clock of out of phase under different time, different external environment.At this moment still adopt the phase place of predefined method control clock obviously cannot.Therefore, must make strict regulation to using environment and signal quality when this method is used, thereby limit the range of application of communication controler, reduce the adaptive capacity of communication controler.
With the anti-phase adjustment method of clock a hypothesis is arranged, the quality that is exactly data-signal can be too not poor, and its stabilization sub stage surpasses the over half of signal period.If therefore rising edge can't be adopted stable data, trailing edge necessarily can be adopted so.But in actual design, if the poor quality of data-signal, the anti-phase adjustment method of clock is just inapplicable.As shown in Figure 4, data signal quality is very poor, and its stabilization sub stage is very short, less than half of signal period.This moment, positive phase clock (clock 1) or inversion clock (clock 2) all can't be adopted stable data.
Summary of the invention
The invention provides a kind of data receive method and device thereof,, guarantee the reliability of communication controler port data sampling to improve the scope of application of communication controler based on clock signal.
The object of the present invention is achieved like this: described data receive method based on clock signal, comprise: the high frequency clock sampled input signal that utilizes relative input clock signal, and according to the sampled result of input signal the input signal phase place is adjusted, carry out the reception of data then according to adjusted input signal.
Described input signal is input clock signal and input data signal.
This method further comprises:
A, utilize high frequency clock respectively input clock signal and input data signal to be carried out sample count, and need the phase value adjusted between definite input clock signal and input data signal;
B, input signal is carried out the phase place adjustment according to the phase value of needs adjustment between input clock signal and input data signal;
C, for adjusted input signal, according to input clock signal to the input data signal reception of sampling.
Described step a comprises:
A1, utilize the high frequency clock signal of hardware inside that input clock signal is carried out sample count, determine the Cycle Length of input clock signal, and determine phase pushing figure input data signal stationary phase with respect to the hopping edge of input data signal according to the Cycle Length of the input clock signal of determining;
A2, utilize the high frequency clock signal of hardware inside that input data signal is sampled, and the phase pushing figure between definite input clock signal hopping edge and input data signal hopping edge;
A3, two phase pushing figures that obtain according to step a1 and step a2 are determined the phase value that needs are adjusted between input clock signal and input data signal.
Described step b is: the phase value according to needs adjustment between input clock signal and input data signal carries out the phase place adjustment to input clock signal.
Described step b is: the phase value according to needs adjustment between input clock signal and input data signal carries out the phase place adjustment to input data signal.
A kind of data sink of realizing based on said method based on clock signal comprises:
High frequency clock generator: be used to produce high frequency clock signal, and export to the phase deviation computing module;
Phase deviation computing module: introduce input clock signal, input data signal and high frequency clock signal, calculate the stationary phase of definite input data signal and the phase pushing figure between input clock signal, export to phase adjusting module;
Phase adjusting module: the phase pushing figure of receiving phase calculations of offset module output, and according to this phase pushing figure the phase of input signals that comprises input clock signal and input data signal is adjusted, export to the Data Receiving processing module after the adjustment;
The Data Receiving processing module: carry out the Data Receiving processing according to the adjusted input signal of input clock signal and input data signal that comprises, and dateout sampling reception result.
Described phase deviation computing module comprises:
Input clock cycle counter: the high frequency clock signal of introducing the output of input clock signal and high frequency clock generator, the Cycle Length that calculate to obtain input clock signal is exported to the phase deviation calculating sub module, exports high frequency clock signal simultaneously and the input clock signal cycle count value is obtained submodule to initial phase;
Initial phase obtains submodule: high frequency clock signal and input clock signal cycle count value according to the output of input clock cycle counter are calculated the initial phase offset value of determining between input clock signal and input data signal, export to phase adjusting module;
Phase deviation calculating sub module:, determine that the phase of input signals adjusted value that comprises input clock signal and input data signal exports to phase adjusting module according to the input clock signal Cycle Length of input clock cycle counter output.
Described phase adjusting module is: the clock phase adjusting module;
Described Data Receiving processing module is: receive the input clock signal after the adjustment of process phase place is handled, and according to the input data signal that the input clock signal of this reception is sampled and received, carry out data sampling and receive processing.
Described phase adjusting module can also be the data phase adjusting module;
Described Data Receiving processing module can also for: receive the input data signal after handling through the phase place adjustment, and the input data signal after handling through the phase place adjustment according to the input clock signal sampling that receives, carry out data sampling and receive and handle.
By technique scheme as can be seen, the present invention adopts high frequency clock sampling input clock and input data, and input clock or input data are adjusted.Therefore, the present invention has realized when input data signal and clock signal phase occurring and deviation occurs and can't normally sample, can automatically adjust to input clock phase place or input data phase by hardware means, promptly realize this function at the inner curing circuit that adopts of phy chip, relatively obtain satisfied data sampling effect under the condition of severe at signal quality and applied environment, promptly the quality requirement to input signal obviously descends, strengthened the all-environment ability of adaptation of communication controler, can accelerate simultaneously the speed of data acquisition process, improve the stability of data acquisition.And the present invention need not software intervention in the process of using, the possibility that greatly reduces the software development difficulty and make mistakes.
Description of drawings
Fig. 1 is desirable clock and data phase graph of a relation;
Fig. 2 is nonideal clock and data phase graph of a relation;
Fig. 3 is reverse adjusted clock of clock and data phase graph of a relation;
Fig. 4 is can't be by reverse clock and the data phase graph of a relation of adjusting of clock;
Fig. 5 is structural representation Fig. 1 of device of the present invention;
Fig. 6 is structural representation Fig. 2 of device of the present invention;
Fig. 7 is structural representation Fig. 3 of device of the present invention;
Fig. 8 is the schematic diagram of high frequency sampling input clock;
Fig. 9 is the schematic diagram of sampled data among the present invention;
Figure 10 is for adjusting the schematic diagram of clock phase;
Figure 11 is the flow chart of method of the present invention;
Figure 12 is the schematic diagram of high-speed data phase place.
Embodiment
Embodiment such as Fig. 5, Fig. 6, shown in Figure 7 of data sink based on clock signal of the present invention specifically comprise:
The high frequency clock generator: be used to produce high frequency clock signal, high frequency clock signal is used for input signal is carried out sample count, and exports to the phase deviation computing module;
Phase deviation computing module: introduce input clock signal, input data signal and high frequency clock signal, calculate the stationary phase of definite input data signal and the phase pushing figure between the input clock signal hopping edge, export to phase adjusting module, so that phase adjusting module is carried out the adjustment of input clock signal or input data signal phase place according to this phase pushing figure;
Described phase deviation computing module further comprises:
Input clock cycle counter: the high frequency clock signal of introducing the output of input clock signal and high frequency clock generator, the Cycle Length that calculate to obtain input clock signal is exported to the phase deviation calculating sub module, exports high frequency clock signal simultaneously and the input clock signal cycle count value is obtained submodule to initial phase;
Initial phase obtains submodule: high frequency clock signal and input clock signal cycle count value according to the output of input clock cycle counter are calculated the initial phase offset value of determining between input clock signal and input data signal, export to phase adjusting module;
Phase deviation calculating sub module:, determine that the phase of input signals adjusted value exports to phase adjusting module according to the input clock signal Cycle Length of input clock cycle counter output.
Phase adjusting module: the phase pushing figure of receiving phase calculations of offset module output, and according to this phase pushing figure phase of input signals is adjusted, export to the Data Receiving processing module after the adjustment;
Described phase adjusting module can be clock phase adjusting module or data phase adjusting module; Promptly can reach the desired phase relation between clock phase and data phase by adjustment, also can reach the desired phase relation between clock phase and data phase by adjustment to the data phase place to clock phase;
The Data Receiving processing module: carry out Data Receiving according to adjusted input signal and handle, and dateout sampling reception result;
When the adjustment by clock phase reaches desired phase between clock phase and data phase and concerns, described Data Receiving processing module is: receive through the input clock signal after the phase place adjustment processing, and, carry out data sampling and receive processing according to the input data signal that the input clock signal of this reception is sampled and received.
When the adjustment by data phase reaches desired phase between clock phase and data phase and concerns, described Data Receiving processing module is: receive through the input data signal after the phase place adjustment processing, and, carry out the data sampling reception and handle according to the input data signal after the input clock signal sampling process phase place adjustment processing that receives.
The embodiment of the data receive method based on clock signal of the present invention such as Fig. 8, Fig. 9, Figure 10 and shown in Figure 11 specifically may further comprise the steps:
Step 1: input clock signal is counted with the inner high frequency clock of hardware, determine the Cycle Length of input signal, and determine phase pushing figure input data signal stationary phase with respect to the input data signal original position according to the Cycle Length of the input clock signal of determining;
As shown in Figure 8, with a high frequency clock signal input clock signal is carried out sample count, when input clock from " 0 " to " 1 " saltus step, begin counting, being counted by the saltus step of " 0 " to " 1 " each time of high frequency clock signal adds 1, finish counting once more during from " 0 " to " 1 " saltus step up to input clock signal, obtain the input clock signal Cycle Length that utilizes the high frequency clock signal sampling to obtain: 10;
Because between high frequency clock signal and the input clock signal is complete asynchronous relationship, might adopt labile state at the rising edge or the trailing edge of input clock signal, thereby cause 1～2 counting error, if but the frequency that guarantees relative input clock signal high frequency clock signal is enough high, counting error is negligible;
Hardware carries out computing to the cycle: the mid point that appears at whole cycle data stationary phase of common data-signal, the length of cycle data is identical with the length of clock cycle again, therefore here input clock cycle length is done and removed 2 computings, obtaining input data signal stationary phase is 5 with respect to the phase pushing figure of input data signal hopping edge; If in the data signal samples processing procedure specific (special) requirements is arranged, as require sampling, then do corresponding computing in view of the above at cycle data 1/3 place;
Step 2: utilize high frequency clock sample simultaneously input data signal and input clock signal and the phase pushing figure between definite input clock signal hopping edge and input data signal hopping edge;
Counter is whenever the rising edge of input clock just begins counting from " 0 ", from " 0 " to " 1 " or the variation from " 1 " to " 0 " always can take place in input data signal, if high frequency clock signal captures such hopping edge, just can obtain the relative phase deviant of input clock signal and input data signal according to the count value of current counter;
As shown in Figure 9, when input data signal generation saltus step, high frequency clock signal is " 1 " to the count value of input clock, and the phase pushing figure that can obtain them is " 1 ";
Step 3: two phase pushing figures according to step 1 and step 2 acquisition determine that the phase value of needs adjustment between input clock signal and input data signal is 6;
Step 4: the phase value according to needs adjustment between input clock signal and input data signal carries out the phase place adjustment to input signal;
As shown in figure 10, calculate and to move 6 high frequency period behind the input clock signal, just can guarantee the reliable samples of data-signal, so utilizing high frequency clock signal that input clock is made a call to 6 claps, promptly whenever count value be 6 o'clock be the rising edge of new clock just, the cycle of new clock is identical with former input clock cycle;
Certainly, can also carry out the phase place adjustment to input data signal, thereby make the desirable phase relation of maintenance between input clock signal and input data signal, to guarantee the reliable samples of data, as shown in figure 12, when input data signal falls behind input clock signal 1, and therefore ideal state can make a call to 4 to input data signal with high frequency clock to clap for falling behind 5 o'clock, is about to move 4 high frequency period behind the input data signal, promptly when count value is 5 (4+1), be the data hopping edge;
Step 5: for adjusted input signal, then according to input clock signal to the input data signal reception of sampling; Be that subsequent operation is handled according to input data signal and adjusted new clock without exception, can obtain satisfied sample effect.
Claims (9)
1, a kind of data receive method based on clock signal, it is characterized in that: utilize the high frequency clock sampling of relative input clock signal to comprise the input signal of input clock signal and input data signal, and the input signal phase place is adjusted according to sampled result at the input signal that comprises input clock signal and input data signal, then, carry out the reception of data according to adjusted input signal.
2, the data receive method based on clock signal according to claim 1 is characterized in that this method further comprises:
A, utilize high frequency clock respectively input clock signal and input data signal to be carried out sample count, and need the phase value adjusted between definite input clock signal and input data signal;
B, input signal is carried out the phase place adjustment according to the phase value of needs adjustment between input clock signal and input data signal;
C, for adjusted input signal, according to input clock signal to the input data signal reception of sampling.
3, the data receive method based on clock signal according to claim 2 is characterized in that described step a comprises:
A1, utilize the high frequency clock signal of hardware inside that input clock signal is carried out sample count, determine the Cycle Length of input clock signal, and determine phase pushing figure input data signal stationary phase with respect to the hopping edge of input data signal according to the Cycle Length of the input clock signal of determining;
A2, utilize the high frequency clock signal of hardware inside that input data signal is sampled, and the phase pushing figure between definite input clock signal hopping edge and input data signal hopping edge;
A3, two phase pushing figures that obtain according to step a1 and step a2 are determined the phase value that needs are adjusted between input clock signal and input data signal.
4, according to claim 2 or 3 described data receive methods based on clock signal, it is characterized in that described step b is: the phase value according to needs adjustment between input clock signal and input data signal carries out the phase place adjustment to input clock signal.
5, according to claim 2 or 3 described data receive methods based on clock signal, it is characterized in that described step b is: the phase value according to needs adjustment between input clock signal and input data signal carries out the phase place adjustment to input data signal.
6, a kind of data sink based on clock signal is characterized in that comprising:
High frequency clock generator: be used to produce high frequency clock signal, and export to the phase deviation computing module;
Phase deviation computing module: introduce input clock signal, input data signal and high frequency clock signal, calculate the stationary phase of definite input data signal and the phase pushing figure between input clock signal, export to phase adjusting module;
Phase adjusting module: the phase pushing figure of receiving phase calculations of offset module output, and according to this phase pushing figure the phase of input signals that comprises input clock signal and input data signal is adjusted, export to the Data Receiving processing module after the adjustment;
The Data Receiving processing module: carry out the Data Receiving processing according to the adjusted input signal of input clock signal and input data signal that comprises, and dateout sampling reception result.
7, the data sink based on clock signal according to claim 6 is characterized in that described phase deviation computing module comprises:
Input clock cycle counter: the high frequency clock signal of introducing the output of input clock signal and high frequency clock generator, the Cycle Length that calculate to obtain input clock signal is exported to the phase deviation calculating sub module, exports high frequency clock signal simultaneously and the input clock signal cycle count value is obtained submodule to initial phase;
Initial phase obtains submodule: high frequency clock signal and input clock signal cycle count value according to the output of input clock cycle counter are calculated the initial phase offset value of determining between input clock signal and input data signal, export to phase adjusting module;
Phase deviation calculating sub module:, determine that the phase of input signals adjusted value that comprises input clock signal and input data signal exports to phase adjusting module according to the input clock signal Cycle Length of input clock cycle counter output.
8, according to claim 6 or 7 described data sinks, it is characterized in that based on clock signal:
Described phase adjusting module is: the clock phase adjusting module;
Described Data Receiving processing module is: receive the input clock signal after the adjustment of process phase place is handled, and according to the input data signal that the input clock signal of this reception is sampled and received, carry out data sampling and receive processing.
9, according to claim 6 or 7 described data sinks, it is characterized in that based on clock signal:
Described phase adjusting module is: the data phase adjusting module;
Described Data Receiving processing module is: receive the input data signal after the adjustment of process phase place is handled, and sample through the input data signal after the phase place adjustment processing according to the input clock signal of reception, carry out data sampling and receive processing.
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| CN 03102893 CN1283060C (en) | 2003-01-27 | 2003-01-27 | Data receiving method based on clock signal and apparatus thereof |
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| CN 03102893 CN1283060C (en) | 2003-01-27 | 2003-01-27 | Data receiving method based on clock signal and apparatus thereof |
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Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100654771B1 (en) * | 2005-07-07 | 2006-12-08 | 삼성전자주식회사 | Display apparatus and control method thereof |
| CN101477338B (en) * | 2008-12-30 | 2011-05-18 | 华为技术有限公司 | Signal regulation method and apparatus |
| CN102332975A (en) * | 2011-06-03 | 2012-01-25 | 北京星网锐捷网络技术有限公司 | Method and device for self-adaptively sampling interface |
| CN103368720B (en) * | 2012-03-28 | 2016-03-30 | 中兴通讯股份有限公司 | The method and system of clock sampling self-adaptative adjustment |
| CN103378848B (en) * | 2012-04-26 | 2016-03-30 | 华为技术有限公司 | A kind of system of selection of sampling clock and device |
| CN103152155A (en) * | 2012-10-22 | 2013-06-12 | 杭州开鼎科技有限公司 | Method for fast clock data recovery |
| CN103018649B (en) * | 2012-11-26 | 2015-01-28 | 西北核技术研究所 | Automatic signal delay compensation method and system suitable for radiation effect test |
| CN105589828B (en) * | 2014-10-22 | 2018-11-30 | 炬芯（珠海）科技有限公司 | A kind of method and apparatus that high-speed interface data send and receive |
| CN105912487A (en) * | 2016-04-07 | 2016-08-31 | 上海斐讯数据通信技术有限公司 | Data timing sequence equalizing method and system |
| CN112765073A (en) * | 2019-11-04 | 2021-05-07 | 中车株洲电力机车研究所有限公司 | Data sampling method, system, storage medium and computer equipment |
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