CN1282990C - Method for fabricating strained crystalline layer on insulator, semiconductor structure and obtained semiconductor structure - Google Patents
Method for fabricating strained crystalline layer on insulator, semiconductor structure and obtained semiconductor structure Download PDFInfo
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- CN1282990C CN1282990C CNB2004100033711A CN200410003371A CN1282990C CN 1282990 C CN1282990 C CN 1282990C CN B2004100033711 A CNB2004100033711 A CN B2004100033711A CN 200410003371 A CN200410003371 A CN 200410003371A CN 1282990 C CN1282990 C CN 1282990C
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 126
- 239000012212 insulator Substances 0.000 title claims abstract description 100
- 238000000034 method Methods 0.000 title claims abstract description 51
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims abstract description 105
- 229910052732 germanium Inorganic materials 0.000 claims abstract description 87
- 239000000758 substrate Substances 0.000 claims abstract description 68
- 238000004519 manufacturing process Methods 0.000 claims abstract description 8
- 238000002425 crystallisation Methods 0.000 claims description 115
- 230000008025 crystallization Effects 0.000 claims description 115
- 239000011248 coating agent Substances 0.000 claims description 45
- 238000000576 coating method Methods 0.000 claims description 45
- 229920001296 polysiloxane Polymers 0.000 claims description 24
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 15
- 229910052799 carbon Inorganic materials 0.000 claims description 15
- 239000000463 material Substances 0.000 claims description 8
- 239000013078 crystal Substances 0.000 abstract description 10
- 230000003247 decreasing effect Effects 0.000 abstract 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 73
- 229910052710 silicon Inorganic materials 0.000 description 73
- 239000010703 silicon Substances 0.000 description 73
- 238000010586 diagram Methods 0.000 description 28
- 230000002349 favourable effect Effects 0.000 description 17
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 16
- 230000003139 buffering effect Effects 0.000 description 9
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- 238000005516 engineering process Methods 0.000 description 9
- 238000002513 implantation Methods 0.000 description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 230000008901 benefit Effects 0.000 description 6
- 230000008859 change Effects 0.000 description 6
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 5
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 5
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- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
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- 150000002290 germanium Chemical class 0.000 description 1
- GPRLSGONYQIRFK-UHFFFAOYSA-N hydron Chemical compound [H+] GPRLSGONYQIRFK-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76259—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along a porous layer
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Abstract
Provided is a simple method for manufacturing a semiconductor structure which has crystal of high quality and also has a highly strained crystalline semiconductor layer on an insulator. The method is provided with: a semiconductor donor substrate comprising germanium and/or an A(III)-B(V)-semiconductor; at least one first crystalline epitaxial layer, in a first step, wherein the content of germanium and/or the A(III)-B(V)-semiconductor of a buffer layer of the first layer is decreased during the first step; at least one insulator layer, in a second step; wherein the first layer is provided between the substrate and the insulator layer; the first layer, which is split in a third step; and at least one second crystalline epitaxial layer on the split first layer, in a fourth step.
Description
Technical field
The present invention relates to a kind of method, on insulator, make the semiconductor structure of strained crystalline layer and the semiconductor structure that utilizes its manufacturing at manufacturing strained crystalline layer on the insulator.
Background technology
Thin strained semiconductor layer such as silicon layer has favourable electronics, hole mobility characteristic.Therefore, this layer is almost all extremely important for microelectronic all spectra, and they can obtain at a high speed, the high performance device of low-power consumption because use.If with strained semiconductor layer transfer printing (transfer) to insulator layer, thereby obtain the structure of SOI (silicon-on-insulator (silicon-on-insulator)) and so on, then can more effective use strained semiconductor layer, known usually their superiority in microelectronics and Micromechanics field.
In the international SOI meeting of 2001 IEEE, people such as Cheng serve as the method that topic discloses SiGe (SiGe-on-insulator) structure on a kind of manufacturing insulator with " SiGe-on-insulator (SGOI): Substrate Preparation and MOSFET Fabrication for ElectronMobility Evaluation ".In this method, the gradual SiGe layer of growth on the monocrystalline silicon raw wafer.In the growth course of SiGe, the Ge content of SiGe increases gradually, reaches about 25% up to the degree of germanium.With this degree, growth loose SiGe layer (relaxed SiGe layer) on gradual SiGe layer.In addition, hydrogen ion is injected this pine SiGe layer, thereby in loose SiGe layer, form pre-reduction layer.After this, this injecting structure and silicon wafer are bonded together.After annealed, along pre-reduction layer, this connected structure be separated into two parts, thereby obtain SiGe structure and residual structure on the insulator.Then, strained silicon on the SiGe layer, thus obtain the Si-on-SiGe-on-insulator structure.
The shortcoming of the structure of said method is, the strain of the strained silicon layer on the SiGe layer can not be brought up to the value with great commercial significance.This is because under the situation of the danger of formation high dislocation density, the limited Ge content of SiGe layer can not be increased to and surpass 25% in not existing in the SiGe layer, wherein the characteristic electron of high dislocation density meeting appreciable impact strained silicon layer.
Summary of the invention
The purpose of this invention is to provide a kind of semiconductor structure and a kind of straightforward procedure that is used to be manufactured on the semiconductor structure that has high-crystal quality and high strained crystalline semiconductor layer on the insulator.
Strained crystalline layer is made in utilization on insulator method can realize this purpose, and this method comprises: setting comprises germanium and/or A (III)-B (V)-semi-conductive raw semiconductor substrate; At first step, at least one first crystallization epitaxial loayer is set, in second step, at least one insulator layer is set; Wherein the first crystallization epitaxial loayer is arranged between raw semiconductor substrate and the insulator layer, the first crystallization epitaxial loayer comprises resilient coating, during first step, the germanium of resilient coating and/or A (III)-B (V)-semi-conductive content is reduced to 50% to 80% ratio with the direction from the raw semiconductor substrate to insulator layer; At third step, the first crystallization epitaxial loayer is separated into two parts; And, on the part of insulator layer one side of the first crystallization epitaxial loayer, at least one second crystallization epitaxial loayer is set in the 4th step.。
Utilize this creativeness method, can make the semiconductor structure that germanium wherein and/or A (III)-B (V)-semi-conductive content reduce with the direction from the substrate to the second layer.Like this, can in ground floor, realize very high germanium and/or A (III)-B (V)-semi-conductive content, thereby obtain the second layer of high strain.Germanium and/or A (III)-B (V)-semi-conductive increase makes grows with fabricating low-defect-density to the small part ground floor, has obtained the second layer of high-crystal quality like this.Utilize this creativeness method, can easily high strain, the high-quality second layer be transferred on the insulator layer, thereby obtain a kind of benefit and semiconductor structure of combining of the very good electrical sub-feature of strained crystalline layer with soi structure.
According to a further embodiment of the invention, raw semiconductor substrate (1) is monocrystalline germanium wafer, monocrystalline A (III)-B (V)-semiconductor wafer, extension germanium layer or extension A (III)-B (V)-semiconductor layer.On these substrates, the ground floor of can grow high Ge content and high-crystal quality.Germanium wafer and/or A (III)-B (V)-semiconductor wafer is a stable substrate, like this, in manufacture process, can well handle the strained crystalline layer on the insulator.
In advantageous embodiment of the present invention, at first step, the germanium of resilient coating and/or A (III)-B (V)-semi-conductive content is reduced to about 40% to 80% germanium ratio, preferably is reduced to about 50% to 80% or about ratio of 60% to 80%.A large amount of like this germanium and/or A (III)-B (V)-semiconductor can obtain the second layer of high strain.
In a preferred embodiment of the invention, at first step, the silicone content of resilient coating is increased to about 30% to 60% silicon ratio, preferably is increased to about 20% to 50% or about ratio of 20% to 40%.At first step, increase silicon in proportion and can obtain good lax resilient coating, particularly good lax GeSi layer.
In another preferred embodiment of the present invention, the second crystallization outer layer growth is to the thickness that is lower than 50nm.Therefore this layer thickness subcritical thickness can prevent the hot dynamic instability of this layer.In this creativeness thin layer, can effectively produce strain.
In another preferred embodiment of the present invention, the first crystallization epitaxial loayer and/or the second crystallization epitaxial loayer comprise carbon.Be preferably a few percent, even be lower than 1% concentration of carbon, cause in the first crystallization epitaxial loayer and/or the second crystallization epitaxial loayer, having good alloy stability and high levels of strain.
The semiconductor structure of strained crystalline layer is made in utilization on insulator can further realize this purpose, and this semiconductor structure comprises: by the raw semiconductor substrate that comprises that germanium and/or A (III)-B (V)-semi-conductive first material constitutes; At least one crystallization epitaxial loayer; And at least one insulator layer; Wherein this at least one crystallization epitaxial loayer is the intermediate layer between raw semiconductor substrate and the insulator layer, this at least one crystallization epitaxial loayer comprises resilient coating, this resilient coating is to comprise germanium and/or A (III)-B (V)-semi-conductive synthetic, and germanium and/or A (III)-B (V)-semi-conductive content is reduced to 50% to 80% ratio with the direction from the raw semiconductor substrate to insulator layer.
This inventive structure is the intermediate product that is used for making strained crystalline layer on insulator layer.Owing to the germanium and/or A (III)-B (the V)-semiconductor that begin to reduce from substrate in the crystallization epitaxial loayer, so can be with fabricating low-defect-density, and with high germanium and/or A (III)-B (V)-semiconductor content, growth crystallization epitaxial loayer, this high-load are the bases of the high strain of further good growth, high-quality crystallizing layer on the crystallization epitaxial loayer of this inventive structure for example.
In preferred conversion example of the present invention, the raw semiconductor substrate is monocrystalline germanium wafer, monocrystalline A (III)-B (V)-semiconductor wafer, extension germanium layer or extension A (III)-B (V)-semiconductor layer.Each wafer and epitaxial loayer contain a large amount of germanium and/or A (III)-B (V)-semiconductor, like this, the crystallization epitaxial loayer that germanium and/or A (III)-B (V)-semi-conductive content is high of can on substrate, well growing, wherein the defect concentration of this crystallization epitaxial loayer is low.
In preferred example of the present invention, the germanium of crystallization epitaxial loayer and/or A (III)-B (V)-semi-conductive content is reduced to about ratio of 40% to 80%, preferably is reduced to about 50% to 80% or about ratio of 60% to 80%.The germanium of about 40% to 80% ratio and/or A (III)-B (V)-semiconductor make can be on the crystallization epitaxial loayer good growth strain crystallizing layer, and about ratio of 50% to 80% has more advantage for obtain higher strain in the upper junction crystal layer, and about scope of 60% to 80% of germanium is the most preferred range that produces very high strain in the crystallizing layer on the crystallization epitaxial loayer.
According to favourable example of the present invention, the silicone content of crystallization epitaxial loayer increases with the direction from the substrate to the insulator layer.Silicon increases in proportion, causes the good modification of lattice, obtains the low crystallization epitaxial loayer of defect concentration like this.
In another preferred embodiment of the present invention, silicone content is increased to about 20% to 60% silicon ratio, preferably is increased to about 20% to 50% or about ratio of 20% to 40%.The feasible crystallization epitaxial loayer that can obtain fabricating low-defect-density of about 20% to 60% silicon ratio, and can obtain good modification such as the top crystallization epitaxial loayer of silicon layer, and 20% to 50% silicon ratio is more favourable to the high crystalline of crystallization epitaxial loayer, thereby the extraordinary upper junction crystal layer of acquired character, silicon layer for example, 20% to 40% silicon ratio is the most favourable for producing high-quality crystallization epitaxial loayer, and this high-quality crystallization epitaxial loayer is the extraordinary basis that forms the high-quality strained crystalline layer on the crystallization epitaxial loayer.
In addition, utilize semiconductor structure can realize purpose of the present invention, this semiconductor structure comprises: semiconductor-based substrate; At least one insulator layer; And at least one first crystallization epitaxial loayer; At least one strain second crystallization epitaxial loayer, wherein the first crystallization epitaxial loayer is the intermediate layer between insulator layer and the strain second crystallization epitaxial loayer, insulator layer is the intermediate layer between the semiconductor-based substrate and the first crystallization epitaxial loayer, and the first crystallization epitaxial loayer comprises resilient coating, this resilient coating is to comprise germanium and/or A (III)-B (V)-semi-conductive synthetic, and germanium and/or A (III)-B (V)-semi-conductive content is reduced to 50% to 80% ratio with the direction from the strain second crystallization epitaxial loayer to insulator layer.
Because germanium and/or A (III)-B (V)-semi-conductive minimizing in the resilient coating, have low-down defect concentration to the small part ground floor, can on ground floor, produce like this and have the crystalline extra play of high-quality.In addition, this inventive structure combines the benefit of soi structure and the good conductive characteristic of strained crystalline layer.Strained layer can have very high strain, because can be adjusted to germanium in the ground floor and/or A (III)-B (V)-semi-conductive content very high.
In further favourable conversion example of the present invention, the germanium of resilient coating and/or A (III)-B (V)-semi-conductive content is reduced to about 40% to 80% germanium ratio, preferably is reduced to about 50% to 80% or about ratio of 60% to 80%.40% to 80% germanium and/or A (III)-B (V)-semiconductor content is higher, can on ground floor, produce the crystallization epitaxial loayer of high strain like this, silicon layer for example, and 50% to 80% ratio is more favourable for the top crystallization epitaxial loayer of realizing higher strain on ground floor, and 60% to 80% ratio is the most favourable for the crystallization epitaxial loayer (for example silicon layer) that produces very high strain on ground floor.
In another embodiment of the present invention, the silicone content of resilient coating increases with the direction from the second layer to the insulator layer.The increase of silicon causes well revising in the direction of the second layer lattice of resilient coating, thereby makes the part ground floor have the high-quality crystallinity at least, and this is the good basis that obtains the crystalline second layer of high-quality.
In another preferred example of the present invention, silicone content is increased to about 20% to 60% silicon ratio, preferably is increased to about 20% to 50% or about ratio of 20% to 40%.The content of about 20% to 60% silicon makes on ground floor good strained silicon, and 20% to 50% ratio is more favourable for obtain higher strained silicon layer on ground floor, and 20% to 40% ratio is the most favourable for obtain high strained silicon layer on ground floor.
In further favourable example of the present invention, the thickness of strained layer is lower than 50nm.This layer thickness causes the second layer to have good hot dynamic stability, therefore in this thin layer, can easily produce strain.
In another advantageous embodiment of the present invention, the first crystallization epitaxial loayer and/or the strain second crystallization epitaxial loayer comprise carbon.Carbon content makes that the ground floor and/or the second layer can be more stable, and shows better levels of strain.
Strained crystalline layer is made in utilization on insulator method can further realize purpose of the present invention, and this method comprises: setting comprises germanium and/or A (III)-B (V)-semi-conductive raw semiconductor substrate; At first step, at least one first crystallization epitaxial loayer is set, in second step, at least one second crystallization epitaxial loayer is set; Wherein the first crystallization epitaxial loayer is arranged between the raw semiconductor substrate and the second crystallization epitaxial loayer, the first crystallization epitaxial loayer comprises resilient coating, during first step, the germanium of resilient coating and/or A (the III)-direction of B (V)-semi-conductive content from the raw semiconductor substrate to the second crystallization epitaxial loayer is reduced to 50% to 80% ratio; At third step, at least one insulator layer is set; Wherein the second crystallization epitaxial loayer is arranged between the first crystallization epitaxial loayer and the insulator layer; And, between the first crystallization epitaxial loayer and the second crystallization epitaxial loayer, separate in the 4th step.Because the reduction of the germanium of resilient coating and/or A (III)-B (V)-semiconductor content, can making at least, the part ground floor has extraordinary crystallinity and fabricating low-defect-density, thereby produce high-quality second crystallizing layer, this second crystallizing layer can be arranged on the ground floor.From germanium and/or A (III)-B (V)-semiconductor as the raw semiconductor substrate, the germanium of resilient coating and/or A (III)-B (V)-semi-conductive content can be reduced to higher germanium and/or A (III)-B (V)-semiconductor content, thereby on ground floor, form second crystallizing layer of high strain, for example silicon layer.The further advantage of this creativeness method is, the good electrical sub-feature of the strain second layer and the benefit of soi layer can be combined, because second strained layer can be arranged on the insulator layer.This creativeness method comprises the easy steps sequence, so that easily make this creativeness semiconductor structure.
In further embodiment of the present invention, raw semiconductor substrate (1) is monocrystalline germanium wafer, monocrystalline A (III)-B (V)-semiconductor wafer, extension germanium layer or extension A (III)-B (V)-semiconductor layer.These substrates provide a large amount of germanium and/or such as A (III)-B (V)-semiconductor of GaAs, thereby good growth has the germanium and/or A (III)-B (the V)-semi-conductive ground floor of high-load on respective substrate.
In favourable example of the present invention, the second crystallization outer layer growth is to the thickness that is lower than 50nm.At this thickness, the second layer has hot dynamic stability, and can grow and have the second layer of high strain.
According to a further advantageous embodiment of the invention, at first step, the germanium of resilient coating and/or A (III)-B (V)-semi-conductive content is reduced to about 40% to 80% germanium ratio, preferably is reduced to about 50% to 80% or about ratio of 60% to 80%.40% to 80% germanium and/or A (III)-B (V)-semi-conductive ratio of resilient coating have formed the good basis of the high strain second layer, and 50% to 80% germanium ratio of ground floor highlyer should change favourablely for obtaining in the second layer, and about 60% to 80% germanium ratio is to realize the most favourable scope of very high strain in the second layer.
In another advantageous embodiment of the present invention, at first step, the silicone content of resilient coating is increased to about 20% to 60% silicon ratio, preferably is increased to about 20% to 50% or about ratio of 20% to 40%.Can be on ground floor with 20% to 60% the silicon ratio high strained silicon layer of growing, and 20% to 50% silicon ratio is favourable for realizing in the second layer on ground floor (such as silicon layer) that height should change, and about 20% to 40% silicon ratio is the most favourable for obtain very high strain in such as the second layer of silicon layer.
In addition, utilize the semiconductor structure of making strained crystalline layer on insulator can realize this purpose, this semiconductor structure comprises: by the raw semiconductor substrate that comprises that germanium and/or A (III)-B (V)-semi-conductive first material constitutes; At least one first crystallization epitaxial loayer; At least one second crystallization epitaxial loayer; And at least one insulator layer, wherein the first crystallization epitaxial loayer is the intermediate layer between the raw semiconductor substrate and the second crystallization epitaxial loayer, the second crystallization epitaxial loayer is the intermediate layer between the first crystallization epitaxial loayer and the insulator layer, the first crystallization epitaxial loayer comprises resilient coating, this resilient coating is to comprise germanium and/or A (III)-B (V)-semi-conductive synthetic, and germanium and/or A (III)-B (V)-semi-conductive content is reduced to 50% to 80% ratio with the direction from the raw semiconductor substrate to the second crystallization epitaxial loayer.
This inventive structure is the intermediate structure that is used for making strained crystalline layer on insulator layer.Because germanium and/or A (III)-B (V)-semiconductor content in the resilient coating reduce from the substrate to the second layer, so can make the germanium of resilient coating and/or germanium and/or A (III)-B (the V)-semiconductor that A (III)-B (V)-semiconductor content is reduced to high level, thereby make on ground floor and to produce the second layer with high strain.Germanium and/or A (III)-B (V)-semi-conductive reduces in proportion further to make to the small part ground floor and has fabricating low-defect-density, thereby produces the high-quality second layer.The further advantage of this inventive structure is, can produce second strained layer on insulator layer, therefore can easily begin to form soi structure from this inventive structure.
In further advantageous embodiment of the present invention, the raw semiconductor substrate is monocrystalline germanium wafer, monocrystalline A (III)-B (V)-semiconductor wafer, extension germanium layer or extension A (III)-B (V)-semiconductor layer.These substrates comprise a large amount of germanium and/or A (III)-B (V)-semiconductor, help high-quality growth like this and contain germanium and/or A (III)-B (V)-semi-conductive ground floor.
In another advantageous embodiment of the present invention, the germanium of ground floor and/or A (III)-B (V)-semi-conductive content is reduced to about ratio of 40% to 80%, preferably is reduced to about 50% to 80% or about ratio of 60% to 80%.40% to 80% germanium and/or A (III)-B (V)-semiconductor ratio makes on ground floor the high strain second layer of growth, and 50% to 80% ratio highlyer should change favourablely for producing in the second layer, and 60% to 80% ratio is the most favourable scope that forms the second layer of very high strain on ground floor.
In another favourable example of the present invention, the silicone content of resilient coating increases with the direction from the substrate to the insulator layer.The described increase of silicon makes the lattice of ground floor can adapt to this substrate well, makes low to the defect concentration of small part ground floor.
In further advantageous embodiment of the present invention, silicone content is increased to about 20% to 60% silicon ratio, preferably is increased to about 20% to 50% or about ratio of 20% to 40%.The second layer that about 20% to 60% silicon ratio makes the high strain of good growth, silicon layer for example, and about 20% to 50% silicon ratio highlyer should change favourablely for obtaining in such as the second layer of silicon layer, and about 20% to 40% silicon ratio is the most favourable scope that obtains very high strain in such as the second layer of silicon layer.
In another advantageous embodiment of the present invention, the first crystallization epitaxial loayer and/or the second crystallization epitaxial loayer comprise carbon.Be preferably the carbon of low content, for example be lower than a few percent, even be lower than 1% carbon, cause in the ground floor and/or the second layer, having highly doped thing stability and good emergent property.
Description of drawings
Below with reference to description of drawings the preferred embodiments of the present invention, accompanying drawing comprises:
Fig. 1 is illustrated in the schematic diagram according to the Semiconductor substrate of the first step use of the method for first embodiment of the invention;
Fig. 2 illustrates the schematic diagram of the first step of first embodiment of the invention;
Fig. 3 illustrates the schematic diagram of acquisition according to second step of the first embodiment of the invention of the semiconductor structure of third embodiment of the invention;
Fig. 4 illustrates the schematic diagram of the implantation step that is applied to structure shown in Figure 3;
Fig. 5 illustrates the schematic diagram of the engagement step of structure shown in Figure 4;
Fig. 6 illustrates the third step according to first embodiment of the invention, the schematic diagram of the separating step of structure shown in Figure 5;
Fig. 7 illustrates the schematic diagram of utilization according to the creative semiconductor structure of the method manufacturing of first embodiment of the invention shown in Fig. 1 to 6;
Fig. 8 is illustrated in the schematic diagram according to the Semiconductor substrate of the first step use of second embodiment of the invention;
Fig. 9 illustrates the schematic diagram of the first step of second embodiment of the invention;
Figure 10 illustrates the schematic diagram according to second step of second embodiment of the invention;
Figure 11 illustrates the schematic diagram of acquisition according to the third step of the second embodiment of the invention of the semiconductor structure of fourth embodiment of the invention;
Figure 12 illustrates the schematic diagram of the implantation step that is applied to structure shown in Figure 11;
Figure 13 illustrates the schematic diagram of the engagement step that is applied to structure shown in Figure 12;
Figure 14 illustrates the schematic diagram of the 4th step of the second embodiment of the invention that is applied to structure shown in Figure 13;
Figure 15 illustrates the schematic diagram of the inventive structure that utilization makes according to the method for the second embodiment of the invention that goes out illustrated in Fig. 8 to 14; And
Figure 16 illustrates the schematic diagram that concerns between the CONCENTRATION DISTRIBUTION of semiconductor structure shown in Fig. 2 and 9 and the thickness.
Embodiment
Fig. 1 is illustrated in the schematic diagram according to the Semiconductor substrate of the first step use of the method for first embodiment of the invention.Semiconductor substrate 1 is the monocrystalline germanium wafer, and it preferably has common available size and characteristic electron.Germanium wafer or raw wafer 1 have upper surface 11 polished and cleaning.
In another embodiment of the present invention, the raw semiconductor substrate can be such as the A of GaAs wafer (III)-B (V) semiconductor wafer, and this has extension Ge layer or such as extension A (III)-B (V) semiconductor layer of GaAs layer above substrate.For example, this substrate can contain GaAs layer or the GaAs wafer that is covered by the Ge layer.
Fig. 2 illustrates the schematic diagram of the first step of first embodiment of the invention.At first step, the growth first crystallization epitaxial loayer 2 on raw semiconductor substrate 1 shown in Figure 1.The first crystallization epitaxial loayer 2 is made of the synthetic of germanium that forms the GeSi layer and silicon.On the upper surface 11 of germanium wafer 1, directly form GeSi layer 2.
In yet another embodiment of the present invention, before growth GeSi layer 2, can on upper surface 11, form the inculating crystal layer of Ge.
To be lower than 1% ratio, to GeSi layer 2 doping carbon.
Pine GeSi layer is on layer 23, and the ratio of its silicon and germanium is corresponding to the silicon of resilient coating 21 and the maximum ratio of germanium.Particularly, the defect concentration of loose GeSi layer 22 is very low, is about 10
4Cm
-2
Fig. 3 illustrates the schematic diagram of second step of first embodiment of the invention.In second step, insulator layer 3 is deposited on the ground floor 2, so that ground floor 2 becomes the intermediate layer between substrate 1 and the insulator layer 3.Insulator layer 3 is made of silicon dioxide and/or silicon nitride.In an illustrated embodiment, to be lower than 900 ℃ temperature, deposit insulator layer 3.In another example of the present invention, insulator layer 3 can be a thermal oxide.With the thickness adjusted of insulator layer to the destination layer thickness that will be transferred to the SiGe/ strained silicon layer on the basic wafer.Insulator layer 3 has upper surface 13.
Semiconductor structure shown in Figure 3 is the inventive structure according to third embodiment of the invention, and it is an intermediate product of making strained crystalline layer on insulator.
Fig. 4 illustrates the implantation step that structure shown in Figure 3 is implemented.At this implantation step, being lower than the suitable energy of about 180keV, with greater than 5 * 10
16Cm
-2Implantation dosage, structure shown in Figure 3 is injected hydrogen material (hydrogen species) 4.Hydrogen material 4 enters ground floor 2 by insulator layer 3 then by upper surface 13, thereby enters the layer 24 of ground floor 2.Layer 24 preferably corresponding between buffering GeSi layer 21 and the loose GeSi layer 22, layers 23 in the ground floor 2.Because injection process, layer 24 is weakened in advance, and forms predetermined Disengagement zone.
At the unshowned next step of above-mentioned figure, the injection last handling process that utilizes standard silicon IC to make, the surface 13 of cleaning insulator layer 3.If desired, can remove insulator layer 3, and can the fresh insulator layer of deposit.
Fig. 5 illustrates the engagement step to structure applications shown in Figure 4.In this engagement step, the basic wafer 6 by formations such as silicon, germanium, A (III)-B (V)-semiconductor, quartz, glass is carried out surface treatment, then, with it and structure shown in Figure 4, be bonded together by surface-treated insulator layer 3.Can utilize chemical Mechanical Polishing Technique, surface clean technology, oxygen plasma treatment technology and other usable surface treatment technologies, the surface treatment before engaging.Base wafer 6 can directly join on the surface 13 of insulator layer 3.According to another embodiment of the invention, basic wafer 6 can have dielectric layer on its composition surface, and this dielectric layer will be bonded together with the surface 13 of insulator layer 3.
Fig. 6 illustrates the third step according to first embodiment of the invention.Third step is the separating step that structure shown in Figure 5 is separated into two semiconductor structure parts 31 and 32. Part 31 and 32 along the predetermined separation line 24 that forms during implantation step shown in Figure 4 separately.The part 31 that is obtained is made of the basic wafer 6 that has formed insulator layer 3 on it, and part 31 above be the part 7 of GeSi layer 2.Part 7 preferably is made of loose GeSi material.
Another part 32 that separating step forms is made of the raw material germanium wafer 1 of the remainder 8 that forms GeSi layer 2 thereon.Remainder 8 preferably contains the remainder of gradual buffering GeSi layer 21 and above-mentioned loose GeSi layer 22.
In separation process shown in Figure 6, employed parameter is actually the normally used parameter of so-called Smart Cut method, for example, in WO00/24059 Smart Cut method is described, and is for reference in this content of quoting WO00/24059.For example, by structure shown in Figure 5 is heat-treated or vibration processing, can separate.
In unshowned another step, utilize cmp method, and adopt heat treatment method alternatively, the part 7 of GeSi layer 2 is carried out finishing.
Fig. 7 illustrates the schematic diagram according to the 4th step of the method for first embodiment of the invention.In the 4th step, on the surface 17 of separating part 31, the second crystallization epitaxial loayer of growing.The second layer 9 is that thickness is lower than 50nm, and carbon content is lower than 1% strained silicon layer.The strain of strained silicon layer is very high, and defect concentration is low.
Semiconductor structure shown in Figure 7 is corresponding to the inventive structure according to the final products of the method for first embodiment of the invention.This structure comprises the part 7 and the second layer 9 of basic wafer 6, insulator layer 3, GeSi layer 2, and wherein insulator layer 3 is the intermediate layers between basic wafer 6 and the part 7, and part 7 is the intermediate layers between the insulator layer 3 and the second layer 9.In another embodiment of the present invention, between each layer of structure shown in Figure 7, there is extra play respectively such as inculating crystal layer.
The strain of silicon layer 9 is to be about the strain that produces when epitaxial growth on 40% to 80% the GeSi layer is lower than the crystallizing silicon layer of 50nm thickness at its Ge content, and this strain is higher than the strain that its thickness of growing is lower than the prior art silicon layer of 50nm on its Ge content is lower than 40% GeSi layer.
Can after strained silicon 9, carry out thermal annealing to structure shown in Figure 7.
Fig. 8 to 13 illustrates the schematic diagram according to each step of the method for second embodiment of the invention.In Fig. 8 to 15, the same Ref. No. that Fig. 1 to 7 uses is used for representing part identical with Fig. 1 to 7 and parts.
Fig. 8 is illustrated in the schematic diagram according to the Semiconductor substrate 1 of the first step use of second embodiment of the invention.Semiconductor substrate 1 is the monocrystalline germanium wafer, and has upper surface 11.
Fig. 9 illustrates the schematic diagram of the first step of second embodiment of the invention.At first step, growth regulation four crystallization epitaxial loayers on the upper surface 11 of germanium wafer 1.As mentioned above, referring to figs. 1 to 7, in another embodiment, can use A (III)-B (V)-semiconductor or have extension Ge thereon or the substrate of A (III)-B (V)-semiconductor layer replaces the Ge wafer.
The first crystallization epitaxial loayer 2 is the GeSi layers that are made of gradual buffering GeSi layer 21 and loose GeSi 22.The gradual buffering GeSi layer 21 of growth on the upper surface 11 of the germanium wafer 1 that silicone content increases gradually.
Silicone content is about 0% surface 11 from percentage composition to begin to be about 20% to 60% ground floor 2 to silicone content percentage and increases.On layer 23, growth has the silicon of constant and the loose GeSi 22 of germanium ratio, and the silicon of this constant and germanium ratio are approximate corresponding to the silicon of gradual buffering GeSi layer 21 and the maximum ratio of germanium.Therefore, the Ge content of gradual resilient coating 21 is about 100% surface 11 from Ge content and is reduced to Ge content and is about 40% to 80% layer 23.To be lower than 1% carbon ratio example, to GeSi layer 2 doping carbon.Ground floor 2 has upper surface 12.
Figure 10 illustrates the schematic diagram according to second step of the method for second embodiment of the invention.In second step, its carbon content of growth is lower than 1% the second crystallization epitaxial loayer 9 on ground floor 2.The second crystallization epitaxial loayer 9 is strained silicon layers that thickness is lower than 50nm.The defect concentrations in crystals of strained silicon layer 9 is very low, and strain is high.The second layer has upper surface 19.
Figure 11 illustrates the schematic diagram according to the third step of the method for second embodiment of the invention.At third step, deposit insulator layer 3 on the surface 19 of strained silicon layer 9.Insulator layer 3 is made of silicon dioxide and/or silicon nitride.The thickness of insulator layer 3 depends on the destination layer signal of the SiGe/ strained silicon layer that must be transferred on the basic wafer.Insulator layer 3 has upper surface 13.
Figure 12 illustrates the schematic diagram of the implantation step that is applied to structure 40 shown in Figure 11.At implantation step, by upper surface 13 and insulator layer 3, inject hydrogen material 4, the layer up to approaching above-mentioned surperficial 12 has so just formed the interface between GeSi layer 2 and the strained silicon layer 9.Because inject,, be scheduled to the Disengagement zone thereby on interface 12, form so weakened in advance in interface 12.
Being less than about the suitable energy of 180keV, with greater than 5 * 10
14Cm
-2The hydrogen of dosage injects.
After injecting, the injection last handling process that utilizes standard silicon IC to make, clean surface 13.If desired, can remove insulator layer 3, and can the new fresh insulator layer of deposit.These steps are not shown.
Then, to shown in Figure 12, with carry out surface treatment by the parallel structure of the basic wafer of formations such as silicon, germanium, A (III)-B (V)-semiconductor, quartz, glass.Can utilize chemical Mechanical Polishing Technique, surface clean technology, oxygen plasma treatment technology or similar approach, carry out surface treatment.
Figure 13 illustrates the engagement step that structure shown in Figure 12 and basic wafer 6 are bonded together.Base wafer 6 is bonded on the surface 13 of insulator layer 3.According to another embodiment of the invention, basic wafer 6 can comprise the insulator layer that engages with the surface 13 of insulator layer 3 on its composition surface.
Figure 14 illustrates the 4th step according to the method for second embodiment of the invention.In the 4th step, structure shown in Figure 13 is separated into two parts 41 and 42.Carry out this separating step with the separation method that is similar to Smart Cut method, in the separation method of Smart Cut method, for example, utilize heat treatment or vibration processing, this structure is separated into two parts along predetermined separation line.
In Figure 14, the defiber between the part 41 and 42 is corresponding to the predetermined Disengagement zone on the interface 12 between the ground floor 2 and second strained silicon layer 9.First separating part 41 is made of the basic wafer 6 that forms insulator layer 3 thereon and have a strained silicon layer 9 on insulator layer 3, so insulator layer 3 is the intermediate layers between basic wafer 6 and the strained layer 9.In another embodiment of the present invention, between basic wafer 6 and the insulator layer 3 and/or between insulator layer 3 and strained layer 9, can there be extra play.Separating part 42 is made of the raw material germanium wafer 1 that forms GeSi layer 2 thereon.
Figure 15 illustrate corresponding to separating part 41 shown in Figure 14, according to the schematic diagram of the final products of the method for second embodiment of the invention.Can carry out thermal annealing to structure 41, and can remove the GeSi residue on the strained silicon layer 9.
The strain of the strained silicon layer 9 of structure 41 shown in Figure 15 is very high, and defect concentration is very low, is lower than 10
4Cm
-2The strain of silicon layer 9 is to be about the strain that produces when epitaxial growth thickness on 40% to 70% the GeSi layer is lower than the crystallizing silicon layer of 50nm at its Ge content, and this strain is higher than the strain that the thickness of growing is lower than the prior art silicon layer of 50nm on its Ge content is lower than 40% GeSi layer.
Figure 16 illustrates the schematic diagram that concerns between the CONCENTRATION DISTRIBUTION of semiconductor structure shown in Fig. 2 and 9 and the thickness.Ref. No. shown in Figure 16, identical with 9 Ref. No.s of using with Fig. 2 represent with Fig. 2 and 9 in identical parts.
In Figure 16, the Ge content of semiconductor structure shown in solid line 51 presentation graphs 2 and 9, in germanium substrate 1, it is about 100%.The silicone content of semiconductor structure shown in chain-dotted line 52 presentation graphs 2 and 9, in germanium substrate 1, it is about 0%.In gradual buffering GeSi layer 21, silicone content 52 is increased to about 30% from 0%, and in resilient coating 21, Ge content 51 is reduced to about 70% value.In Figure 16, the increase of shown silicon 52 and the reduction of germanium 51 all are continuous.In resilient coating 21, can adopt gradual change or the silicon that progressively changes and/Ge content, and do not adopt continually varying silicon and/Ge content.In addition, the zone that in resilient coating 21, can exist one or more germanium and/or silicone content not to change.
The germanium of the loose GeSi layer 22 on the resilient coating 21 is approaching constant with the ratio of silicon, about 30% to 60% silicon, about 40% to 70% germanium.Pine layer 22 is dislocation-free almost.The defect concentrations in crystals of pine layer 22 is lower than 10
4Cm
-2
Technology is carried out a layer transfer printing although above preferred embodiment adopts Smart Cut, but also can adopt any other layer transfer technique, for example other embrittlement technology (fragilization technique) of Bond-and-Etchback technology or employing porous layer forming process.
Claims (23)
1. method of on insulator, making strained crystalline layer, this method comprises:
Setting comprises germanium and/or A (III)-B (V)-semi-conductive raw semiconductor substrate (1);
At first step, at least one first crystallization epitaxial loayer (2) is set;
In second step, at least one insulator layer (3) is set;
Wherein the first crystallization epitaxial loayer (2) is arranged between raw semiconductor substrate (1) and the insulator layer (3), the first crystallization epitaxial loayer (2) comprises resilient coating (21), during first step, the germanium of resilient coating (21) and/or A (III)-B (V)-semi-conductive content is reduced to 50% to 80% ratio with the direction from raw semiconductor substrate (1) to insulator layer (3);
At third step, the first crystallization epitaxial loayer (2) is separated into two parts; And
In the 4th step, on the part (7) of insulator layer (3) one sides of the first crystallization epitaxial loayer (2), at least one second crystallization epitaxial loayer (9) is set.
2. method according to claim 1,
It is characterized in that raw semiconductor substrate (1) is monocrystalline germanium wafer, monocrystalline A (III)-B (V)-semiconductor wafer, extension germanium layer or extension A (III)-B (V)-semiconductor layer.
3. any one the described method in requiring according to aforesaid right,
It is characterized in that
At first step, the silicone content of resilient coating (21) is increased to 20% to 50% ratio.
4. method according to claim 1,
It is characterized in that
The second crystallization epitaxial loayer (9) grows into the thickness that is lower than 50nm.
5. method according to claim 1,
It is characterized in that
The first crystallization epitaxial loayer (2) and/or the second crystallization epitaxial loayer (9) comprise carbon.
6. semiconductor structure that is used on insulator making strained crystalline layer, this semiconductor structure comprises:
By the raw semiconductor substrate (1) that comprises that germanium and/or A (III)-B (V)-semi-conductive first material constitutes;
At least one crystallization epitaxial loayer (2); And
At least one insulator layer (3);
Wherein this at least one crystallization epitaxial loayer (2) is the intermediate layer between raw semiconductor substrate (1) and the insulator layer (3), and this at least one crystallization epitaxial loayer (2) comprises resilient coating (21), this resilient coating (21) is to comprise germanium and/or A (III)-B (V)-semi-conductive synthetic, and germanium and/or A (III)-B (V)-semi-conductive content is reduced to 50% to 80% ratio with the direction from raw semiconductor substrate (1) to insulator layer (3).
7. structure according to claim 6,
It is characterized in that
Raw semiconductor substrate (1) is monocrystalline germanium wafer, monocrystalline A (III)-B (V)-semiconductor wafer, extension germanium layer or extension A (III)-B (V)-semiconductor layer.
8. according to claim 6 or 7 described structures,
It is characterized in that
The silicone content of crystallization epitaxial loayer (2) increases with the direction from raw semiconductor substrate (1) to insulator layer (3).
9. structure according to claim 8,
It is characterized in that
Silicone content is increased to 20% to 50% ratio.
10. semiconductor structure, this semiconductor structure comprises:
Semiconductor-based substrate (6);
At least one insulator layer (3); And
At least one first crystallization epitaxial loayer (2);
At least one strain second crystallization epitaxial loayer (9),
Wherein the first crystallization epitaxial loayer (2) is the intermediate layer between insulator layer (3) and the strain second crystallization epitaxial loayer (9), insulator layer (3) is the intermediate layer between the semiconductor-based substrate (6) and the first crystallization epitaxial loayer (2), and the first crystallization epitaxial loayer (2) comprises resilient coating (21), this resilient coating (21) is to comprise germanium and/or A (III)-B (V)-semi-conductive synthetic, and germanium and/or A (III)-B (V)-semi-conductive content is reduced to 50% to 80% ratio with the direction from the strain second crystallization epitaxial loayer (9) to insulator layer (3).
11. structure according to claim 10,
It is characterized in that
The silicone content of resilient coating (21) increases with the direction from the strain second crystallization epitaxial loayer (9) to insulator layer (3).
12. structure according to claim 11,
It is characterized in that
Silicone content is increased to 20% to 50% ratio.
13. structure according to claim 10,
It is characterized in that
The thickness of the strain second crystallization epitaxial loayer (9) is lower than 50nm.
14. structure according to claim 10,
It is characterized in that
The first crystallization epitaxial loayer (2) and/or the strain second crystallization epitaxial loayer (9) comprise carbon.
15. a method of making strained crystalline layer on insulator, this method comprises:
Setting comprises germanium and/or A (III)-B (V)-semi-conductive raw semiconductor substrate (1);
At first step, at least one first crystallization epitaxial loayer (2) is set;
In second step, at least one second crystallization epitaxial loayer (9) is set;
Wherein the first crystallization epitaxial loayer (2) is arranged between the raw semiconductor substrate (1) and the second crystallization epitaxial loayer (9), the first crystallization epitaxial loayer (2) comprises resilient coating (21), during first step, the direction of the germanium of resilient coating (21) and/or A (III)-B (V)-semi-conductive content from raw semiconductor substrate (1) to the second crystallization epitaxial loayer (9) is reduced to 50% to 80% ratio;
At third step, at least one insulator layer (3) is set;
Wherein the second crystallization epitaxial loayer (9) is arranged between the first crystallization epitaxial loayer (2) and the insulator layer (3); And
In the 4th step, between the first crystallization epitaxial loayer (2) and the second crystallization epitaxial loayer (9), separate.
16. method according to claim 15,
It is characterized in that
Raw semiconductor substrate (1) is monocrystalline germanium wafer, monocrystalline A (III)-B (V)-semiconductor wafer, extension germanium layer or extension A (III)-B (V)-semiconductor layer.
17. method according to claim 15,
It is characterized in that
The second crystallization epitaxial loayer (9) grows into the thickness that is lower than 50nm.
18. according to any one the described method in the claim 15 to 17,
It is characterized in that
At first step, the silicone content of resilient coating (21) is increased to 20% to 50% ratio.
19. a semiconductor structure that is used for making strained crystalline layer on insulator, this semiconductor structure comprises:
By the raw semiconductor substrate (1) that comprises that germanium and/or A (III)-B (V)-semi-conductive first material constitutes;
At least one first crystallization epitaxial loayer (2);
At least one second crystallization epitaxial loayer (9); And
At least one insulator layer (3)
Wherein the first crystallization epitaxial loayer (2) is the intermediate layer between the raw semiconductor substrate (1) and the second crystallization epitaxial loayer (9), the second crystallization epitaxial loayer (9) is the intermediate layer between the first crystallization epitaxial loayer (2) and the insulator layer (3), the first crystallization epitaxial loayer (2) comprises resilient coating (21), this resilient coating (21) is to comprise germanium and/or A (III)-B (V)-semi-conductive synthetic, and germanium and/or A (III)-B (V)-semi-conductive content is reduced to 50% to 80% ratio with the direction from raw semiconductor substrate (1) to the second crystallization epitaxial loayer (9).
20. structure according to claim 19,
It is characterized in that
Raw semiconductor substrate (1) is monocrystalline germanium wafer, monocrystalline A (III)-B (V)-semiconductor wafer, extension germanium layer or extension A (III)-B (V)-semiconductor layer.
21. according to claim 19 or 20 described structures,
It is characterized in that
The silicone content of resilient coating (21) increases with the direction from raw semiconductor substrate (1) to insulator layer (3).
22. structure according to claim 21,
It is characterized in that
Silicone content is increased to 20% to 50% ratio.
23. structure according to claim 19,
It is characterized in that
The first crystallization epitaxial loayer (2) and/or the second crystallization epitaxial loayer (9) comprise carbon.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| EP03290231A EP1443550A1 (en) | 2003-01-29 | 2003-01-29 | A method for fabricating a strained crystalline layer on an insulator, a semiconductor structure therefor, and a fabricated semiconductor structure |
| EP03290231.4 | 2003-01-29 | ||
| US48599703P | 2003-07-09 | 2003-07-09 | |
| US60/485,997 | 2003-07-09 |
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| Publication Number | Publication Date |
|---|---|
| CN1538499A CN1538499A (en) | 2004-10-20 |
| CN1282990C true CN1282990C (en) | 2006-11-01 |
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| Application Number | Title | Priority Date | Filing Date |
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| CNB2004100033711A Expired - Lifetime CN1282990C (en) | 2003-01-29 | 2004-01-29 | Method for fabricating strained crystalline layer on insulator, semiconductor structure and obtained semiconductor structure |
Country Status (4)
| Country | Link |
|---|---|
| JP (1) | JP4853990B2 (en) |
| KR (1) | KR100576684B1 (en) |
| CN (1) | CN1282990C (en) |
| SG (1) | SG115609A1 (en) |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE10310740A1 (en) * | 2003-03-10 | 2004-09-30 | Forschungszentrum Jülich GmbH | Method for producing a stress-relaxed layer structure on a non-lattice-matched substrate, and use of such a layer system in electronic and / or optoelectronic components |
| FR2880988B1 (en) * | 2005-01-19 | 2007-03-30 | Soitec Silicon On Insulator | TREATMENT OF A LAYER IN SI1-yGEy TAKEN |
| FR2889887B1 (en) * | 2005-08-16 | 2007-11-09 | Commissariat Energie Atomique | METHOD FOR DEFERING A THIN LAYER ON A SUPPORT |
| FR2891281B1 (en) * | 2005-09-28 | 2007-12-28 | Commissariat Energie Atomique | METHOD FOR MANUFACTURING A THIN FILM ELEMENT |
| US7608526B2 (en) * | 2006-07-24 | 2009-10-27 | Asm America, Inc. | Strained layers within semiconductor buffer structures |
| GB2467935B (en) * | 2009-02-19 | 2013-10-30 | Iqe Silicon Compounds Ltd | Formation of thin layers of GaAs and germanium materials |
| FR2972567B1 (en) | 2011-03-09 | 2013-03-22 | Soitec Silicon On Insulator | METHOD OF FORMING A STRUCTURE OF GE ON III / V ON INSULATION |
| CN103165511B (en) * | 2011-12-14 | 2015-07-22 | 中国科学院上海微系统与信息技术研究所 | Method for manufacturing germanium on insulator (GOI) |
| EP3573094B1 (en) * | 2014-11-18 | 2023-01-04 | GlobalWafers Co., Ltd. | High resistivity semiconductor-on-insulator wafer and a method of manufacturing |
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2004
- 2004-01-27 JP JP2004018825A patent/JP4853990B2/en not_active Expired - Lifetime
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| KR20040070018A (en) | 2004-08-06 |
| KR100576684B1 (en) | 2006-05-04 |
| JP4853990B2 (en) | 2012-01-11 |
| SG115609A1 (en) | 2005-10-28 |
| JP2004343052A (en) | 2004-12-02 |
| CN1538499A (en) | 2004-10-20 |
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