CN1282312C - Method and system for decoding low-density parity check code - Google Patents
Method and system for decoding low-density parity check code Download PDFInfo
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Abstract
An approach is provided for transmitting messages using low density parity check (LDPC) codes. Input messages are encoded according to a structured parity check matrix that imposes restrictions on a sub-matrix of the parity check matrix to generate LDPC codes. The LDPC codes are transmitted over a radio communication system (100) (e.g., satellite network), wherein a receiver (300) communicating over the radio communication system (100) is configured to iteratively decode the received LDPC codes according to a signal constellation associated with the LDPC codes. The receiver (300) is configured to iteratively regenerating signal constellation bit metrics after one or more decoding iterations.
Description
Technical field
The present invention relates to communication system, more particularly relate to system through coding.
Background technology
The communication system utilization is encoded and is guaranteed reliable communication on the noisy communications channel.These communication channels provide fixing message capacity, and this capacity can represent that it has determined a theoretical upper limit (being usually said shannon limit) with the every sign bit number under the fixing signal to noise ratio (snr).As a result, various encoding schemes are target with the speed that realizes approaching shannon limit just.The coding that has a class to approach shannon limit is exactly low-density checksum (LDPC) sign indicating number.
Because the LDPC sign indicating number has many shortcomings, therefore formerly be not widely adopted.A shortcoming is that the LDPC coding techniques is very complicated.Utilize generator matrix to carry out the LDPC coding and need to store a huge non-sparse matrix.In addition, the LDPC sign indicating number needs in store always large matrix piece; Therefore, even the parity matrix of LDPC sign indicating number is sparse, it also is debatable storing these matrixes.
Angle from realizing also can run into many challenges.For instance, memory is exactly the major reason why the LDPC sign indicating number is not widely adopted in actual applications.The challenge of another key is how to realize the connection network between a plurality of processors (node) in the decoder in the enforcement of LDPC sign indicating number.In addition, the computing load in the decode procedure, particularly check-node running also can have problems.
Therefore, need the LDPC communication system to adopt simple encoding and decoding step.Also need to use expeditiously the LDPC sign indicating number to support high data rate, do not introduce higher complexity simultaneously again.Also need to improve the performance of LDPC encoder and decoder.Also need to reduce to realize the storage requirement of LDPC coding.Also need a kind of scheme to simplify communication between the processing node in the LDPC decoder in addition.
Summary of the invention
The present invention is devoted to solve such or such demand, and a kind of method that is used for the decoding of structured low density parity check (LDPC) sign indicating number wherein is provided.Part by the restriction parity-check matrix is for following triangle battle array and/or satisfy the structure that other conditions are come regulation LDPC sign indicating number, thereby makes the communication between the decoder processes node become very simple.In addition, this method can make full use of the unequal error protection ability of LDPC sign indicating number on transmitted bit, provides extra error protection with the bit that is more vulnerable to influence to high-order modulation constellation figure (such as 8-PSK (phase shift keying)).Decode procedure adds iteration regenerated signal planisphere bit metric in the LDPC decoder after each decoder iteration or a plurality of decoder iteration.Above-mentioned arrangement provides a kind of high efficiency operation method of decoding LDPC sign indicating number.
According to an aspect of the embodiment of the invention, a kind of method of low-density checksum (LDPC) sign indicating number that is used to decode is wherein disclosed.This method comprises and receives a priori probability information that depends on distance vector information, described distance vector information relate to the symbolic point of the signal constellation which relevant with the LDPC sign indicating number and receive distance between the noise symbol point arranged.This method also comprises posterior probability information that depends on priori probability information of transmission.This method comprises according to prior probability and posterior probability information judges whether the parity check equation relevant with the LDPC sign indicating number satisfies.In addition, this method also comprises optionally according to determination step regenerated signal constellation bit metric.In addition, this method comprises according to regenerated signal constellation bit metric output decoder information.
A kind of system of low-density checksum (LDPC) sign indicating number that is used to decode is wherein disclosed according to the embodiment of the invention on the other hand.This system comprises and is used to receive a device that depends on the priori probability information of distance vector information, described distance vector information relate to the symbolic point of the signal constellation which relevant with the LDPC sign indicating number and receive distance between the noise symbol point arranged.This system also comprises and is used to send a device that depends on the posterior probability information of priori probability information.In addition, this system also comprises according to prior probability and posterior probability information and judges the device that the parity check equation relevant with the LDPC sign indicating number be whether satisfied.This system comprises and being used for optionally according to the device of judging regenerated signal constellation bit metric.In addition, this system also comprises the device that is used to export based on the decoded information of regenerated signal constellation bit metric.
A kind of receiver of low-density checksum (LDPC) sign indicating number that is used to decode is wherein disclosed according to the embodiment of the invention on the other hand.This receiver comprises a bit metric maker, this maker is provided to generate a priori probability information according to distance vector information, described distance vector information relate to the symbolic point of the signal constellation which relevant with the LDPC sign indicating number and receive distance between the noise symbol point arranged.This receiver also comprises a decoder, this decoder is provided to export a posterior probability information based on priori probability information, described priori probability information receives from the bit metric maker, and wherein decoder also is provided to judge according to prior probability and posterior probability information whether the parity check equation relevant with the LDPC sign indicating number satisfies.If parity check equation does not satisfy, decoder is just exported the decoded information based on regenerated signal constellation bit metric so.
According to the embodiment of the invention on the other hand, the method that the information of low-density checksum (LDPC) sign indicating number is used in a kind of transmission is wherein disclosed.This method comprises according to a structured odd-even check matrix encodes to input information, and described structured odd-even check matrix adds that to the submatrix of parity matrix restrictive condition is to generate the LDPC sign indicating number.This method comprises that also wherein a receiver that communicates by wireless communication system is provided to the LDPC sign indicating number that the basis signal constellation which iterative decoding relevant with the LDPC sign indicating number receives by a wireless communication system transmission LDPC sign indicating number.This receiver is set at one or more decoding iteration iteration regenerated signal planisphere bit metric afterwards.
By illustrating multiple specific embodiment and execution mode, other aspects of the present invention, characteristics and advantage all have embodiment clearly in detailed description subsequently, comprising in order to realize best mode of the present invention.The present invention also has other different embodiment, and its some details can be improved from different aspects, and all these does not depart from design philosophy of the present invention and scope.Therefore, accompanying drawing and explanation should be regarded as exemplary, rather than restrictive.
Description of drawings
The present invention illustrates but not for the purpose that limits illustrates, similar Reference numeral is represented similar elements in each figure of accompanying drawing, wherein:
Fig. 1 shows the schematic diagram of communication system according to an embodiment of the invention, and this communication system is set up uses low-density checksum (LDPC) sign indicating number;
Fig. 2 shows the schematic diagram of an exemplary transmitter in the system shown in Figure 1;
Fig. 3 shows the schematic diagram of a typical receiver in the system shown in Figure 1;
Fig. 4 shows the schematic diagram of sparse parity matrix according to an embodiment of the invention;
Fig. 5 shows the bipartite graph of the LDPC sign indicating number of matrix shown in Figure 4;
Fig. 6 shows the schematic diagram of the submatrix of sparse parity matrix according to an embodiment of the invention, and wherein said submatrix comprises the parity values that is limited in down in the Delta Region;
Fig. 7 shows a curve chart, the figure illustrates the coding of the not limited parity matrix of use (H matrix) and uses performance comparison between the coding with limited H matrix of submatrix as shown in Figure 6;
Fig. 8 A and 8B show non-Gray code 8-PSK modulation scheme and Gray code 8-PSK modulation scheme respectively, and they all are used in the system shown in Figure 1;
Fig. 9 shows a curve chart, the figure illustrates the coding that indicates with Gray code and with the performance comparison between the coding of non-Gray code sign;
Figure 10 shows the workflow diagram of the LDPC decoder that uses non-Gray code mapping according to an embodiment of the invention;
Figure 11 shows the workflow diagram of the LDPC decoder that uses the Gray code mapping according to an embodiment of the invention, and this decoder as shown in Figure 3;
Figure 12 A-12C shows according to an embodiment of the invention in the decode procedure, interactional schematic diagram between check-node and the bit node;
Figure 13 A and 13B show the flow chart of steps that is used for the information of sending between calculation check node and the bit node according to various embodiments of the invention, the corresponding respectively computational process of front and back to method and parallel method of having used of two figure;
Figure 14 A-14C shows several curve charts, and these curve charts have shown the simulation result that generates the LDPC sign indicating number according to various embodiments of the present invention;
Figure 15 A and 15B show the top and the bottom margin of memory according to an embodiment of the invention respectively, and this memory is organized supports the structuring access to realize the randomness in the LDPC coding; And
Figure 16 shows the schematic diagram according to a computer system of the embodiment of the invention, and this system can carry out the encoding and decoding processing procedure of LDPC sign indicating number.
Embodiment
This paper has described a kind of system, method and software that is used for high efficiency decode structures low-density checksum (LDPC) sign indicating number.In the following description, for for the purpose of illustrating and elaboration many details, understand completely to provide for the present invention comprehensively.But to those skilled in the art, do not need these detailed details or the form by equivalence just can realize the present invention.In other example, show some well-known structure and equipment with the block diagram form, unnecessary fuzzyly obscure to avoid the present invention produced.
Fig. 1 shows the schematic diagram of communication system according to an embodiment of the invention, and this communication system is set up uses low-density checksum (LDPC) sign indicating number.A digital communication system 100 comprises a transmitter 101, and it generates signal waveform and sends a receiver 105 to by communication channel 103.In this discrete communication system 100, transmitter 101 has an information source, and it produces a discrete set of possibility information; Each possible information has the signal waveform of a correspondence.These signal waveforms are decayed by communication channel 103 or change with other forms.In order to resist noisy communication channel 103, will use the LDPC sign indicating number.
The LDPC sign indicating number that transmitter 101 generates makes realization of High Speed become possibility, and don't can cause any performance loss.Rely on modulation scheme (such as 8-PSK) to avoid the sub-fraction check-node is distributed to the bit node that those have been subjected to the channel error influence easily from these structured LDPC codes of transmitter 101 outputs.
But this LDPC sign indicating number has a kind of decoding algorithm (unlike the turbo sign indicating number) of parallelization, and this algorithm only relates to some shirtsleeve operations, searches such as addition, comparison and table.In addition, the LDPC sign indicating number of careful design can not demonstrate the sign of any error lowest limit.
According to one embodiment of present invention, transmitter 101 utilizes a kind of simple relatively coding techniques generation to come to communicate with receiver 105 based on the LDPC sign indicating number of parity matrix (auxiliary efficient memory access during decoding).As long as block length is enough big, transmitter 101 employed LDPC sign indicating numbers can surpass cascade turbo+RS (Reed-Solomon) sign indicating number.
Fig. 2 shows the schematic diagram of an exemplary transmitter in the system shown in Figure 1.Transmitter 200 is equipped with a LDPC encoder 203, and it can receive from the input of information source 201 and export the more encoding stream of highly redundant degree, and this encoding stream is fit to the correction process that receiver 105 is done.Information source 201 generates k signal by a discrete symbols collection X.The LDPC sign indicating number is determined by parity matrix.On the other hand, coding LDPC sign indicating number need be specified generator matrix usually.Although can utilize Gaussian elimination method to obtain generator matrix by parity matrix, the matrix that obtains no longer is sparse, and store a big generator matrix may be very complicated.
A kind of simple coding techniques of encoder 203 usefulness is generated signal and is sent into modulator 205 by glossary of symbols Y, and described coding techniques utilizes parity matrix by parity matrix being applied certain structure.Specifically, certain part by restriction matrix is that triangular form comes parity matrix is applied restriction exactly.Among the structure of this parity matrix Fig. 6 below explanation is more fully arranged.This restriction can cause negligible performance loss, and has therefore formed a kind of attractive compromise proposal.
Modulator 205 coded message of own coding device 203 in the future is mapped as signal waveform, and this signal waveform is fed to a transmitting antenna 207 again, and transmitting antenna is launched these waveforms by communication channel 103.Thereby coded message is just modulated and send to a transmitting antenna 207.The transmission signal of transmitting antenna 207 propagates on the receiver again, and is as described below.
Fig. 3 shows the schematic diagram of a typical receiver in the system shown in Figure 1.At receiving terminal, a receiver 300 comprises a demodulator 301, and it carries out demodulation to the received signal from transmitter 200.These signals are that reception antenna 303 receives to supply to separate to call.After demodulation, received signal is forwarded to demodulator 305, and demodulator 305 is attempted rebuilding original source information by generating information X ' with 307 collaborative works of bit metric maker.For the mapping of non-Gray code, bit metric maker 307 in decode procedure with decoder 305 (repeatedly) exchange probabilistic information back and forth, this has a detailed description in Figure 10.In addition, if used Gray code mapping (according to one embodiment of present invention), the once transmission of bit metric maker is just enough, may can only produce limited performance raising because further carry out the bit metric generation after each LDPC decoder iteration; This method has more detailed description in Figure 11.Be appreciated that the advantage that the present invention brings, analyzing the LDPC sign indicating number and be what how to produce is highly significant, and this has illustrated in Fig. 4.
Fig. 4 shows the schematic diagram of sparse parity matrix according to an embodiment of the invention.The LDPC sign indicating number is long linear block codes, and it has sparse parity check matrix H
(n-k) * nUsually the scope of block length n can not wait by bit from thousands of to tens thousand of.For instance, illustrated among Fig. 4 and be used for the parity matrix that length n=8 speed is 1/2 LDPC sign indicating number.Same sign indicating number also can be represented equivalently with the bipartite graph shown in Fig. 5.
Fig. 5 shows the bipartite graph of the LDPC sign indicating number of matrix shown in Figure 4.Parity check equation represents, for each check-node, all adjacent bit nodes and (on GF (Galois territory) (2)) equal zero.As seen from the figure, bit node has occupied the left side of figure, and relevant with one or more check-nodes according to predetermined relation.For instance, for check-node m1, about the expression formula n of bit node
1+ n
4+ n
5+ n
8=0 sets up.
Get back in the receiver 300, LDPC decoder 305 is taken as an information passing decoder, and decoder 305 need draw the value of bit node thus.In order to finish this task, bit node and check-node will communicate to each other repeatedly.The characteristic of this communication illustrates below.
From the check-node to the bit node, each check-node provides an estimation about that bit node value (" judgement ") to an adjacent bit node, and this estimation is based on from the information of other adjacent bit nodes.For instance, if n in the above example
4, n
5And n
8And for m
1" seeming " is 0, so m
1Will be to n
1The value of pointing out it is 0 (because n
1+ n
4+ n
5+ n
8=0); Otherwise m
1Will be to n
1The value of pointing out it is 1.In addition, for soft-decision decoding, also need to add reliability measurement.
From the bit node to the check-node, each bit node sends an estimation about it self value to an adjacent check-node, and this estimation is based on from the feedback information of other adjacent check-nodes.In the above example, n
1Have only two adjacent check-node m
1And m
3If m
3Give n
1Feedback information indication n
1Value be likely 0, n so
1To notify m
1To n
1Self value be estimated as 0.For bit node the situation of adjacent check-node more than two is arranged, bit node will carry out majority voting (soft-decision) to the feedback information from other adjacent check-nodes before the check-node report court verdict that communicates with.Repeat said process up to all bit nodes all be considered to correct till (that is to say that all parity check equations all are satisfied) or till reaching predetermined maximum iteration time and declaration decoding failure thus.
Fig. 6 shows the schematic diagram of the submatrix of sparse parity matrix according to an embodiment of the invention, and wherein said submatrix comprises the parity values that is limited in down in the Delta Region.As previously described, encoder 203 (Fig. 2) can use simple coding techniques by the value of Delta Region under the restriction parity matrix.According to one embodiment of present invention, the liquid container that parity matrix applied there is following form:
H
(n-k)×n＝[A
(n-k)×kB
(n+k)×(n+k)]
Wherein B is following triangle battle array.
Use Hc
T=0 with any block of information i=(i
0, i
1... i
K-1) be encoded into a code word
C=(i
0, i
1..., i
K-1, p
0, p
1P
N-k-1), and try to achieve check digit with the recursion mode; For instance,
a
00i
0+ a
01i
1+ ... + a
0, k-1i
K-1+ p
0=0 solves p
0,
a
10i
0+ a
11i
1+ ... + a
1, k-1i
K-1+ b
10p
0+ p
1=0 solves p
1,
Solve p in the same way
2, p
3... p
N-k-1
Fig. 7 shows a curve chart, the figure illustrates the coding of the not limited parity matrix of use (H matrix) and uses performance comparison between the coding of the limited H matrix shown in Fig. 6.This curve chart shows two kinds of performance comparison between the LDPC coding: a kind of coding used general parity matrix, and another kind of coding uses the parity matrix that is restricted to down the triangle battle array to simplify coding.The modulation scheme that is used for emulation is 8-PSK.Performance loss is in 0.1dB.Therefore, use the caused performance loss of restriction of triangle H matrix down to ignore, and the benefit highly significant that from the simplification of coding techniques, obtains.Thereby any being expert at/be listed as the matrix that is equivalent to down triangle under the exchange or goes up triangular form can be used to identical purpose.
Fig. 8 A and 8B show non-Gray code 8-PSK modulation scheme and Gray code 8-PSK modulation scheme respectively, and they can be used in the system shown in Figure 1.Non-Gray code 8-PSK scheme shown in Fig. 8 A can be used in the receiver shown in Figure 3, so that the system of a low-down frame erasure rate of needs (FER) to be provided.This requirement also can connect same outer sign indicating number by using the Gray code 8-PSK scheme shown in Fig. 8 B, and as Bose, Chaudhuri and Hocquenghem (BCH) sign indicating number, writing brush bright (Hamming) sign indicating number, or Reed-Solomon (RS) sign indicating number satisfy jointly.
In suc scheme, need be between LDPC decoder 305 (Fig. 3) and bit metric maker 307 not back and forth, bit metric maker 307 may use the 8-PSK modulation.Under the situation of sign indicating number, the LDPC decoder 305 that uses Gray code to indicate can not demonstrate an early stage mistake lowest limit, as shown in Figure 9 outside having.
Fig. 9 shows a curve chart, the figure illustrates among Fig. 8 A and the 8B coding that indicates with Gray code and with the performance comparison between the coding of non-Gray code sign.The mistake lowest limit comes from such a case: suppose that LDPC decoder 305 has sent correct feedback information, indicating the 8-PSK bit metric of regenerating with non-Gray code so can be more accurate, and this is farther because have two 8-PSK intersymbol distances of two known bits in non-Gray code indicates.This point can be considered as being operated under the higher signal to noise ratio (snr) equivalently.Therefore, even use the mistake asymptote of the identical LDPC sign indicating number of Gray code or non-Gray code sign to have identical slope (promptly parallel to each other), that curve that uses non-Gray code to indicate also can pass through lower FER point on the SNR arbitrarily.
On the other hand, for the system that does not need very low FER, need not carry out any reciprocal Gray code sign between LDPC decoder 305 and 8-PSK bit metric maker 307 may be more suitable, and this is because regeneration 8-PSK bit metric can cause extra complexity before each LDPC decoder iteration.In addition, when using Gray code to indicate, regeneration 8-PSK bit metric can only produce very faint performance improvement before each LDPC decoder iteration.As mentioned before, if outer sign indicating number is provided, need not reciprocal Gray code so and indicate the system that only need just can be used to very low FER.
The characteristic of LDPC sign indicating number is also depended in selection between Gray code sign and non-Gray code sign.Usually, bit or check-node exponent number are high more, it is just good more to use Gray code to indicate, because for higher node exponent number, it is more that the initial feedback that mails to 8-PSK (or similarly more high order modulation) bit metric maker 307 from LDPC decoder 305 can indicate variation with non-Gray code.
8-PSK (or similarly more high-order) modulation is together used with a binary decoder, but we recognize that three (or more a plurality of) in the symbol are not " equal level of noise " when bit is received.For example, when indicating with Gray code 8-PSK, the 3rd bit in symbol is bigger with regard to being considered to contain noisiness for decoder than two other bit.Therefore, can in having represented the 8-PSK symbol, not specify a spot of border by those bit nodes of the 3rd bit of " noise is bigger " in the design of LDPC sign indicating number, thereby guarantee that those bits can not worsened twice.
Figure 10 shows the workflow diagram of the LDPC decoder that uses non-Gray code mapping according to an embodiment of the invention.Under this method, LDPC decoder and bit metric maker carry out interative computation in succession.Used the 8-PSK modulation in this example; But same principle also is applicable to other more modulation schemes of high-order.In this case, suppose demodulator 301 to distance vector d of bit metric maker 307 output, this vector has been represented the distance of making an uproar between symbolic point and the 8-PSK symbolic point that has that receives, each element of this vector as shown in the formula:
8-PSK bit metric maker 307 communicates with exchange priori probability information and posterior probability information with LDPC decoder 305, represents with u and a respectively.That is to say that vectorial u and a represent the prior probability and the posterior probability of coded-bit likelihood ratio logarithm respectively.
8-PSK bit metric maker 307 the following is and respectively organizes three bits generation priori likelihood ratios.At first obtain the external information of coded-bit:
e
j＝a
j-u
j j＝0，1，2
Then determine 8-PSK symbol probability p
i, i=0,1 ... 7.
*y
j=-f (0, e
j) j=0,1,2 wherein f (a, b)=max (a, b)+LUT
f(a, b),
And LUT
f(a, b)=ln (1+e
-| a-b|)
*x
j＝y
j+e
j j＝0，1，2
*p
0＝x
0+x
1+x
2 p
4＝y
0+x
1+x
2
p
1＝x
0+x
1+y
2 p
5＝y
0+x
1+y
2
p
2＝x
0+y
1+x
2 p
6＝y
0+y
1+x
2
p
3＝x
0+y
1+y
2 p
7＝y
0+y
1+y
2
Then, bit metric maker 307 is determined the input of the priori likelihood ratio logarithm of coded-bit as LDPC decoder 305, and is as follows:
u
0＝f(d
0+p
0，d
1+p
1，d
2+p
2，d
3+p
3)-f(d
4+p
4，d
5+p
5，d
6+p
6，d
7+p
7)-e
0
u
1＝f(d
0+p
0，d
1+p
1，d
4+p
4，d
5+p
5)-f(d
2+p
2，d
3+p
3，d
6+p
6，d
7+p
7)-e
1
u
2＝f(d
0+p
0，d
2+p
2，d
4+p
4，d
6+p
6)-f(d
1+p
1，d
3+p
3，d
5+p
5，d
7+p
7)-e
2
Notice that the function f (.) that has two above variablees can the iteration evaluation; Such as
f(a，b，c)＝f(f(a，b)，c)
The course of work of the LDPC decoder 305 that uses non-Gray code mapping is described now.In step 1001, the likelihood ratio logarithm v of LDPC decoder 305 initialization codes bit before carrying out the iteration first time according to (reaching shown in Figure 12 A) described below step:
Here, v
N → kiExpression is sent into its adjacent check-node k from bit node n
iInformation, u
nExpression is corresponding to the demodulator output of bit n, and N is a codeword size.
In step 1003, a check-node k is updated, thereby input v produces output w.In Figure 12 B as seen, from d
cIndividual adjacent bit node is input to the input information v of check-node k
N1 → k, v
N2 → k..., v
Ndc → kRepresent.Our target is will calculate check-node k to export to d
cThe output information of individual adjacent bit node.These information are represented as:
w
K → n1, w
K → n2..., w
K → ndc, wherein
Function sheet g (.) is defined as follows:
g(a，b)＝sign(a)×sign(b)×{min(|a|，|b|)}+LUT
g(a，b)，
LUT wherein
g(a, b)=ln (1+e
-| a+b|)-ln (1+e
-| a-b|).And function f is the same, and the function g that has two above variablees can the iteration evaluation.
Then, according to step 1005, decoder 305 output posterior probability information (Figure 12 C), satisfy:
According to step 1007, judge whether all parity check equations all are satisfied.If these parity check equations are not all to be satisfied, in step 1009, decoder 305 will be derived 8-PSK bit metric and channel input u again so
nUpdate bit node in step 1011 then.As shown in Figure 14 C, from d
vIndividual adjacent check-node is input to the input information w of bit node n
K1 → n, w
K2 → n..., w
Kdv → nRepresent.D is calculated and returned to the output information of bit node n
vIndividual adjacent check-node; These information are used
v
N → k1, v
N → k2..., v
N → kdvExpression, and following calculating:
In step 1013, decoder 305 output hard decisions (under the situation that all parity check equations all are satisfied):
Said method is suitable for when using non-Gray code to indicate.But, when using Gray code to indicate, carry out the treatment step shown in Figure 11.
Figure 11 shows the workflow diagram of the LDPC decoder that uses the Gray code mapping according to an embodiment of the invention, and this decoder as shown in Figure 3.When using Gray code to indicate, preferably only before the LDPC decoder, generate a bit metric, after each LDPC decoder iteration because the bit metric of regenerating can only produce inappreciable performance improvement.In step 1101 and 1103, the same with step 1001 shown in Figure 10 and 1003, the likelihood ratio logarithm v of coded-bit is carried out initialization, and upgrade check-node.Then in step 1105, bit node n is updated.Subsequently, a decoder output posterior probability information (step 1107).In step 1109, judge whether all parity check equations all are satisfied; If satisfy, decoder is exported hard decision (step 1111) so.Otherwise with regard to repeated execution of steps 1103-1107.
Figure 13 A shows the flow chart of steps that is used for the information of sending between calculation check node and the bit node according to an embodiment of the invention, has adopted front and back to method in the calculating.Have d for one
cThe check-node of bar adjacent edge needs to carry out d
c(d
c-1) inferior computing and repeatedly g (. .) function.Yet front and back are reduced to 3 (d to method with computational complexity
c-2), wherein stored d
c-1 variable.
With reference to Figure 12 B, from d
cIndividual adjacent bit node is input to the input information v of check-node k
N1 → k, v
N2 → k..., v
Ndc → kRepresent.Need calculate output information and return to d from check-node k
cIndividual adjacent bit node; These output information w
K → n1, w
K → n2..., w
K → ndcRepresent.
With front and back when method is calculated these output informations, forward variable f
1, f
2... f
DcBe defined as follows:
f
1＝v
1→k
f
2＝g(f
1，v
2→k)
f
3＝g(f
2，v
3→k)
f
dc＝g(f
dc-1，v
dc→k)
In step 1301, calculate these forward variables, and under in step 1303, their being stored.
Similarly, the back is to variable b
1, b
2... b
DcBe defined as follows:
b
dc＝v
dc→k
b
dc-1＝g(b
dc，v
dc-1→k)
b
1＝g(b
2，v
1→k)
In step 1305, calculate these backs to variable.Subsequently, in step 1307 according to the forward variable under storing and calculate afterwards calculate output information to variable.The following calculating of output information:
w
k→1＝b
2
w
k→i＝g(f
i-1，b
i+1) i＝2，3，…，d
c-1
w
k→dc＝f
dc-1
In this method, has only forward variable f
1, f
2, f
DcNeed be stored.When after to variable b
iWhen being calculated, output information w
K → iAlso calculated simultaneously, stored the needs of back to variable thereby omitted.
As described below, can also further improve assumed (specified) load by parallel method.
Figure 13 B shows the flow chart of steps that is used for the information of sending between calculation check node and the bit node according to an embodiment of the invention, has adopted parallel method in the calculating.In step 1311, for having from d
cThe input v of individual adjacent bit node
N1 → k, v
N2 → k..., v
Ndc → kCheck-node k calculate following parameters:
Notice function g (. .) can also following expression:
Make full use of function g (. .) iterative nature, can obtain following formula:
Therefore, w
K → n1Can solve in the following manner:
Ln (.) in the above-mentioned equation can be utilized a look-up table LUT
xObtain (step 1313), LUT
xRepresentative function ln|e
x-1|.Unlike other look-up tables LUT
fOr LUT
g, table LUT
xMay need the clauses and subclauses identical with quantization level quantity.According to step 1315, in case obtained γ
k, will utilize above-mentioned equation to be all n with parallel mode
iCalculate w
K → n1
γ
kCalculating time of implementation log preferably
2(d
c).
Figure 14 A-14C shows several curve charts, and these curve charts have shown the simulation result that generates the LDPC sign indicating number according to various embodiments of the present invention.Specifically, Figure 14 A-14C shows the performance of using more high order modulation and 3/4 code check (QPSK, 1.485 bit/symbol), 2/3 code check (8-PSK, 1.980 bit/symbol) and the LDPC sign indicating number of 5/6 code check (8-PSK, 2.474 bit/symbol).
Have two kinds of method in common to realize interconnection between check-node and the bit node: (1) is parallel method fully, and (2) part parallel method.In parallel fully structure, all nodes and the interconnection between them all are physics realizations.The advantage of this structure is speed.
But parallel organization can be introduced bigger complexity when realizing all nodes and the connection between them fully.Therefore under complete parallel organization, need less block length reduce complexity.Under the sort of situation, for identical clock frequency, may cause throughput descend in proportion and FER to the deterioration of Es/No.
The second method that realizes the LDPC coding is a subclass of the whole nodes of physics realization, and only uses " physics " nodes of these limited quantities to handle all " function " nodes of coding.Although the LDPC decoder functions can be processed very simple and can carry out with parallel mode, the further challenge in the design is to set up between the bit node that how distributes in " at random " and the check-node to communicate by letter.According to one embodiment of present invention, decoder 305 (Fig. 3) solves this problem by in structurized mode memory being carried out access.So that realize a kind of coding that seems at random.Below with reference to Figure 15 A and 15B this method is described.
Figure 15 A and 15B show the top and the bottom margin of memory according to an embodiment of the invention respectively, and this memory is organized supports the structuring access to realize the randomness in the LDPC coding.Concentrate effort by generation to parity matrix, just can implementation structure access under the prerequisite of not damaging the real random code performance.In general, parity matrix can be specified with being connected between check-node and the bit node.For instance, bit node is divided into 392 1 groups (for the example purpose shows 392).In addition, suppose to be connected to the check-node on first bit node of 3 rank, for example be numbered as a, b, c, the check-node that is connected to so on second bit node just is numbered as a+p, b+p and c+p, the check-node that is connected on the 3rd bit node just is numbered as a+2p, b+2p and c+2p, or the like.For 392 bit nodes of next group, the check-node that is connected to first bit node is different from a, b, c, thereby by selecting suitable p, just can allow all check-nodes have identical exponent number.On natural constant, carry out a random search, make the LDPC sign indicating number that generates be 4 iteration and 6 iteration independently.
Above-mentioned be arranged in the auxiliary storage access of carrying out in check-node and the bit node processing procedure.The value on the limit in the bipartite graph can be stored in a kind of storage media, such as random-access memory (ram).For LDPC sign indicating number very at random, in check-node and bit node processing procedure, need with random fashion one by one the value of opposite side carry out access.But this access plan is too slow for the high data rate applications occasion.RAM among Figure 15 A and the 15B organizes in some way, thereby can obtain large quantities of relevant limits in a clock cycle; Correspondingly, these values should be placed on " together " in memory.We observe, in actual applications, even used real random code, for one group of check-node (and corresponding bit node), relevant limit also can be placed next to each other among the RAM, but the dependence edge adjacent with one group of bit node (corresponding check-node) will be by random dispersion in RAM.Therefore, " together " among the present invention comes from the design of parity matrix itself.That is to say that the design of check matrix will guarantee that the dependence edge of one group of bit node and check-node is stored among the RAM simultaneously together.
As seen, each square frame comprises the value on a limit from Figure 15 A and 15B, and described limit is a plurality of bits (such as 6).According to one embodiment of present invention, limit RAM is divided into two parts: top margin RAM (Figure 15 A) and base RAM (Figure 15 B).Base RAM comprises for example limit between the 2 rank bit nodes and check-node.Top margin RAM comprises the bit node that is higher than 2 rank and the limit between the check-node.Therefore, for each check-node, 2 adjacent sides are stored among the RAM of base, and remaining limit all is stored among the top margin RAM.
The continuous example that goes up is once chosen one group of 392 bit node and 392 check-nodes for processing.For the processing of 392 check-nodes, from top margin RAM, take out the continuous row of q bar, from the RAM of base, take out 2 continuous row.In this example, the exponent number of each check-node is q+2.For the processing of bit node, if 392 bit node exponent numbers of this group are 2, their limit all is arranged in 2 continuous row of base RAM so.If exponent number d＞2 of bit node, all to be arranged in certain d of top margin RAM capable on their limit so.The address that this d is capable can be stored in the nonvolatile memory, such as read-only memory (ROM).Wherein the stored limit of delegation is corresponding to article one limit of 392 bit nodes, and the limit in another row is corresponding to the second limit of 392 bit nodes, or the like.In addition, the column index that belongs to the limit of one group of first bit node in 392 nodes during each is gone also can be stored among the ROM.Initial column index is followed with " revolution " form in limit corresponding to second, third node such as bit such as grade.For instance, if the j bar limit in the delegation belongs to first bit node, j+1 bar limit just belongs to second bit node so, and j+2 bar limit belongs to the 3rd bit node ..., and j-1 bar limit belongs to the 392nd bit node.
Above-mentioned structure (as shown in Figure 15 A and 15B) has been arranged, and the memory access speed during the LDPC coding has just improved greatly.
Figure 16 shows a computer system 1600, can realize one embodiment of the present of invention in this system.This computer system 1600 comprises a bus 1601 or other are used to the communicator of the information of transmitting, and also comprises a processor 1603 that is connected on the bus 1601, is used for process information.Computer system 1600 also comprises main storage 1605, and as random-access memory (ram) or other dynamic storage device, memory is connected on the bus 1601, the instruction that is used for store information and will be carried out by processor 1603.Main storage 1605 can also be used in processor 1603 execution command storage temporary variable or other average informations.Computer system 1600 also comprises a read-only memory (ROM) 1607 or other static memories, and this memory is connected on the bus 1601, is used for storing the instruction of static information and processor 1603.A storage device 1609 as disk or CD, is connected on the bus 1601 in addition, is used for store information and instruction.
According to one embodiment of present invention, the generation of LDPC sign indicating number realizes by computer system 1600, and this is to carry out a group of being stored in the main storages 1605 by processor 1603 to instruct and finish.Can be from other computer-readable medium, as storage device 1609, in main storage 1605 is read in this class instruction.Stored command sequence makes processor 1603 finish wherein said treatment step in the execution main storage 1605.Can also in the multiprocessing structure, use one or more processors to carry out instruction stored in the main storage 1605.In other implementation, can realize embodiments of the invention jointly with the instruction of hard-wired circuitry instead of software or in conjunction with software instruction.Therefore, implementation of the present invention is not limited to any specific hardware circuit and the combination of software.
Here using term " computer-readable medium " to refer to any participation provides instruction to the medium of processor 1603 for execution.This medium can be a various ways, including, but not limited to non-volatile medium, volatibility medium and transmission medium.Non-volatile medium comprises for example CD or disk, as memory device 1609.The volatibility medium comprises dynamic memory, and for example main storage 1605.Transmission medium comprises coaxial cable, copper cash and optical fiber, comprises the metal wire that constitutes bus 1601.Transmission medium can also be sound wave, light wave or electromagnetic wave form, just as what produce in radio frequency (RF) and infrared ray (IR) data communication.The general type of computer-readable medium comprises, but for example floppy disk, floppy disc, hard disk, tape, any other magnetizing mediums, CD-ROM, CDRW, DVD, any other optical medium, punched card, paper tape, optical markings paper tape, any other physical medium-these physical mediums all have perforation pattern or the mark of other optical identifications, RAM, PROM, EPROM, FLASH-EPROM, any other storage chip or module, carrier wave or any computer-readable medium.
When providing the instruction that to carry out, can use the computer-readable medium of various ways to processor.For instance, be used for realizing that at least a portion instruction of the present invention can be stored on the disk of a remote computer at first.In this case, remote computer is written into main storage with instruction and utilizes modulator-demodulator to send instruction by telephone wire.The modulator-demodulator of local computer system receives data and utilizes an infrared transmitter that data transaction is become an infrared signal on telephone wire, again infrared signal is sent to a portable computing device, such as a PDA(Personal Digital Assistant) and notebook computer.An infrared detector on the portable computing device receives information entrained on the infrared signal and instruction, and data are put on the bus.Bus is sent to main storage to data, and processor obtains and executes instruction from main storage again.The instruction that main storage receives can optionally be stored in the memory device before or after processor is carried out.
Therefore, various embodiment of the present invention provide a kind of method that is used for generating structure low-density checksum (LDPC) sign indicating number, so that simplify encoder.By the restriction parity matrix is the structure that following triangle battle array is come regulation LDPC sign indicating number.In addition, this method can also make full use of the unequal error protection ability of LDPC sign indicating number to transmitted bit, provides extra error protection with the bit that is more vulnerable to the mistake influence in high-order modulation constellation figure (as 8-PSK (phase shift keying)).Decode procedure repeats regenerated signal planisphere bit metric after being included in each decoder iteration or a plurality of decoder iteration in the LDPC decoder.Said method can be at the prerequisite decline low complex degree of any sacrifice in performance not.
In conjunction with various embodiments and implementation the present invention has been described herein, but the present invention is not limited thereto, but has contained the structure of multiple improvement and equivalence, they are all within additional claim scope.
Claims (16)
1. the method for the low-density checksum LDPC sign indicating number that is used to decode, this method comprises:
Receive a priori probability information that depends on distance vector information from the bit metric maker, described distance vector information comprises the information of the distance dependent between the symbolic point that noise symbol point and the signal constellation which relevant with the LDPC sign indicating number are arranged that receives, wherein, determine the signal constellation which bit metric based on described distance vector information, and the symbol of described signal constellation which uses gray encoding, thus the parity check bit that easier affected bit is assigned in the symbol constellation of gray encoding at least with the symbol constellation of gray encoding in the parity check bit that arrives of insusceptible Bit Allocation in Discrete as many;
Send a posterior probability information that depends on priori probability information from decoder;
Will be on continuous physical storage locations about the information storage of the bit node of LDPC sign indicating number and check-node;
In decoder, judge whether satisfy the parity check equation relevant with the LDPC sign indicating number according to prior probability and posterior probability information;
In the bit metric maker optionally according to determination step regenerated signal planisphere bit metric; And
In decoder according to regeneration signal constellation which bit metric output decoder message.
2. method according to claim 1 is characterized in that, also comprises:
Determine external information according to a posterior probability information and a priori probability information; And
According to the external information output symbol probability relevant with signal constellation which.
3. method according to claim 1 is characterized in that, described LDPC sign indicating number all uses a kind of structurized parity matrix to encode, and this structurized parity matrix has applied restriction to the submatrix of parity matrix.
4. method according to claim 1 is characterized in that, described signal constellation which comprises a kind of among 8-PSK, 16-QAM and the QPSK.
5. the system of the low-density checksum LDPC sign indicating number that is used to decode, this system comprises:
Be used for receiving a device that depends on the priori probability information of distance vector information from the bit metric maker, described distance vector information comprises the information of the distance dependent between the symbolic point that noise symbol point and the signal constellation which relevant with the LDPC sign indicating number are arranged that receives, wherein, determine the signal constellation which bit metric based on described distance vector information, and the symbol of described signal constellation which uses gray encoding, thus the parity check bit that easier affected bit is assigned in the symbol constellation of gray encoding at least with the symbol constellation of gray encoding in the parity check bit that arrives of insusceptible Bit Allocation in Discrete as many;
Be used for sending a device that depends on the posterior probability information of priori probability information from decoder;
Being used for will be about the bit node of LDPC sign indicating number and the device of information storage on continuous physical location of check-node;
Be used for judging the device that whether satisfies the parity check equation relevant according to prior probability and posterior probability information with the LDPC sign indicating number at decoder;
Be used at the bit metric maker optionally according to the device of judging regenerated signal planisphere bit metric; And
Be used at the device of decoder output based on the decode messages of regenerated signal planisphere bit metric.
6. system according to claim 5 is characterized in that, also comprises:
Be used for determining the device of external information according to a posterior probability information and priori probability information; And
Be used for device according to the external information output symbol probability relevant with signal constellation which.
7. system according to claim 5 is characterized in that, described LDPC sign indicating number all uses a kind of structurized parity matrix to encode, and this structurized parity matrix has applied restriction to the submatrix of parity matrix.
8. system according to claim 5 is characterized in that, described signal constellation which comprises a kind of among 8-PSK, 16-QAM and the QPSK.
9. the receiver of the low-density checksum LDPC sign indicating number that is used to decode, this receiver comprises:
A bit metric maker, this maker is provided to generate a priori probability information according to distance vector information, described distance vector information comprises the information of the distance dependent between the symbolic point that noise symbol point and the signal constellation which relevant with the LDPC sign indicating number are arranged of reception, wherein, determine the signal constellation which bit metric based on described distance vector information, and the symbol of described signal constellation which uses gray encoding, thus the parity check bit that easier affected bit is assigned in the symbol constellation of gray encoding at least with the symbol constellation of gray encoding in the parity check bit that arrives of insusceptible Bit Allocation in Discrete as many;
Be set up the memory of continuous storage about the information of the bit node of LDPC sign indicating number and check-node;
A decoder, this decoder is provided to export a posterior probability information based on the priori probability information that receives from the bit metric maker, wherein decoder also is provided to judge whether satisfy the parity check equation relevant with the LDPC sign indicating number according to prior probability and posterior probability information, if do not satisfy parity check equation, decoder is just exported the decode messages based on regenerated signal planisphere bit metric so.
10. receiver according to claim 9, it is characterized in that, described bit metric maker also is provided to determine external information according to a posterior probability information and a priori probability information, and exports the symbol probability relevant with signal constellation which according to external information.
11. receiver according to claim 9 is characterized in that, described LDPC sign indicating number all uses a kind of structurized parity matrix to encode, and this structurized parity matrix has applied restriction to the submatrix of parity matrix.
12. receiver according to claim 9 is characterized in that, described signal constellation which comprises a kind of among 8-PSK, 16-QAM and the QPSK.
13. a method that is used to send the message of having used low-density checksum LDPC sign indicating number, this method comprises:
According to a structured odd-even check matrix input message is encoded, described structured odd-even check matrix applies restriction to generate the LDPC sign indicating number to the submatrix of parity matrix; And
Send the LDPC sign indicating number by a wireless communication system, wherein a receiver that communicates by wireless communication system is provided to the LDPC sign indicating number that the basis signal constellation which iterative decoding relevant with the LDPC sign indicating number receives, described receiver is set at one or more decoding iteration iteration regenerated signal planisphere bit metric afterwards, wherein, determine the signal constellation which bit metric based on the distance vector information between the symbolic point that noise symbol point and the signal constellation which relevant with the LDPC sign indicating number are arranged that receives, and the symbol of described signal constellation which uses gray encoding, thus the parity bit that easier affected bit is assigned in the symbol constellation of gray encoding at least with the symbol constellation of gray encoding in the parity check bit that arrives of insusceptible Bit Allocation in Discrete as many.
14. method according to claim 13, it is characterized in that, receiver in the described step of transmitting comprises a LDPC decoder, it is provided to send a posterior probability information that depends on priori probability information, this priori probability information is generated according to described distance vector information by a bit metric maker, and decoder judges whether satisfy the parity check equation relevant with the LDPC sign indicating number according to a prior probability and a posterior probability information.
15. method according to claim 13 is characterized in that, described signal constellation which comprises a kind of among 8-PSK, 16-QAM and the QPSK.
16. method according to claim 13 is characterized in that, described wireless communication system comprises the satellite of supporting the transmission of LDPC sign indicating number.
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| US39345702P | 2002-07-03 | 2002-07-03 | |
| US60/393,457 | 2002-07-03 |
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| JP (1) | JP3917563B2 (en) |
| KR (1) | KR100574306B1 (en) |
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Cited By (1)
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| CN102638629A (en) * | 2012-03-30 | 2012-08-15 | 西安烽火电子科技有限责任公司 | Shortwave modulator/demodulator and modulation/demodulation method thereof |
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| US7197690B2 (en) | 2002-05-31 | 2007-03-27 | Broadcom Corporation | Bandwidth efficient coded modulation scheme based on MLC (multi-level code) signals having multiple maps |
| KR100543154B1 (en) * | 2002-07-26 | 2006-01-20 | 휴우즈 일렉트로닉스 코오포레이션 | Method and system for generating low density parity check codes |
| US7234098B2 (en) * | 2003-10-27 | 2007-06-19 | The Directv Group, Inc. | Method and apparatus for providing reduced memory low density parity check (LDPC) codes |
| KR100918763B1 (en) * | 2003-11-14 | 2009-09-24 | 삼성전자주식회사 | Interleaving apparatus and method in a channel coder using a parallel concatenated low density parity check code |
| US7383487B2 (en) | 2004-01-10 | 2008-06-03 | Broadcom Corporation | IPHD (iterative parallel hybrid decoding) of various MLC (multi-level code) signals |
| EP1708367A4 (en) | 2004-01-20 | 2009-02-11 | Nec Corp | Inspection matrix generation method, data transmission system, encoding device, decoding device, and inspection matrix generation program |
| KR100594818B1 (en) | 2004-04-13 | 2006-07-03 | 한국전자통신연구원 | A Decoding Apparatus of Low-Density Parity-Check Codes Using Sequential Decoding, and a method thereof |
| KR20050118056A (en) * | 2004-05-12 | 2005-12-15 | 삼성전자주식회사 | Method and apparatus for channel encoding and decoding in mobile communication systems using multi-rate block ldpc codes |
| CN100362755C (en) * | 2004-06-28 | 2008-01-16 | 华为技术有限公司 | Method for evaluating sign |
| US7395490B2 (en) | 2004-07-21 | 2008-07-01 | Qualcomm Incorporated | LDPC decoding methods and apparatus |
| DE602005026754D1 (en) * | 2004-08-10 | 2011-04-21 | Samsung Electronics Co Ltd | Apparatus and Method for Coding and Decoding Low-Density Block Parity Check Codes (LDPC) |
| FI121431B (en) | 2004-09-13 | 2010-11-15 | Tamfelt Pmc Oy | Tissue structure intended for use in a paper machine and method for manufacturing the same |
| WO2006027818A1 (en) * | 2004-09-03 | 2006-03-16 | Mitsubishi Denki Kabushiki Kaisha | Ldpc code generating method and communication apparatus |
| KR100641052B1 (en) * | 2004-12-08 | 2006-11-02 | 한국전자통신연구원 | LDPC encoder and decoder, and method for LDPC encoding and decoding |
| EP1717959A1 (en) * | 2005-04-29 | 2006-11-02 | STMicroelectronics N.V. | Method and device for controlling the decoding of a LDPC encoded codeword, in particular for DVB-S2 LDPC encoded codewords |
| CN100454768C (en) * | 2005-06-01 | 2009-01-21 | 西南交通大学 | Non-logarithm-domain high-speed maximum posteroir probability Turbo decoding method |
| US7526715B2 (en) | 2005-10-17 | 2009-04-28 | Ramot At Tel Aviv University Ltd. | Probabilistic error correction in multi-bit-per-cell flash memory |
| ATE534999T1 (en) * | 2005-10-17 | 2011-12-15 | Univ Ramot | PROBABILISTIC ERROR CORRECTION IN A MULTI-BIT PER CELL FLASH MEMORY |
| JP4727380B2 (en) * | 2005-10-24 | 2011-07-20 | Ｋｄｄｉ株式会社 | Decoding device and method, and demodulation decoding device and method |
| CN102386996B (en) * | 2010-09-01 | 2015-11-25 | 国家广播电影电视总局广播科学研究院 | A kind of physical layer data in satellite two-way communication transmission method and device |
| CN103067025B (en) * | 2013-01-01 | 2017-03-01 | 中国传媒大学 | LDPC encoder and coded method in CMMB based on the circulation of block row |
| US10148326B2 (en) * | 2015-07-06 | 2018-12-04 | Qualcomm Incorporated | Methods and apparatus for extended receiver processing time |
| US10122382B2 (en) * | 2015-09-18 | 2018-11-06 | SK Hynix Inc. | VSS LDPC decoder with improved throughput for hard decoding |
| CN107733570B (en) * | 2017-09-27 | 2020-08-14 | 西安邮电大学 | Constellation mapping method based on algebraic interleaver and searching method of mapping mode |
| CN111786680B (en) * | 2019-04-03 | 2023-01-13 | 华为技术有限公司 | Method and device for determining generator matrix |
| CN115298980B (en) * | 2020-03-23 | 2024-09-17 | 华为技术有限公司 | Communication device and method for iterative code design |
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| CA2310186A1 (en) * | 2000-06-02 | 2001-12-02 | Jeffrey P. Castura | Method and system for decoding |
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| CN102638629A (en) * | 2012-03-30 | 2012-08-15 | 西安烽火电子科技有限责任公司 | Shortwave modulator/demodulator and modulation/demodulation method thereof |
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| CN1527499A (en) | 2004-09-08 |
| JP3917563B2 (en) | 2007-05-23 |
| JP2004080753A (en) | 2004-03-11 |
| EP1379001A2 (en) | 2004-01-07 |
| EP1379001A3 (en) | 2004-03-10 |
| KR100574306B1 (en) | 2006-04-27 |
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| HK1068463A1 (en) | 2005-04-29 |
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