CN1280898C - Double-enclosure protective-ring structure for semiconductor chip - Google Patents
Double-enclosure protective-ring structure for semiconductor chip Download PDFInfo
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- CN1280898C CN1280898C CN 02106072 CN02106072A CN1280898C CN 1280898 C CN1280898 C CN 1280898C CN 02106072 CN02106072 CN 02106072 CN 02106072 A CN02106072 A CN 02106072A CN 1280898 C CN1280898 C CN 1280898C
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Abstract
The present invention relates to a double-seal protective ring structure for semiconductor chips, which at least comprises a semiconductor chip of which the interior comprises elements and internal circuits, a plurality of dielectric layers positioned on the semiconductor chip, seal protective rings at inner side which are used for preventing moisture and oxygen intrusion and respectively positioned in the dielectric layers and in the outer edge area of the semiconductor chip for sealing and surrounding the elements and the internal circuits, and seal protective rings at outer side for blocking external stress so as to avoid that internal chip structures are destroyed when the chip is cut, wherein the seal protective rings at outer side are respectively positioned in the dielectric layers and the outer side of each seal protective ring at inner side.
Description
Technical field
The present invention relates to semiconductor structure, particularly a kind of use comprises the double-enclosure retaining ring structure that is applied to semiconductor wafer of at least two sealing retaining ring (sealring) structures.
Background technology
In recent years, because the progress of semiconductor technology causes the wafer density on the semiconductor crystal wafer to improve constantly.Along with the quick evolution of semiconductor technology, electronic product is under the promotion of the fast trend of compact, multi-functional speed, and the not only more and more density of the semi-conductive I/O number of IC are also more and more higher, and the requirement of speed is also more and more faster.After the downsizing along with electronic component dimensions, many new challenges constantly appear in integrated circuit in manufacture process.And that semi-conductor industry involves is extremely wide, and its processing procedure relates to many different technology and the scope that contains comprises fields such as physics, chemistry, material, electronic motor.
After the processing procedure of integrated circuit entered the deep-sub-micrometer field, the resistance-capacitance sluggishness of metal interconnecting significantly improved, and also therefore influenced the arithmetic speed and the access rate of integrated circuit.In order to improve the aggregation density of integrated circuit, under the condition that live width and line-spacing all should not improve, the material of changing metal interconnecting and interlayer dielectric layer is best selection.In addition, for making intraconnections or interlayer hole, developed the method that is called dual damascene (dual damascene) in copper wiring, it comprises the processing procedure that relates to irrigation canals and ditches and bottom interlayer hole.Irrigation canals and ditches and interlayer hole are inserted electric conducting material simultaneously, therefore form intraconnections and metal bolt simultaneously.The prior art of relevant dual damascene can be consulted the Boeck of motorola inc; People such as Bruce Allen are at No. the 5880018th, United States Patent (USP) disclosed " Method for manufacturing a lowdielectric constant inter-level integrated circuit structure ".
And aspect metal interconnecting, metal material changes the copper metal into by original Al-Si-Cu alloy or aluminium copper, except having low-resistance characteristic, have more sub-animal migration of good antidetonation and good anti-stress, except the operation rate that can improve element, reliability that simultaneously can lift elements; On the other hand, interlayer dielectric layer then must select the material of low-k (Low Dielectric Constant) to replace original silicon dioxide, to reduce the coupling capacitance between the metal interconnecting.The dielectric constant of silicon dioxide is about 4.2, therefore must select dielectric constant less than 4.2 dielectric medium as interlayer dielectric layer, can reach the effect that reduces the resistance-capacitance sluggishness, for example: fluorine doped silica (SiOF), organic spin-coating glass (HSQ) or the like.Another effective advanced low-k materials is black diamond (blackdiamond), and it is formed by methyl-monosilane (methylsilane), and its composition is silicon 20%, oxygen 30%, carbon 9%, hydrogen 36%, reaches other elements.It is hole that 36% volume is arranged approximately because of black diamond, so its dielectric constant is about 2.9, is a kind of advanced low-k materials of having very much potentiality.
Generally, after semiconductor element is formed at wafer,, materials used is sealed wafer in order to protect above-mentioned wafer in order to protect these elements.Usually sealing retaining ring (seal ring) is formed among the dielectric layer and around the neighboring area of wafer, is positioned at inboard element with protection.In encapsulation technology, owing to having relatively poor mechanical stress, advanced low-k materials causes serious problem, the normal interface along low-k oxide layer or nitration case that breaks extends and the destruction copper interconnects, and this crack will stop at copper interconnects and cause aqueous vapor or oxygen to invade in the crack thus, and with the intraconnections oxidation, even can arrive inner circuit.A kind of advanced person's sealing retaining ring structure must be proposed for the demand in response to copper wiring, advanced low-k materials.
Summary of the invention
Purpose of the present invention is for proposing a kind of semiconductor structure with double-enclosure retaining ring, and wherein the first sealing retaining ring can absorb the mechanical stress of cutting crystal wafer, and the second sealing retaining ring is in order to prevent the intrusion of aqueous vapor or oxygen.
A kind of double-enclosure retaining ring structure that is applied to semiconductor wafer of the present invention comprises at least: semiconductor wafer, and its inside comprises element and internal circuit; The plural layer dielectric layer is positioned on the above-mentioned semiconductor wafer; The sheath structure is positioned on the plural layer dielectric layer; Outer edge area at this semiconductor wafer is provided with, extend to the outside sealing retaining ring that sheath structure upper surface prevents the inboard sealing retaining ring that aqueous vapor, oxygen are invaded and stops external stress from the semiconductor wafer upper surface, described outside sealing retaining ring is positioned at the outside of this inboard sealing retaining ring.
Wherein above-mentioned plural layer dielectric layer comprises dielectric constant less than 4.2 dielectric material.Above-mentioned outside sealing retaining ring comprises the horizontal-extending conductive layer, reaches the conductive layer of arranged perpendicular.Above-mentioned inboard sealing retaining ring comprises the horizontal-extending conductive layer, reaches the conductive layer of arranged perpendicular.
The horizontal-extending conductive layer of above-mentioned outside sealing retaining ring, and the conductive layer of arranged perpendicular, and the horizontal-extending conductive layer of inboard sealing retaining ring, and the conductive layer of arranged perpendicular can comprise one of compound crystal silicon, copper metal, copper alloy, aluminum metal, aluminium alloy, tungsten metal, tungsten alloy etc. or combination in any respectively.
Because the present invention comprises two sealing retaining rings, outside sealing retaining ring can prevent mechanical stress when wafer cuts destruction will stop that external stress destroys the internal wafer structure to avoid it; Damage when retaining ring is sealed in the outside in cutting when forming the crack, inboard sealing retaining ring can prevent that aqueous vapor, oxygen are along this crack intrusion, with internal circuit or the element of avoiding this semiconductor wafer of oxidation.
Description of drawings
Figure 1 shows that the vertical view of double-enclosure retaining ring semiconductor structure of the present invention;
Figure 2 shows that the sectional view of double-enclosure retaining ring semiconductor structure of the present invention.
Embodiment
The present invention discloses one and is applied to the sealing retaining ring structure that semiconductor package process prevents stress, aqueous vapor or oxygen influence.In preferred embodiment, as shown in Figures 1 and 2, Figure 1 shows that the vertical view of double-enclosure retaining ring semiconductor structure of the present invention, Figure 2 shows that among Fig. 1 of the present invention along the sectional view of the double-enclosure retaining ring semiconductor structure of A-A ' tangent plane.Semiconductor wafer 100 comprises intraconnections 130 and connects the semiconductor element 110,120 that is positioned at interior zone, and a plurality of contact mats (contact pad) 140 also are disposed on the wafer 110.Only purchasing in order to be an embodiment of said apparatus, non-is feature of the present invention, so non-in order to limit the present invention.
Consult Fig. 2, plural layer dielectric material 105 is formed on the wafer 100, and above-mentioned dielectric material 105 is an advanced low-k materials to be applied to copper wiring.Wherein comprise but be not defined as fluorine doped silica (SiOF), organic spin-coating glass (HSQ), black diamond (black diamond) or the like.One sheath structure 170 is draped over one's shoulders and is invested on the plural layer dielectric material 105 in order to protection internal semiconductor element.
Outside sealing retaining ring 150 and inboard sealing retaining ring 160 are formed at respectively among the plural layer dielectric material 105, and structure rings such as semiconductor element 110,120, intraconnections 130 and contact mat (contact Pad) 140 are around in wherein, so be called the sealing retaining ring.Above-mentioned outside sealing retaining ring 150 comprises the conductive layer 155 of horizontally extending conductive layer 156 and arranged perpendicular, and in like manner, inboard sealing retaining ring 160 also comprises the conductive layer 165 of horizontally extending conductive layer 166 and arranged perpendicular.The material of forming above-mentioned conductive layer 156,155,166 and 165 can comprise compound crystal silicon, copper metal, copper alloy, aluminum metal, aluminium alloy, tungsten metal, tungsten alloy or the like.The rest may be inferred, and metal that is fit to and alloy all can be applied among the present invention as outside sealing retaining ring 150 or inboard sealing retaining ring 160.
Above-mentioned outside sealing retaining ring 150 can prevent mechanical stress when cutting crystal wafer destruction will stop that external stress destroys the internal wafer structure to avoid it.When sealing retaining ring 150 in the outside damages during in cutting when forming the crack, inboard sealing retaining ring 160 major functions are to prevent that aqueous vapor, oxygen from invading along the crack avoiding the oxide-semiconductor structure, so the present invention can provide dual defence line.Therefore even the invasion of aqueous vapor or oxygen is arranged, it can cause the influence in the outside sealing retaining ring 150 or inboard sealing retaining ring 160 outsides, and not entail dangers in the structure of wafer internal circuit or element.
The above embodiment only is explanation technological thought of the present invention and characteristics, its purpose makes the personage who has the knack of this skill can understand content of the present invention and is implementing according to this, when not limiting claim of the present invention with it, promptly the equalization of doing according to disclosed spirit generally changes or modifies, and must be encompassed in the claim scope of the present invention.
Claims (6)
1. a double-enclosure retaining ring structure that is applied to semiconductor wafer is characterized in that, comprises at least:
Semiconductor wafer, its inside comprises element and internal circuit;
Multilayer dielectric layer is positioned on the above-mentioned semiconductor wafer;
The sheath structure is positioned on the multilayer dielectric layer;
Outer edge area at this semiconductor wafer is provided with, and extends to the outside sealing retaining ring that prevents the inboard sealing retaining ring that aqueous vapor, oxygen are invaded and stop external stress of sheath structure upper surface from the semiconductor wafer upper surface; Wherein, described outside sealing retaining ring is positioned at the outside of this inboard sealing retaining ring;
Described outside sealing retaining ring comprises the conductive layer of horizontal-extending conductive layer and arranged perpendicular;
Described inboard sealing retaining ring comprises the conductive layer of horizontal-extending conductive layer and arranged perpendicular.
2. the double-enclosure retaining ring structure that is applied to semiconductor wafer as claimed in claim 1 is characterized in that: above-mentioned multilayer dielectric layer comprises dielectric constant less than 4.2 dielectric material.
3. the double-enclosure retaining ring structure that is applied to semiconductor wafer as claimed in claim 1 or 2 is characterized in that: the described horizontal-extending conductive layer of above-mentioned outside sealing retaining ring comprises one of polysilicon, copper metal, copper alloy, aluminum metal, aluminium alloy, tungsten metal, tungsten alloy or combination in any.
4. the double-enclosure retaining ring structure that is applied to semiconductor wafer as claimed in claim 1 or 2 is characterized in that: the conductive layer of the described arranged perpendicular of above-mentioned outside sealing retaining ring comprises one of polysilicon, copper metal, copper alloy, aluminum metal, aluminium alloy, tungsten metal, tungsten alloy or combination in any.
5. the double-enclosure retaining ring structure that is applied to semiconductor wafer as claimed in claim 1 or 2 is characterized in that: the described horizontal-extending conductive layer of above-mentioned inboard sealing retaining ring comprises one of polysilicon, copper metal, copper alloy, aluminum metal, aluminium alloy, tungsten metal, tungsten alloy or combination in any.
6. the double-enclosure retaining ring structure that is applied to semiconductor wafer as claimed in claim 1 or 2 is characterized in that: the conductive layer of the described arranged perpendicular of above-mentioned inboard sealing retaining ring comprises one of polysilicon, copper metal, copper alloy, aluminum metal, aluminium alloy, tungsten metal, tungsten alloy or combination in any.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02106072 CN1280898C (en) | 2002-04-10 | 2002-04-10 | Double-enclosure protective-ring structure for semiconductor chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02106072 CN1280898C (en) | 2002-04-10 | 2002-04-10 | Double-enclosure protective-ring structure for semiconductor chip |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1450632A CN1450632A (en) | 2003-10-22 |
| CN1280898C true CN1280898C (en) | 2006-10-18 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 02106072 Expired - Lifetime CN1280898C (en) | 2002-04-10 | 2002-04-10 | Double-enclosure protective-ring structure for semiconductor chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1280898C (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7893459B2 (en) * | 2007-04-10 | 2011-02-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Seal ring structures with reduced moisture-induced reliability degradation |
| CN104022105B (en) * | 2014-04-22 | 2018-12-18 | 上海华力微电子有限公司 | The protection ring and packaging and testing method of structure short circuit are tested when for preventing encapsulation |
-
2002
- 2002-04-10 CN CN 02106072 patent/CN1280898C/en not_active Expired - Lifetime
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| Publication number | Publication date |
|---|---|
| CN1450632A (en) | 2003-10-22 |
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Granted publication date: 20061018 |