CN1280828C - High-performance embedded semiconductor storing equipment having multidimensional one-stage bit line - Google Patents

Abstract

The present invention discloses a dynamic random access memory which solves the long-standing problem of overcrowding distribution intervals of memory devices by using a multidimensional bit line structure. Improvement on the design aspect of decoders further reduces the total area of the memory device. The present invention also discloses a novel memory access method. External users are unaware of data update operation carried out in the memory completely. DRAMs with high performance can be manufactured on the premise that the density of the memory is not lowered by the memory structure, and the requirements of the memory to system support are simplified greatly.

Description

A kind of manufacturing has the method for selecting transistorized embedded DRAM cell array

Technical field

The present invention relates to the high-performance semiconductor storage arrangement, especially relate to the in-line memory device that has along the one-stage bit line of different designs direction connection.

Background technology

Usually DRAM (dynamic RAM) is considered to a kind of high density, low cost, but the lower storage arrangement of performance.The DRAM in the market and the semiconductor memory system of other type (for example, static RAM (SRAM)) always seem that by comparison performance is lower.The density of DRAM is improved rapidly, and each integrated level for device all increases exponentially than previous generation.Rely on the superfine technology and improve memory unit, though can make DRAM reach higher integrated level, but DRAM is but quite slow in the improvement speed of aspect of performance, has produced gap thereby make between storage arrangement and the logical unit at aspect of performance.Present people have proposed a lot of new methods and have reduced this performance gap, and synchronous dram (SDRAM), expanding data output (EDO) DRAM, multiple row DRAM (MDRAM) and RAMBUS system etc. are the modal several methods that is used for improving the DRAM performance.The United States Patent (USP) U.S.4833653 that is proposed by people such as Mashiko and disclose a kind of method of the subarray that is activated selectively by the United States Patent (USP) U.S.No.4758993 that people such as Takemae propose is used for improving the performance of DRAM.The another kind of method that improves the DRAM performance then is that a SRAM cache is inserted DRAM inside (being called " composite memory ").The United States Patent (USP) U.S.No.5421000 that proposes by people such as Fortino, the United States Patent (USP) U.S.No.5226147 that proposes by people such as Fujishima and the specific embodiment that all discloses composite memory by the United States Patent (USP) U.S.5305280 that people such as Hayano propose.The subject matter of said method is that they are that the performance that improves DRAM has been paid quite high cost, and the improvement degree of memory performance still is not enough to remedy this gap.Another problem is that all above-mentioned technology all need and the incompatible special system design of computer system at present, therefore are difficult to it is used on the present computer system.

Another shortcoming of DRAM is that its storer is new data more, that is to say, the user need often read the content of memory cell, and with new data write store unit because this demand data, thus the system that supports DRAM than the system complex of supporting SRAM many.Memory data upgrades also can waste electric energy.The United States Patent (USP) U.S.5276843 that people such as Tillinghast propose discloses a kind of method that reduces the memory data renewal frequency, and the United States Patent (USP) U.S.5365487 that people such as United States Patent (USP) U.S.5305280 that people such as Hayano propose and Patel propose discloses a kind of DRAM that carries out the memory data updating ability automatically that has.Upgrade the electric energy that is consumed though these inventions have reduced memory data to a certain extent, the electric energy that can save compared with the present invention comes just not by a long chalk.And these patents still can't solve the resource conflict problem between memory data renewal and the normal running.

Recently, IDT (Integrated Device Technology) company declares them by DRAM being divided into the method for a plurality of subarrays, and the performance of DRAM has been reached near the degree of SRAM.This new unit and existing memory are incompatible, and it needs the special system support to upgrade conflicting between the operation with the read operation of processing memory with memory data.The area that it accounts for is bigger by 30% than DRAM, and performance is also poorer than the SRAM of same size.

Another major issue of DRAM design is that being spaced of its peripheral circuit is overstocked.Though the size of memory cell is reducing rapidly in recent years, also unsubstantial improvement of peripheral circuit or change.For example the size of peripheral circuits such as sensor amplifier, code translator and pre-charge circuit depends on the size at the interval of memory cell, when memory cell day by day dwindles along with technology of new generation, " getting into " some peripheral circuits just have been difficult in little closely-spaced between memory cell more.Memory array is divided into a plurality of little subarrays when improving performance, and this problem can be more outstanding.Each subarray all needs the peripheral circuit of oneself, and the shared area of these peripheral circuits will significantly increase.Therefore in foreseeable future, the integrated level of DRAM will have been decided by peripheral circuit probably.The United States Patent (USP) U.S.4920517 that people such as Yamauchi propose discloses a kind of utilization sensor amplifier has been placed on the storer two ends, the new method that the distribution of storer is doubled at interval.This method needs some sensor amplifiers that use more.Though it is wideer at interval than the distribution of the storer that passes conventional DRAM at interval to distribute for the storer that utilizes, be to use the Yamauchi technology after, the storer interval that distributes remains very little.

All foregoing invention provide the scheme that partly solves the reservoir designs problem with research and development, but have also brought new problem simultaneously.Therefore people's strong request is worked out and a kind ofly can be improved memory performance but can obviously not influence the solution of other characteristic (for example not increasing system's support of area occupied and user friendly type etc.).

Another difficult problem that the people that utilize ordinary skill to make dynamic RAM (DRAM) run into is, usually they always treat DRAM as the storage arrangement that is a kind of high density, low cost and low performance, and the limitation of this view makes them feel easily it to be integrated into a kind of in-line memory.This is because occur after superfine manufacturing technology and memory unit be improved, and just might realize the high integration of DRAM.At present typical DRAM manufacturing technology is four strata silicon, double-level-metal (4P2M) manufacturing technology.The sort memory manufacturing technology is relatively emphasized the structure of superfine on the manufacturing memory cell, and thinks that the performance on the logical circuit is less important.A kind of top-priority emphasis of the optimisation technique that is used to make the high speed logic device is different fully therewith, and it emphasizes the characteristic of transistorized performance and multilayered metal film.An example of at present typical logical device manufacturing technology is three-layer metal sheet, single poly-silicon (1P3M) technology.

As its name suggests, so-called in-line memory be exactly a kind of with some high performance logic circuits be integrated on the same chip for being positioned over high density memory devices on the identical chips.A difficult problem of making the high density in-line memory is how the manufacturing technology of two kinds of mutual contradictions to be combined.Present embedded technology needs four strata silicon and three-layer metals.This Technology Need surpasses 20 and covers operation.Utilize so complicated at present technology, the yield rate of wanting to reach desirable and certain reliability be difficulty very.And, since logical circuit and storage component part to technology require conflictingly, make present embedded manufacturing technology be difficult to produce high performance storage component part.Present embedded manufacturing technology neither one is proved to be success.The industrial utmost point of integrated circuit (1C) need successfully be developed the in-line memory device.

The applicant of present application for patent has utilized a kind of new technology to change the structure of IC storer, makes storage component part no longer conflict mutually with logical circuit, thereby successfully produces the in-line memory device.The example of this structural change has had disclosed waiting United States Patent (USP) U.S.08/653 of unexamined in 620 application cases.It is too close that patent application case has in the past solved the interval that distributes in the storer, can't arrange the problem of sensor amplifier position, and solved the demand of storer oneself Data Update by the hidden-type data method for updating.This patent application case has also further disclosed the solution of other problem.The single-transistor decoder circuit is following the code translator aspect and is solving the overstocked at interval problem that distributes.The little modification of typical logical circuit manufacturing technology or existing logical circuit manufacturing technology can be used to make memory cell.Utilize these new inventions, just can produce high-performance, highdensity in-line memory device.

Summary of the invention

Therefore, fundamental purpose of the present invention is under the situation that does not increase memory-size, improves the performance of semiconductor memory system.Another object of the present invention is to make the user friendly of DRAM stronger by improving device performance and simplified system support.Another object of the present invention is to provide a kind of follow-on semiconductor memory system, and its peripheral circuit has the integrated requirement of the following memory cell height of adaptation.

Another purpose of the present invention is to reduce the power consumption of high-performance semiconductor storer.

Another free-revving engine of the present invention is, under the prerequisite of not using complicated technology, produces the high density memory devices that has high performance logic circuits and come on same chip.Another fundamental purpose of the present invention be to make embedding/, formula DRAM the has performance identical with the high speed logic circuit.Another fundamental purpose of the present invention is to improve the output and the reliability thereof of in-line memory.

Semiconductor memory system according to technology manufacturing provided by the invention can achieve the above object and some other purpose.This storage arrangement comprises and a kind ofly connects the novel structure of bit lines, the design of a kind of new decoder circuit and a kind of new sequential control circuit along a plurality of distribution arrangements, and its advantage is need not wait for that memory data upgrades to finish just can finish one and read circulation.

For achieving the above object, the invention provides following technical scheme:

A kind of manufacturing has the method for selecting transistorized embedded DRAM cell array, and wherein this DRAM cell array and high performance logic circuits coexist as on the same base material, and this method comprises:

Adopt a gate electrode formation technology to form a DRAM simultaneously and select transistorized gate electrode, and be that a high performance logic circuits forms a logical circuit gate electrode, wherein select transistor gate anodizing thing to have identical thickness substantially with logical circuit gate electrode oxide, and

Employing wherein selects the transistor AND gate logic transistor to have identical substantially critical voltage forming the roughly the same embedded technology of selection transistor AND gate logic transistor.

According to the present invention, can obtain following and some other beneficial effect:

(1) therefore its multidimensional bit line structure bit line parasitic load that can reduce sensor amplifier greatly and born, can greatly improve memory performance.Our test findings illustrates, and the operating speed of storer of the present invention is than faster with the SRAM of capacity.

(2) the multidimensional bit line structure also allows us to support many pairs of bit line with a sensor amplifier.Therefore, for sensor amplifier and other peripheral circuit, distributed too close at interval problem with regard to not existing.Solved after the too close at interval problem that distributes, we just can pay the performance that increases the high cost raising storer that distribution area brings.

(3) Xin Ying design of encoder has reduced the size of memory decoder greatly, thereby makes the designer need not because of the code translator area occupied pays through the nose more, just memory array can be divided into the plurality of sub array.

Carry out when (4) Xin Ying I/O (IO) circuit design allows us that the memory data renewal process is deferred to the storer next operation.This technology allows us with the circulation of the Data Update in the normal running of storer " hiding ".Make storage arrangement the same with existing SRAM device good to user's friendly degree.In fact, storer of the present invention can be done compatiblely fully with existing SRAM device.

(5) this novel DRAM consumes the electric energy that is consumed far below existing DRA, can reach above-mentioned performance improvement.

(6) solved storer along the too close at interval problem of code translator direction distribution.Therefore, we can be divided into several less modules with a memory array, and do not sacrifice its useful area.This structural change allows us to serve as each DRAM memory cell with the less capacitor of capacity, and this has just simplified manufacturing process widely.

(7) in present logic IC manufacturing technology, only need increase several procedures simply, just can produce high density DRAM memory cell.The storage arrangement of resulting product support on same chip and the high performance operation of logical circuit.

(8) simplification of manufacturing process has improved product reliability greatly and has reduced production cost.

Though new technical characterictics more of the present invention limit in several dependent claims of the present invention, read purpose of the present invention, feature and detailed description hereinafter in conjunction with the drawings, structure of the present invention and content all are understood that.

Description of drawings

Fig. 1 is the schematic block diagram of the original manufacturing process of storage arrangement;

Fig. 2 is the simple schematic block diagram of many group semiconductor memory systems;

Fig. 3 a is the schematic block diagram that has the storage arrangement of two-dimentional bit line;

Fig. 3 b is the schematic block diagram that has the storage arrangement of three-dimensional bit line;

Fig. 4 a is the element distribution plan and the power consumption diagram thereof of existing memory set;

Fig. 4 b is the element distribution plan and the power consumption diagram thereof of the storage arrangement of first embodiment of the invention;

Fig. 5 is the synoptic diagram of sensor amplifier used in the present invention;

Fig. 6 imports/goes out the synoptic diagram of (10) circuit for the present invention;

Shown in Fig. 7 a is the oscillogram of minimum detectable signal in read cycle;

Shown in Fig. 7 b is the oscillogram of minimum detectable signal in data updating process;

Shown in Fig. 7 c is the oscillogram of minimum detectable signal in write cycle;

Fig. 8 is used for supporting the synoptic diagram of the IO circuit of quick reading of data for the present invention;

Shown in Fig. 9 is timing diagram between the minimum detectable signal of storage arrangement of the present invention;

Shown in Figure 10 is an example of existing CMOS code translator;

Figure 11 (a) is the synoptic diagram of enhancement mode monocrystal tubular type code translator of the present invention;

Figure 11 (b) is the control signal of code translator shown in Figure 11 (a) and the synoptic diagram of output signal;

Figure 12 (a) is the synoptic diagram of depletion type monocrystal tubular type code translator of the present invention;

Figure 12 (b) and Figure 12 (c) are the control signal of code translator shown in Figure 12 (a) and the synoptic diagram of output signal;

Figure 13 utilizes active transistor to serve as the synoptic diagram of the memory cell of depositing element;

Figure 14 (a-g) covers the sectional view that operation is made the processing step of DRAM memory cell for increasing by one in the logical circuit manufacturing process that is illustrated in standard;

Figure 15 (a-c) covers the vertical view that operation is made the processing step of DRAM memory cell for increasing by one in the logical circuit manufacturing process that is illustrated in standard;

Figure 16 (a-d) covers the sectional view that operation is made another processing step of autoregistration trench capacitors of DRAM memory cell for increasing by one in the logical circuit manufacturing process that is illustrated in standard;

Shown in Figure 17 is the vertical view of the memory cell made by the operation shown in Figure 17 (a)-(d);

Figure 18 (a) illustrates is sectional view to the unconfined capacitor of polarity of electrode voltage;

What Figure 18 (b) illustrated is to utilize transistor to separate near the sectional view of the memory cell of trench capacitors;

Shown in Figure 19 is the vertical view of actual storage of the present invention unit;

Figure 20 (a) illustrates is exemplary allocations figure in memory data update time of large-scale DRAM memory cell; And

Figure 20 (b) is the synoptic diagram that is equipped with the DRAM of bug patch code (ECC) holding circuit.

Embodiment

Before narration the present invention, at first introduce the conventional semiconductor storage arrangement, help the understanding of the present invention like this.

Fig. 1 shows the structure of the memory cell array of existing DRAM with electronic circuit and topo graph dual mode.Memory cell array 100 include some to bit line BL1, BL1# parallel to each other, BL2, BL2#, BL3, BL3# ..., BLn, BLn# (n is an integer) and several parallel to each other and with word line WL1, the WL2...WLm (m is an integer) of bit line square crossing.On these point of crossing, dispose respectively memory cell MC1, MC2 ..., MCn.In memory cell array shown in Figure 1 100, represent memory cell with circle one by one.Each memory cell comprises a field effect transistor switch transistor 110 and memory cell capacitors 112.Bit line BL is connected with the drain electrode of transistor 110.The gate electrode of transistor 110 is connected with word line WL.Sensor amplifier SA1, SA2 ... San is positioned at the end in memory cell array, and every pairs of bit line is connected with a sensor amplifier.For example, bit line BL1 and BL1# are connected to sensor amplifier SA1, bit line BL2 and BL2# be connected to sensor amplifier SA2 .... bit line BLn and BLn# are connected to sensor amplifier SAn.The output of these sensor amplifiers all is connected on the data output switch 120.This output switch 120 contains a traffic pilot 122 by code translator 124 controls.This output switch 120 can a selection from a plurality of sensor amplifiers be exported and output data is positioned on data bus D and the D#.

For example, when memory cell MC1 reads information, will carry out following operation.At first, word-line decoder 126 is selected word line WL2, and the transistor 110 in the memory cell MC1 is switched on.Thereby the signal charge in making in the capacitor 112 of memory cell MC1 is read on the bit line BL1#, so that produce small potential difference (PD) between bit line is to BL1 and BL1#.Sensor amplifier SA1 can amplify this potential difference (PD).Output switch 120 is selected the output of Sa1, and by traffic pilot 122 data is being sent on data bus D, the D#.After above-mentioned read operation finished, the electric charge that is stored in the memory cell capacitors 112 just was neutralized.Therefore, the raw data that SA1 must be read writes back in the memory cell MC1.This process is called as the Data Update of storer.Present employed sensor amplifier carries out Data Update to this memory cell always after it judges the state of memory cell.Make sure to keep in mind when selected WL2, along word line MC2, MC3 ... each memory cell of other of MCn all is switched on.Therefore, even we only need store the data to MC1, also must with other each sensor amplifier SA2, SA3 ... San all open with read with upgrade be stored in other each with memory cell that WL2 is connected in data.

The DRAM of this structure has following shortcoming:

(1) for from some the memory cell reading of data along a word line, we must read and upgrade along the data in all memory cells on this word line.Most of energy has all consumed on the Data Update rather than on the reading of data.Because a large amount of devices need be activated, can slow down the again operating speed of storer of the waste of this energy.

(2) when the scale of memory array increased, the stray capacitance of bit line (Cb) also can increase thereupon.Ratio between the capacity C m of memory cell and bit line stray capacitance Cb has determined the amplitude of bit line to potential difference (PD).If (Cm/Cb) ratio is too little, the read operation of storer is just unreliable.Therefore, (Cm/Cb) ratio normally determines a limiting factor of memory array scale.Therefore developed such as raceway groove technology, four layers of special fabrication processes technology such as polynary technology, be used for improving the capacity C m of memory cell, yet, improve Cm/Cb ratio and be still subject matter in the reservoir designs.

(3) in order to support the Data Update of storer, every pairs of bit line all needs a sensor amplifier.Along with the raising of memory cell integrated level, at interval will be fewer and feweri for the distribution of the use of sensor amplifier.Therefore, in very little distribution at interval, just be difficult to produce stable performance, the good sensor amplifier of operation.In integrated circuit (IC) design, this problem is commonly called " it is too close at interval to distribute ".Owing to be difficult to a plurality of active devices are clamp-oned a narrow space, the too close excess waste that always causes silicon area at interval distributes.Similar problem also can occur in the manufacturing of code translator and pre-charge circuit.

In order to reduce the influence of the problems referred to above, existing large-scale storer always is divided into plurality of sub arrays, as the memory set 200 shown in Fig. 2.Each memory sub-array group 200 all has code translator 210 and the output switch 212 of oneself.Every pairs of bit line in each memory set all needs a sensor amplifier 214.Output switch 212 can be selected the output of each memory set, and data are delivered on the data bus 220, so that high level amplifier and code translator can be delivered to data on the output pin.

This many group manufacturing technologies have partly solved the problems referred to above.Because whenever each memory set can both independent operation,, we reduce power consumption so can remaining on the method for low-voltage state by the memory set that will not be used.Because reducing of active region, the long journey speed of storer also is improved.Just (Cm/Cb) ratio can be remained in the proper range by the scale that limits each memory set.The multiple group type storer allows us to connect a cover sensor amplifier to save the energy, still, owing to still need the data of all memory cells that have been activated are upgraded, so every pairs of bit line still needs a sensor amplifier.This many group manufacturing technologies provide the part solution, but have also produced new problem simultaneously.Because each memory set all needs a complete set of peripheral circuit, this just makes the shared area of peripheral circuit just increase greatly.The area ratio that the less memory set of size is wasted on the peripheral circuit is bigger.It is to need the subject matter that solves in the multiple group type reservoir designs that balance improves benefit that the ratio of (Cm/Cb) brings and the peripheral circuit overstocked harm of bringing in interval that distributes.People such as Yamauchi make the distribution of sensor amplifier increase by one times at interval by sensor amplifier being arranged in the method for memory array both sides, still show too little at interval but distribute.People also propose many other solutions, but all these solutions all just partly deal with problems, also can produce some new problems simultaneously.

The present invention can address the above problem just.Fig. 3 a shows the memory construction of the embodiment of the invention with electronic circuit and topo graph dual mode.Basic device blocks memory cell 300 of the present invention, each memory cell all comprise several code translators 302, amplifier AMP1, AMP2 ..., AMPi and a plurality of memory module 310.These memory modules are arranged in pairs; Memory module 1# and memory module 1 symmetry, memory module 2# and memory module 2 symmetries ... memory module i# and memory module I symmetry.Each memory module all includes some word line switches 312, bit line switch 314 and a compact memory array 316.The state of word line switch 312 and bit line switch 314 is controlled by module select signal Song.For example, module select signal BLKSEL1 is controlling the word line switch in memory module 1 and the memory module 1# and the state of bit line switch.The memory cell that memory array comprises is similar to storer storage unit shown in Figure 1.In Fig. 3 a, represent these memory cells with circle.Each memory cell all with memory module in a short word line be connected with a short bit line.For example, in memory module 1, the gate electrode of memory cell MC12 is connected with module bit line BL12 with module word line WL12.Each module word line all is connected with a unit word line by word line switch 312.For example, WL12 is connected with UWL1 by a word line switch 312 by module select signal BLKSEL1 control; WL22 is connected with UWL2 by a word line switch by module select signal BLKSEL2 control; ... Wlij selects the word line switch of BLKSELi (i is an integer with j) control to be connected with UWLj by one by module.In this example, memory unit have two-layer bit line-be Institutional Layer bit line UBL1, UBLI#, UBL2, UBL2#...UBLn, UBLn# and module layer bit line BL11, BL11#, BL12, BL12# ... etc.The module layer bit line is made of ground floor metal (metal 1), and its orientation is vertical mutually with word line.The Institutional Layer bit line is made of second layer metal (metal 2), and its orientation and space line are parallel to each other.Each module layer bit line all is connected with a unit bit line by a bit line switch 314 in the module.For example, BL12 by one by the word line switch of module select signal BLKSEL1 control and UBL2 mutually.Connect: BL22 is connected with UBL2 by a word line switch by module select signal BLKSEL2 control ... .BLii is connected with UBLj by a word line switch by module select signal BLKSELi control, every pair of unit bit line all is connected with an amplifier, for example, UBL1 is connected with AMP1 with UBL1#; UBL2 is connected with AMP2 with UBL2# ... UBLi is connected with AMPi with UBLi#.These Institutional Layer bit lines and module layer bit line have constituted a two-dimentional bit line network, thereby make us utilize an amplifier just can support that the bit line in a plurality of modules is right.

The advantage of this two-dimentional bit line connected mode is only need expend the content that a little electric energy promptly can read storer, for example, when the memory cell from the WL12 of module 1 reads information, will carry out following operation.At first, module select signal BLKSEL1 is activated, other each module select signal this moment unactivated state still.All word line switches 312 and bit line switch 314 in memory module 1 and memory module 1# are in conducting state, and the word line switch in other each memory module then still keeps un-activation.Unit code translator 302 is activated the word line UWL2 of unit, and other word line then keeps the state of not being activated.Therefore, have only WL12 to be activated, and other each module word line still keep the state of not being activated.Transistor 110 in the memory cell MC12 is in conducting state.Therefore, the signal charge in the memory cell MC12 capacitor is read by module bit line BL12 and the bit line UBL2 of unit by module bit line switch 314.Meanwhile, BL12# is connected with UBL2# by the module bit line switch in the memory module 1#.But,, read on the UBL2# so there is no signal charge because WL12# still keeps the state of not being activated.Because the position of the bit line of memory module centering is the mirror image symmetry status, so its stray capacitance also equates.Signal charge in the memory cell MC12 produces a small potential difference (PD) between UBL2 and UBL2#.This potential difference signal is read out amplifier AMP2 detection and amplifies: be transferred into high-level data bus (not shown) then, and be used to memory cell MC12 is carried out Data Update.Equally, the content of memory cell MC11 is read out so big device AMP1 reads and upgrades; The content of memory cell Mci1 is read out amplifier AMPi and reads and upgrade.

During memory cell reading of data in module 1# on the WL12#,, just the same during memory cell reading of data on other operation and the WL12 in module 1 except unit code translator 302 will be activated the UWL2# rather than the UWL2 that is activated.If want each memory cell reading of data on the Wlij in the module I, unit code translator 302 should be by sharp UWLj, and module select signal BLKSELi should be activated simultaneously.The content of memory cell Mci1 is read out that amplifier AMP1 reads and by Data Update; The content that reads memory cell MCi2 is read out that amplifier AMP2 reads and by Data Update; ...; The content of memory cell MCii is read out that amplifier AMPi reads and by Data Update.

Each memory cell that is activated sensor amplifier that all needs to be activated, this is sure, otherwise the data that are stored in the memory cell will be lost.The difference of the present invention and prior art is, the sensor amplifier that is activated no longer need to be arranged at the bit line that connects the memory cell that is activated near, and the number of the memory cell that is activated is than the number much less of the storer that is activated among the existing DRAM.The multidimensional bit line structure allows us that the sensor amplifier peace that is activated is fallen in the position away from the memory cell that is activated, and can not bring the additional parasitic load to bit line.The distribution of sensor amplifier and peripheral circuit is irrelevant with the size of memory cell at interval.Therefore, high performance peripheral circuit might be designed, and area occupied can be obviously do not increased.

As can be seen, the multidimensional bit line structure of the present invention electric charge that to be " elder generation " store in the ground floor sensor amplifier is surveyed by the memory cell of clear work.The multidimensional data bus of existing multiple row group DRAM then is " back " electric charge of storing in the ground floor sensor amplifier detects the memory cell that is activated.In the existing multi-bank memory, each pairs of bit line needs a ground floor sensor amplifier, therefore can't solve the overstocked at interval problem that distributes.

Though the form with literal and accompanying drawing in the literary composition has provided some specific embodiments of the present invention, will be appreciated that in actual production technology and also can change to some extent and revise.For example, two bit lines of above-mentioned specific embodiment hypothesis bit line pairs lay respectively on two relative memory modules of position.Clearly, for the people who is proficient in this technology, the present invention also can support typical bit line shown in Figure 1 to structure, and promptly two of bit line centering bit lines are adjacent one another are.A bit be obviously in addition, above-mentioned two-dimentional bit line structure can be extended to three-dimensional or multidimensional bit line structure at an easy rate.For simplicity, Fig. 3 a shows a kind of two-dimentional bit line structure, but the number of plies of bit line structure is not limited to example.The best number of plies of bit line structure is by manufacturing process and design specification decision.

A bit be obviously in addition, saved bit line switch; The unit bit line does not need bit line switch just can be directly connected on the module bit line.Though bit line switch helps to reduce the bit line stray capacitance of each sensor amplifier induction, but, therefore on function, need not again the configuration bit wiretap because word line switch has been kept apart the memory cell in the memory cell in each memory module and other memory module.Though, there is no this restriction in the present invention when in last example, having disposed a sensor amplifier in every pair of memory module.We can dispose more than one sensor amplifier in each memory module, perhaps only dispose a sensor amplifier in the zone that many memory modules are formed.Because the design feature of multidimensional bit line, the present invention can remove the restriction arranged evenly between memory array and the peripheral circuit fully.

Fig. 3 b shows the memory array that 3 layers of bit line connect that has of the present invention.For simplicity, only show two pairs of bit line among the figure.The ground floor bit line is made by ground floor metal (M1), second layer bit line is made by second layer metal (M2), is then made by three-layer metal (M3) for the 3rd layer.Each memory module 350 comprise a plurality of and M1 bit line that hold in both hands to arrange to (BBLi, BBLi#), (BBLj, BBLj#).This memory array comprises a plurality of memory columns 360.The M1 bit line is connected in other memory module on the corresponding M1 bit line along same memory word row 360 by M2 bit line CBLi, CBLi#, CBLj, CBLj#.Bit line in each memory column uses metal 3 bit line M3Li, M3Li#, M3Lj, M3Lj# to be connected to the bit line in other memory column by bit line switch 362.Every bit lines in memory column 360 only needs a bit line switch 362 and a M3 bit line.Memory array one end disposed one group of sensor amplifier SA1 ..., Sai ... Saj.Each all is connected with a sensor amplifier to above-mentioned three-dimensional bit line network.For example, (BBLi, CBLi, M3Li), (BBLi#, CBLi#, M3Li#) etc. are connected with Sai, and (BBLi, CBLi, M3Li), (BBLi#, CBLi#, M3Li#) is connected with Saj.Because each memory module 350 all has the word line switch (not shown among Fig. 3 b) of oneself, be not activated so do not have above a memory module in any time network.Therefore, use a small amount of sensor amplifier just can support a large amount of memory cells, and do not violate each memory cell that is activated and to have a sensor amplifier that is activated to survey the requirement of its store charge.

Though the bit line structure among Fig. 3 b is the employed bit line structure of our actual product, for simplicity, we still discuss with the example that the two dimension of the simplification shown in Fig. 3 a bit line structure is used as hereinafter.

(a illustrates with the form of simplified block diagram in b) at Fig. 4 about the difference of device distribution area and power consumption between prior art and the present invention.Shown in Fig. 4 a is the contracted notation figure of the memory set (containing N pairs of bit line, each word line of M and 8 output terminals (N and M are integer)) in the conventional DRAM memory array 400.In Fig. 4 a, sensor amplifier is represented with long rectangle 402.Because a sensor amplifier supports that a bit line is right, the distribution of sensor amplifier is exactly the right distribution interval of bit line at interval, so that make them must be positioned at a long narrow rectangular area.The output of sensor amplifier can be chosen to 8 output terminals by output decoder 404 and traffic pilot 406.The distribution of output decoder 404 is also very narrow at interval.The distribution of each device is exactly the interval of a memory cell Cx at interval in the word-line decoder 410.During storage operation, be activated across word line 412 of whole memory set.The quantity of the memory transistor that is activated is N.All N sensor amplifier all is activated, and all N bit line in this memory set is to all charge or discharge with the operation of sensor amplifier.The zone that is activated in the whole memory set is expressed as the shadow region in Fig. 4 a.

Fig. 4 b is the contracted notation figure of a row storer in the DRAM memory array of the present invention.For simple by comparison, we suppose that the memory array among Fig. 4 b comprises and the memory cell of Fig. 4 a memory array equal number and the data output end of equal number.This memory set is divided into 4 units 450, and each unit comprises 8 pairs of memory modules 452.Every pair of memory module all has an amplifier 454.Each unit contains a unit word-line decoder 456.Fig. 3 a shows the detailed structure of memory unit.Unit selects code translator 460 to produce plurality of unit along word-line direction and selects signal XBLKSEL.Module selects code translator 462 can produce several row level module select signals YBLKSEL.When all being activated across the XBLKSEL of module and YBLKSEL, memory module 452 just is activated.What amplifier 454 zones were interior just can produce a local module select signal with door (AND) circuit.The output terminal of each amplifier all is arranged on row level bit line KBL, the KBL#, so that make I/O (IO) equipment 470 be positioned at the storer edge.For simplicity, only show a pair of row level bit line among Fig. 4 b.Hereinafter the details of other peripheral circuit will be discussed further.The distribution of the sensor amplifier 454 shown in Fig. 4 b is wide 8 times than shown in Fig. 4 a at interval.Peripheral circuit no longer needs spaced apart closely, so as we it can be designed not only fast, the area occupied but also little of speed.When storer is operated, in chosen unit 450, have only a memory module 452 and 8 sensor amplifiers 454 to be activated.Shown in the shadow region among Fig. 4 b is exactly the zone that is activated.This obviously much smaller than the conventional memory group shown in Fig. 4 a of zone that be activated by the clear zone of living.Therefore, the power consumption of storer of the present invention is more much smaller than the power consumption of the storer of prior art.

The computing formula of the bit line stray capacitance Cbp of the existing storer shown in Fig. 4 a is:

Cbp＝(M/2)*Cd+M*Cm1 (1)

In the formula: Cd is the distributed capacitance of a bit line contact, and Cm1 is the electric capacity of metal 1 in each unit memory cells bit line, and M is the quantity along memory cell on the bit line.Suppose two shared contacts of memory cell, the sum of contact just is M/2.

The computing formula of the bit line stray capacitance Cbp of the existing storer shown in Fig. 4 a is:

Cb＝(M/16)*Cd+(M/8)*Cm1+(8*Cd+N*Cm2) (2)

In the formula: Cm2 is the electric capacity of each storer metal 2 bit lines at interval on the unit bit line direction.Two (M/16) * Cd+ (M/8) * Cm1 is the electric capacity of this ground bit lines, and the length of this bit line is 1/8 of Fig. 4 a neutrality line length.Last two stray capacitances that (8*Cd+N*Cm2) is the unit bit line, this unit bit line contain 8 bit line switch contacts and N metal 2 bit line contact.Junction capacitance Cd is more a lot of greatly than the electric capacity of metal bit line.The metal 2 bit line capacitance Cm2 capacitor C m1 than metal 1 bit line usually are little a lot.Therefore, one of the present invention bit line stray capacitance Cb that sensor amplifier produced of expression is significantly less than Cbp in the formula (1,2).Bit line capacitance means that for a short time storage operation speed is fast, low in energy consumption, good reliability.Produce memory cell and do not need to use complex technology.In order to reduce total area occupied, can also make each sensor amplifier connect more multi-memory unit by the size that increases each memory module.

The shared total area of memory cell of two memory arrays shown in Fig. 4 a and Fig. 4 b is identical.Therefore, the different complete distribution by peripheral circuit of two memory array areas occupied causes.The available distribution of the output decoder of the storer shown in Fig. 4 b and sensor amplifier is available at interval 8 times that distribute of the storer shown in Fig. 4 a at interval.Be proficient in this technology the people be easy to find out that storer of the present invention is because it is at the distribution of the direction that is parallel to word line broad at interval, so it is along littler than the size of existing storer perpendicular to the size on the word-line direction.The present invention still needs same distribution code translator 460 at interval.In addition, each memory module 452 of the present invention all needs one group of word line switch 462.Because we can adopt the code translator of lower-order the reduction of load, thereby the area that is additionally taken by word line switch 462 can obviously not increased.

The sensor amplifier that the present invention uses is the same substantially with the typical sensor amplifier of prior art.Fig. 5 shows the synoptic diagram of the amplifier shown in Fig. 3 a.When sensor amplifier enabling signal SAEN was activated, transistor MP11, MP12, MN11 and MN12 just constituted a slight signal perception circuit, and this circuit is detectable to go out the unit bit line to the small electric potential difference on UBL and the UBL#.When a row levels word line KWL is activated, transmit lock transistor MN14 will the bit line UBL of unit of transfer with row grade bit line KBL between signal.When row level word line KWL was activated, transmission gate electrode transistor MN13 will transmit signal between bit line UBL# of unit and row level bit line KBL#.When sensor amplifier was not activated, MN17 was used to compensate the voltage on UBL and the UBL#.The principle of work of above-mentioned sensor amplifier is common to all in reservoir designs circle, just no longer has been described in further detail here.

Fig. 6 is the block scheme of the input and output shown in Fig. 4 b (IO) equipment 470.Row level bit line is connected with row level sensor amplifier 650 by row level bit line switch 651 with KBL# to KBL.This sensor amplifier 650 is just the same with sensor amplifier shown in Figure 5; Its enabling signal is KSAEN.When enabling signal MREAD was activated, KBL switch 651 just was switched on, and can make bit line and sensor amplifier isolated when MREAD is not activated.Reservoir designs circle knows that all the effect of this bit line switch 651 is the operating speeds that improve sensor amplifier.The output terminal SOUT of sensor amplifier is connected with bug patch code (ECC) circuit 652.This ECC circuit is that industry is known, so we do not do further discussion.The output terminal EOUT of ECC circuit is connected to the input end of output driver 665.When output driver 665 is started by signal READOUT, it just with data-driven to the external impact damper.When carrying out write operation, we with in the impact damper data deposit in the storage register 662.The output terminal UDATA storer of storage register writes driver 664 with a storer and is connected.Storer writes driver 664 and is subjected to the UPDATE signal controlling, drives the data on KBL and the KBL# when storer is carried out the Data Update operation.

What Fig. 7 (a-c) illustrated is the oscillogram of the minimum detectable signal of previously described storer.

Fig. 7 a shows storer at the sequential chart that carries out operation minimum detectable signal when (being called " read cycle ") from the memory cell reading of data.At first, in time T 1, module selects letter BLKSEL to be activated.When XBLKSEL and YBLKSEL all are in when being activated state, signal BLKSEL just is activated.No matter when as long as BLKSEL is activated, the pre-charge circuit of selected memory module just can be turned off, and the pre-charge circuit of all sensor amplifiers of selected memory unit also all can turn-off.Because the information of relevant BLKSEL signal is unnecessary, so the waveform of precharging signal and row level module select signal XBLKSEL, YBLKSEL is not shown among the figure.After signal BLKSEL was activated, 2 module word line WL were activated in time T.In case module word line WL is activated, just can begin to produce the small electric potential difference to BL, BL# and unit bit line on to UBL, UBL# at the module bit line.These unit bit lines on produce enough big potential difference (PD) after, SAVCC becomes VCC, SAVSS becomes VSS, thereby the sensor amplifier of selected memory unit is activated.In case the unit sensor amplifier is activated in time T 3, just begin to increase the bit line current potential.Then, be activated at time T 4 row level word line KWL; In a single day KWL is activated, and will send the potential difference (PD) on UBL and the UBL# to the row bit line to KBL and KBL# between time T 4 and the T5.Because the electric charge between row bit line and the unit bit line is shared effect, the voltage of UBL and UBL# can at first be reduced to PCGV; The unit sensor amplifier finally can overcome electric charge and share effect, and amplifies its potential difference (PD).In time T 5, row word line KWL is in off state, and KSAVCC is risen to VCC, and KSAVSS rises to VSS, and row level sensor amplifier 750 is activated.Row level sensor amplifier 750 can be enlarged into the total power supply voltage with the potential difference (PD) on KBL and the KBL#.Meanwhile, unit level sensor amplifier also can rise to the total power supply voltage with UBL and UBL#.Because we come selected memory cell is carried out Data Update by the unit's of dependence level sensor amplifier, so before time T 6 was turn-offed word line, we need provide a time margin to be able to abundant answer to guarantee the signal charge in these memory cells.After word line was turned off, sensor amplifier can be turned off in time T 7, was closed at time T 8 module select signal BLKSEL then.In case signal BLKSEL is turned off, storer just is configured to pre-charge state, and at this moment all bit-line voltages all are returned to PCGV.Because the load of bit lines at different levels is all very little, so the precharge time of storer of the present invention is than existing storer much shorter.In time T 9, all signals all have been returned to pre-charge state fully, and storer has been ready for next operation.

Shown in Fig. 7 b is to be used for memory cell is carried out the sequential chart of minimum detectable signal of the storage operation (being called " Data Update cycle ") of Data Update.Except not needing that data tape is fallen in lines the level, Data Update cycle and read cycle are closely similar.Whole Data Update is in the cycle, and all row level signal KWL, KSAVCC, KSAVSS, KBL and KBL# still keep the state of not being activated.In time T 11, module select signal BLKSEL is in state of activation, and then in time T 12, word line WL is activated.On module grade and the grade bit line BL of unit, BL#, UBL and UBL#, begin to produce potential difference (PD).In time T 13, sensor amplifier is activated.This sensor amplifier amplifies fast and the driving bit line reaches the total power supply voltage.When the electric charge in the selected memory cell is replied fully, just can turn-off word line WL in time T 14, turn-off module select signal BLKSEL at T15 then.In time T 16, all signals all are returned to pre-charge state, and storer has been ready for next operation.With Fig. 7 b and Fig. 7 a relatively, be easy to find out, because no longer need to be activated KBL and KBL#, so the time of required time ratio read cycle of Data Update cycle is short.

Shown in Fig. 7 c is the sequential chart of (being called " write cycle ") minimum detectable signal when storer is carried out operation with new data write store unit.In time T 21, module select signal BLKSEL and row level word line KWL are activated.Meanwhile, new data are written into row level bit line KBL and KBL#.Then, be sent to more rudimentary bit line UBL, UBL#, BL and BL# again.Storer writes driver 764 and has stronger driving force, so as can be fast with bit-line drive to needed value.On time T 22, can the unit's of being activated level sensor amplifier to assist write operation.In case the electric charge complete data in the memory cell upgrades, and will turn-off word line WL and KWL on time T 23.At T24, module select signal BLKSEL is turned off then.In time T 25, storer has reverted back to pre-charge state fully, has been ready for next time memory operation.With Fig. 7 c and Fig. 7 a relatively, because storer writes the strong driving force of driver 764, so carry out required time write cycle than short many of to carry out read cycle required time.

Shown in Fig. 7 a, read operation is than writing or the slow reason of Data Update operation is that because reply signal charge in the selected memory cell fully up to unit level sensor amplifier, read operation just can be finished.From the angle of external user, because the process that data are sent to external impact damper is carried out simultaneously, so the required overall performance that can't influence memory read operations extra time of Data Update storer from row level circuit.Therefore, external user is that fundamental sensation does not go out the Data Update time.Unique external user that allows is felt this excessive data effect of update time, is just in time with the request of read cycle at one time situation to take place when the predetermined Data Update cycle.Storer can not be carried out Data Update cycle and the read cycle on the different addresses simultaneously, so one of them request must be waited for.Therefore the external control logic just must be handled the situation of this resource contention.For the storer with ECC support, data write operation always begins with memory read operations, writes operation so the problems referred to above are present in storer too.For compatible fully with SRAM, we must allow external user can not discover the internal storage Data Update cycle fully.As long as change IO circuit shown in Figure 8, and change sequential chart control shown in Figure 9 and just can reach this point.

IO circuit in Fig. 8 except two extra traffic pilots 845,860 are arranged, almost with Fig. 6 in the striking resemblances of IO circuit.The output terminal EOUT of ECC circuit is connected to the input end of bypass traffic pilot 854.When read cycle, conform to the position of the storage register 662 interior data that store if read memory location, bypass traffic pilot 854 is selected the output terminal of Storage Registers 662.Otherwise bypass traffic pilot 854 is selected the output terminal of ECC circuit, and sends memory output signal to output driver 665.When carrying out a write operation, store the input that traffic pilot 860 is selected external impact damper, and when carrying out read operation, then the selection memory data of reading.This structure allows us " to hide " a Data Update cycle in normal memory operation, and this also can improve the speed of normal read operation.After using circuit shown in Figure 8, the latest data of previous storage operation will be stored in the Storage Register 662.If in the time of will carrying out new storage operation, we had been bound to check whether data are stored in the Storage Register before the memory array reading of data.If desired data have been stored in the Storage Register,, needed only directly in the Storage Register reading of data just without the execute store operation.When reading new data set from memory array, the data that storage operation finishes to be positioned at present the store buffer district write back to memory array and are bound to carry out the data update cycle before.Because we always will read the result with each storer and write Storage Register, so just do not need immediate data to upgrade selected memory cell.This configuration has been arranged, and we just can stop read operation before unit level sensor amplifier will be activated the memory cell data renewal.Therefore, unit level circuit can carry out the Data Update cycle when storer is sent to external impact damper with reading of data.This structure has been eliminated conflicting between Data Update cycle and the normal memory operation, and its principle of operation will utilize the oscillogram in Fig. 9 to be described further.

Fig. 9 shows when storage operation and Data Update running time overlapping (to different addresses or identical memory module) and the bad situation when needing from the store buffer district new data more simultaneously.Under this bad situation, for fear of the complicacy that the intensification system supports, Data Update cycle and memory updating cycle all must " hide " in memory read operations.In other words, we must not make external user under the perceptible time, carry out this two operating cycles simultaneously.

At time T r1 shown in Figure 9, in order to carry out read operation, module select signal BLKSEL is activated.At time T r2, word line WL is activated, and then, at time T r3, the unit sensor amplifier is activated.At time T r4, the word line KWL of unit is activated, and then, at time T r5, the unit sensor amplifier is activated.Up to time T r5, the read cycle shown in storage operation and waveform and Fig. 8 a is in full accord.At time T r5, it is different that both operate beginning, and we can select module signal BLKSEL, word line WL, KWL and unit level sensor amplifier to turn-off at Tr5 simultaneously, need not to wait for that memory data is fully amplified.Memory modules is deposited Tf1 in the time and is replied to pre-charge state fast, is ready for next operation.During this period, unit level sensor amplifier do not have time enough will more rudimentary bit line BL, the signal in BL#, UBL and the UBL# amplifies fully.Those memory cells that have been activated will no longer store raw data, and this will be fare-you-well, because by following operation, correct data can be deposited in the Storage Register 622.At time T f1, a row levels sensor amplifier can induce data, and correct data will deposit in the Storage Register 622 and be updated to when next storage operation in these selected storeies.Therefore, even the store charge in the memory cell is neutralized at this moment, data can not lost yet.Meanwhile, when we waited for that data that row levels circuit will newly read are sent to external circuit, unit level and module level memory circuitry just can be used to carry out the Data Update operation.This concealed Data Update cycle can betide on any storage address.When the Data Update cycle occurs in the same module that we have just read bad sequential situation will take place, Fig. 9 shows the sequential chart of unfavorable condition.At time T f1, BLKSEL is activated to carry out the Data Update cycle.To time T f5, the waveform Data Update cycle the same with waveform in Fig. 8 b will be carried out from time T f1.At time T w1, memory unit has been ready for new operation, and row level read operation is also finished.At this moment, IO unit 720 is carrying out ECC and is revising, and data are sent to impact damper.Meanwhile, row level data resource all is in upstate, so we can utilize this chance to carry out write cycle, the legacy data in the Storage Register 762 is upgraded back in the memory array.Waveform and the waveform in Fig. 7 c from time T w1 to Tw5 in Fig. 9 are just the same, when storage operation finishes, the latest data that can will read from storer deposits Storage Register 662 in, deposit memory array in after former data are updated, so just fulfil the Data Update request, and finished the external memory storage operation requests.

We still need to note down the data that are stored in each memory cell that has been activated, and this is sure, otherwise data will be lost.The difference of process is that data temporarily are stored in the Storage Register between above-mentioned storage access process and typical DRAM storage access, upgrades the memory cell that has been activated so that we need not immediate data.The bandwidth that this structure utilization can be used arrives next storage operation process with the Data Update operating delay, so that the hiding data update cycle is improved system performance.

Said structure is different with composite memory, because (1) the present invention has simplified the sequential control of DRAM read cycle, and the SRAM of composite memory does not simplify the operation of DRAM; (2) system of the present invention control and device performance are all identical with storage operation, with the data independence of whether hitting in the Storage Register, and when storage operation lost the control of cache memory array, the performance of cache memory and control had marked difference; (3) when SRAM had higher cache hit rate with bigger temporary storage, composite memory had preferable performance, and the quality of performance of the present invention and hit rate are irrelevant; (4) Storage Register can't increase the use in space significantly, and SRAM then can take specific distribution area on the chip of composite memory.Therefore, above the structure of described storer is different fully with principle of operation and composite memory.

From literary composition as can be known, can obtain following advantage according to the present invention:

(1) solved the overstocked at interval problem that distributes fully because many bit lines are to all sharing identical sensor amplifier, each peripheral circuit can with distribution be the manyfold at storer interval at interval.Therefore, just can make sensor amplifier and the peripheral circuit that has high susceptibility for electric symmetry and high distribution efficiency.

(2) bit-line load born of sensor amplifier reduces widely, thereby can significantly improve performance.

(3) a large amount of memory cells can be appended to each sensor amplifier, to reduce total area occupied of device.

(4) innovative design of code translator has significantly reduced the size of code translator, but can not influence its driving force, and the load on each word line also can significantly reduce.This design of encoder has also reduced area occupied and has improved the performance of device.

(5) change of storage access process can make us that storage operation is next time arrived in the Data Update operating delay, so external user just can't be discovered internal data renewal operation.

(6) in each storage operation, the device that need be activated is those devices that must be activated.This wastes power supply a little.But the present invention than the storer of prior art want power saving many.

Storage arrangement of the present invention is put into serial production, and uses 0.6 micron technology can produce the memory array that includes 1,000,000 memory cells, and we can realize the access time of 4ns, and this is than fast 10 times of the storage arrangement that has same storage volume now.

Figure 10 shows the representative instance of a prior art code translator, and each code translator branch comprises the AND gate electrode 1101 of a control code translator 03-0 output.Two groups of input select signals that repel mutually (G0, G0NN) and (G1 G1NN) is connected to the input end of these AND, shown in Figure 10.So, the more than one decoder output 03-0 that can not be activated at any time.

Figure 11 (a) is the synoptic diagram of single-transistor code translator, and each code translator branch of this code translator only uses a n channel transistor M3 to M0.The source electrode of each transistor M3 to M0 all is connected to a word line WL3 to WL0 of memory set.One group of drain electrode of repelling mutually selects signal DSEL1, DSEL0 all to be connected to the drain electrode of these transistors M3 to M0, one group of gate electrode of repelling mutually selects signal GSEL1 and GSEL0 then to be connected to the gate electrode of these transistors M3 to M0, shown in Figure 11 (a).In this configuration, only when DSEL1 and GSEL1 are activated WL3 just can be activated, only when DSEL1 and GSEL0 are activated WL2 just can be activated, only when DSEL0 and GSEL1 are activated WL1 just can be activated and only when DSEL0 and GSEL0 are activated WL0 just can be activated.

Therefore, the circuit in Figure 11 (a) satisfies the required function of storer word line code translator.Typical C MOS AND gate electrode comprises 3 p channel transistors and 3 n channel transistors.Code translator in Figure 12 (a) only uses a transistor for the output of each code translator, and is apparent, and the code translator in Figure 11 (a) will be much smaller than the code translator in Figure 10.But the monocrystal code translator in Figure 11 (a) needs the special sequential control shown in the following example.

What Figure 11 (b) illustrated is, the sequential chart of the input signal of one of the word line WL0 that is used to be activated.Before time T 0, there is no the decoding activity, all gate electrodes select signal GSEL1, GSEL0 all must be in power supply supply voltage Vcc state, and all drain electrodes select signal DSEL1, DSEL0 all must be in ground voltage Vss state, are activated by noise signal or electric leakage signal otherwise just have the word line accident.If will activate a word line WL0, we must turn-off all gate electrodes in time T 0 and select signal GSEL1, GSEL0, activate a gate electrode at T1 then and select signal GSEL0 and a drain electrode to select signal DSEL0.In order to turn-off code translator, select signal GSEL1 and GSEL0 before T3 is activated, must at first turn-off DSEL0 once more at T2 at all gate electrodes.Above-mentioned control procedure is necessary, in case unexpected activate selected word line.As long as we activate a word line, because involve all inputs, so above-mentioned sequential control order is quite complicated.Above-mentioned code translator is the simplified example of 4 output decoders, and a real memory decoder must be controlled thousands of word lines.The power supply that this complicated control procedure consumes is appreciable for a real memory decoder.Another problem of the interior code translator of Figure 11 (a) also shows in Figure 11 (b).Because the bulk effect of n channel transistor M0, the voltage of the word line WL0 that has been activated can be than the also low Vbd that goes up of power supply supply voltage Vcc, shown in Figure 11 (b).This voltage drop is a big problem of DRAM code translator, because can reduce the signal charge that is stored in the DRAM memory cell like this.

Figure 12 (a) is the synoptic diagram of code translator of the present invention.Unique difference of the code translator shown in Figure 11 (a) and Figure 12 (a) is that the code translator shown in Figure 12 (a) has replaced enhancement transistor M3 to M0 with depletion mode transistor D3 to D0.The critical voltage of these depletion mode transistors D3 to D0 is controlled at and is less than about greatly in power supply supply voltage Vss-0.2 volt (or approximately be typical enhancement transistor critical voltage the 1/3) scope.

What Figure 12 (b) illustrated is the sequential chart of input signal, and the effect of this signal is a word line WL0 who selects the interior depletion type monocrystal shown in Figure 12 (a).Before time T 0, all gate electrodes select signal GSEL1, GSEL0 and all drain electrodes to select signal DSEL1, DSEL0 all to be in the state of ground voltage Vss.Different with the enhancement mode monocrystal code translator in Figure 11 (a) is when code translator is in waiting status, can set all control signal GSEL1, GSEL0 for Vss.Because depletion mode transistor D3 to D0 can partly be activated during for Vss at its gate electrode voltage, so noise signal or little electric leakage signal can't activate word line W) WL3-WL0.If will activate a word line WL0, we no longer need to turn-off all gate electrodes and select signal, only need shown in Figure 12 (b), activate a gate electrode and select signal GSEL0 and a drain electrode to select signal DSEL0 to get final product.If will turn-off code translator, as long as we turn-off GSEL0 and DSEL0 shown in Figure 12 (b).This control procedure wants simple many compared with the control procedure shown in Figure 11 (b).And the critical voltage of transistor M0 is lower than zero because be activated, does not translate the pressure drop that causes because of bulk effect so also do not have on selected word line.Depletion type single-transistor code translator in Figure 12 (a) is the same little with enhancement mode single-transistor code translator in Figure 11 (a) aspect area, but its power consumption is less.Unique problem is when the shutoff door electrode is selected signal and activate drain electrode to select signal, has some word lines and partly is activated, the WL1 shown in Figure 12 (b).When the voltage Vpt in the memory cell was lower than the critical voltage of selecting gate electrode, this word line partly was activated with regard to the problem that is not function aspects, but might cause the problem of current potential electric charge reservation owing to subcritical leakage current.A solution of this problem is exactly a negative voltage to be imported all gate electrodes that have been turned off in time T 0 to select on the signal, shown in Figure 12 (c).This is added in drain electrode and selects a small amount of negative voltage on the signal to guarantee that depletion type gate electrode transistor D1 maintains non-conductive state, and word line WL1 just can partly not be activated like this.

The diagram and the character introduction of the specific embodiment by the single-transistor code translator, the insider can recognize that just can also carry out other revises and change, for example: the n channel transistor of example above available p channel transistor or depletion type p channel transistor replace.

Recognize that from aforementioned the shared area of single-transistor code translator of the present invention is much smaller than the shared area of the CMOS code translator of prior art.Therefore large-scale memory array can be divided into some little modules that each module contains own code translator district, and can significantly not increase the total area.When memory array was distinguished into some little modules, we had just no longer needed the needed jumbo capacitor in DRAM unit of prior art.Therefore, just can use the standard logic technology to make the DRAM memory cell.

Figure 13 shows an example with the DRAM memory cell of logic technology manufacturing.This memory cell 1400 comprises one and selects transistor 1402 and a storage transistor 1404.The gate electrode of storage transistor 1404 is biased to full power supply supply voltage Vcc, so that make it be equivalent to a capacitor.The drain electrode of storage transistor 1404 is connected to the source electrode of selecting transistor 1402, selects the gate electrode of transistor 1402 to be connected to word line WL, and selects transistor drain to be connected to bit line BL.Use the memory construction of this memory cell 1400 and the present invention and the interior announcement of patent application case formerly, just can successfully produce commercial memory product.The major advantage of logical storage units 1400 is to use the standard logic technology to make this storer.The memory product that is obtained can reach unprecedented high-performance.Because use two transistors to replace a transistor and a capacitor when making a memory cell, so the area of logical storage units 1400 is greater than the area of the DRAM unit of prior art.Therefore, just may use with the similar manufacturing technology of logic technology and make one-transistor memory cells.

Therefore, to 13, will disclose a kind of semiconductor memory system 300 according to Fig. 3 a to 4b and Figure 12 (a), its available a plurality of cell datas are upgraded sensor amplifiers (SA) and are operated.Storage arrangement 300 comprises a plurality of along first bit line direction, with the memory cell array of parallel mode along the first direction first order bit line (for example bit line BLni of position i module n) of first direction (for example horizontal direction) arrangement.This memory cell array further comprises a plurality of word line WL that intersect with first direction first order bit line.This memory cell array further comprises a plurality of memory cells, and these memory cells all are coupled between one of word line of one of first direction first order bit line (for example bit line BLni of position i module n) along first bit line direction and store data separately.This storage arrangement further comprise a plurality of along a plurality of different directions (for example along vertical direction, wherein have at least a direction different with first direction) different directions first order bit line, as multimode or the bit line i of unit (seeing also Fig. 3 b) such as UBLi, BBLi, CBLi, i=1 wherein, 2,3 ... I, wherein each first direction first order bit line is all by different directions first order bit line or be connected directly to cell data and upgrade one of sensor amplifier (SA).A concrete most preferred embodiment by, be used for arranging different directions first order bit line (for example multimode bit line i (seeing also Fig. 3 b) of UBLi, BBLi, CBLi etc.) (i=1 wherein, 2,3, ... one of different directions I), as vertical direction perpendicular to first direction (for example being used to arrange the horizontal direction of first direction first order bit line).In the most preferred embodiment shown in Fig. 4 b, storage arrangement 300 also comprises the bit line switch that is connected between the first order bit line and is arranged in different directions.Semiconductor memory system also comprises one and is used for producing the code translator 302 that activation signal activates one of word line WL, this code translator 302 also comprises a plurality of drain electrode selection wires (for example DSEL0 and DSEL1 etc.), and each all has the drain electrode that can receive a plurality of mutual repulsions and selects one of signal.This code translator 302 also comprises a plurality of gate electrode selection wires (for example GSEL0, GSEL1 etc.), and each all has the gate electrode that can receive a plurality of mutual repulsions and selects one of signal.This code translator 302 also comprises a plurality of transistors, for example D0, D1 or M0, M1 etc., each transistor all comprises a pair of drain electrode that is connected to one of a plurality of drain electrode incoming lines (for example DSEL0, DSEL1 or the like), selects one of signal so that receive the drain electrode of the mutual repulsion that therefore forms.Each transistor also comprises a pair of gate electrode that is connected to one of a plurality of gate electrode incoming lines (for example GSEL0, GSEL1 etc.), is used for the gate electrode of the mutual repulsion that receives so form to select one of signal.Each transistor also comprises a source electrode, this source electrode is connected to an output signal line, be used to provide activation signal and give one of word line WL, this word line depends on drain electrode selection signal DSEL0, the DSEL1 etc. of mutual repulsion, and gate electrode selection signal GSEL0, the GSEL1 etc. that depend on mutual repulsion.In most preferred embodiment, each transistor all is an enhancement transistor, and in other most preferred embodiment, each transistor all is a depletion mode transistor.

Further, to 13, also disclose a kind of method of setting semiconductor memory system, can upgrade sensor amplifiers (SA) with a plurality of cell datas and operate according to Fig. 3 a to 4b and Figure 12 (a).This method comprises following operation steps: (a) dispose a plurality of first direction first order bit lines in a parallel manner along first direction; (b) a plurality of word lines that intersect with first direction first order bit line of configuration; (c) be coupled each first direction first order bit line and wherein be used for memory cell between one of the word line of store data; (d) along a plurality of different directions first order bit lines of a plurality of different directions (wherein have at least a direction different) configuration with first direction; (e) with each first direction first order bit line by different directions first order bit line or be connected directly to cell data and upgrade sensor amplifier; (f) each word line WL is connected to code translator 302, the signal that is activated that is used for receiving so forming activates one of word line WL; (g) form code translator with a plurality of transistors, wherein each transistor comprises a drain electrode, a gate electrode and one source pole; (h) selection wire that will drain is connected to each transistor drain, and the gate electrode selection wire is connected to each transistorized gate electrode; (i) one of signal is selected in the drain electrode that receives a plurality of mutual repulsions with each drain electrode selection wire, and uses the gate electrode that each gate electrode selection wire receives a plurality of mutual repulsions and select one of signal; And (j) with each the transistorized source electrode generation output signal in a plurality of transistors, this source electrode depends on the gate electrode selection signal that the drain electrode of mutual repulsion is selected signal and repelled mutually, to provide the signal that is activated to each bar word line.

According to Figure 13, the present invention has further disclosed a kind of dynamic RAM (DRAM) unit that is coupled to word line and bit line.This DRAM memory cell comprises one and selects transistor 1402, and this transistor comprises the drain electrode and the gate electrode that is connected to word line WL that are connected to bit line BL.This memory cell also comprises a storage transistor 1404, this transistor comprises one and is connected to drain electrode and gate electrode that is connected to power supply supply voltage Vcc of selecting transistor 1402 source electrodes, and this storage transistor 1404 is used as capacitor of depositing binary digit of storage here.Generally speaking, the present invention further discloses a kind of memory cell that is coupled to word line and bit line.This memory cell comprises a storage transistor, and this transistor is connected to word line and bit line by being used for the selecting arrangement of selective activation memory cell.And storage transistor also comprises a gate electrode, and this gate electrode is biased to the power supply supply voltage, is stored binary digit as a capacitor.

Being to use that Figure 14 (a-f) and Figure 15 (a-c) illustrate is similar to the step that the standard logic manufacturing technology is made high-density storage.First step is to determine active region 1502 and generate insulation field oxide 1504 to isolate these active regions, shown in interior sectional view of Figure 14 (a) and the interior vertical view of Figure 15 (a).This step is the same with any IC standard manufacturing technology.Next procedure is to utilize radome 1506 to determine the position of the trench type capacitor shown in Figure 14 (b).Adopt the selectivity plasma etching process, on the opening that field oxide 1504 and raceway groove radome 1506 are determined, etch raceway groove 1510, shown in interior sectional view of Figure 14 (a) and the interior vertical view of Figure 15 (a).Because three edges of raceway groove 1510 all determine that by field oxide so this is the process of a self-aligned, 1506 need of raceway groove radome determine that a trench edges gets final product.After the aforesaid operations step, all following operation stepss have been the manufacturing technology steps of typical standard logic technology all just.At first, on active region 1502 surfaces, form thin dielectric layer 1511, comprise the surface of the raceway groove 1510 shown in Figure 14 (d).Next procedure is that the poly-silicon 1512 of deposition is to fill up raceway groove 1510 and to cover whole silicon wafer, shown in Figure 14 (e).Then, gather silicon etch process, determine the position of the electrode 1524 of transistor gate electrode 1522 and trench type capacitor with gathering radome 1520, shown in Figure 14 (f).Figure 15 (c) shows the vertical view of memory unit, and Figure 15 (g) then shows its sectional view.Trench type capacitor 1510 fills up poly-silicon, and all trench type capacitors 1510 all have an electrode 1602 to be connected to power supply supply voltage Vcc by poly-silicon, and other electrode of trench type capacitor then is connected to the source electrode of selecting transistor 1604.Poly-silicon word line 1606 determines to select transistorized gate electrode, and selects transistor drain to be connected to metal bit line by diffused contact 1608.

By above as can be known, can obtain following advantage according to the present invention:

(1) except covering step and plasma etch step, to be useful on the step of making the DRAM unit all be existing standard logic process step.Compare with existing in-line memory manufacturing technology, the present invention surpasses 30% to the simplification degree of its manufacturing technology.

(2) method of determining the size of trench type capacitor is the self-aligned method, and field oxide has been determined three edges of trench type capacitor, has only one to be determined by radome.This self-aligned method allows us that memory unit area is reduced to minimum degree.

Now having worked out another kind utilizes logic technology to make the technology of self-aligned trench type capacitor.First step be according to shown in Figure 16 (a) sectional view the standard logic technology make the CMOS transistor.Now, can produce MOS transistor fully.Poly-silicon gate electrode 1702 by the oxide covering protection, then, and deposition raceway groove radome 1706.This raceway groove radome 1706 is used for protecting us not need to excavate the zone of trench type capacitor, because four edges in this zone have all been determined well, so do not need to determine the size of trench type capacitor at this.Here will determine three edges with field oxide 1710 in the mode identical with previous processing step, its 4th edge then determined by the oxide on the transistor gate electrode 1704, so just finished the self-aligned program.Therefore, following selectivity plasma etch step can be utilized the best area of trench type capacitor, shown in Figure 16 (b).Before whole surface is covered by the second strata silicon 1714, on the surface of raceway groove 1712, form thin dielectric layer, shown in Figure 16 (c).By Figure 16 (a) the photoresistance 1716 determined of the identical radome that uses determined the size (the interior use of the polarity of the photoresistance that uses and Figure 16 (c) is opposite in Figure 16 (a)) of the second strata silicon 1716.Then, the electrode 1720 of the etching second strata silicon to form these trench type capacitors 1722.Figure 17 shows the DRAM vertical view of being made by above-mentioned steps.The first strata silicon is determined word line 1802, the second strata silicon and then is used for filling up trench type capacitor 1722, and an electrode 1720 of all trench type capacitors is connected to Vcc.

Above-mentioned processing step more complicated than shown in Figure 14 (a-g), the characteristics of four limit openings of trench type capacitor make it have the advantage of complete self-aligned.Therefore, the utilization of area of silicon wafer can be optimized fully.By the specific embodiments of the invention with diagram and text description, the insider knows can have other to revise and change.For example, can be at the insulation course that forms in other processing step rather than the formation step in the trench type capacitor at the gate electrode oxide.The definite order of processing step also can change, so that simplify technology.

The apex electrode (1602) of the trench type capacitor (1510) of the memory cell of figure shown in (14) must be connected to a voltage, and this voltage should be higher than the critical voltage (Vt) of bottom electrode voltage at least, so that allow the regional conducting of insulation course (1511) bottom.Similarly, the apex electrode (1702) of the trench type capacitor of the memory cell shown in the figure (16) must be connected to a voltage, and this voltage should be higher than the critical voltage Vt of bottom electrode voltage at least.In typical case, these apex electrodes (1602,1702) all are connected to power supply supply voltage Vcc.If deposition diffusion layer (1805) just can be removed this restriction near trench type capacitor (1802), shown in the interior sectional view of Figure 18 (a).The drain electrode of this diffusion layer (1805), word line transistors (1606) and apex electrode (1602) the identical adulterant that all mixes.Therefore, the bottom electrode of trench type capacitor (1801) always is in conducting state, has so just removed the restriction to electrode voltage.The another kind that sectional view in Figure 18 (b) shows apparatus structure changes, and in this structure, transistor (1811) replaces field oxide and isolates two adjacent trench type capacitors (1821,1823).The gate electrode (1813) of this isolated transistor (1811) is connected to ground voltage Vss, to separate adjacent trench type capacitor (1821,1823).Therefore transistor (1811,1815) is determined trench type capacitor (1821,1823) but not the two edges of field oxide regions, and this helps to reduce the size of memory cell.

In above-mentioned example, for simplicity, the shape of memory cell is depicted as an angle of 90 degrees.In fact, memory cell can be depicted as the multi-angle shape as the memory unit of overlooking shown in Figure 19 usually.Trench type capacitor (1901) will be placed on the place that becomes miter angle with contact (1903), and word line (1907) also is placed to miter angle with diffusion zone (1905).Because the area of trench type capacitor (1901) determined by field oxide and transistor edge, so its shape might not be the shown rectangular shape of example in Figure 19.

The word line transistors of memory cell of the present invention (1402) has the characteristic identical with peripheral circuit and logical circuit, and is interior at one time the manufacturing.The word line transistors of the DRAM of prior art is different from logic transistor usually.In order to hold the higher word line voltage that the word line boost pressure circuit imports, the thickness (Tox) of the gate electrode oxide of the word line transistors of prior art is bigger than the thickness of logic transistor.In order to reduce leakage current, the critical voltage of the word line transistors of prior art (Vt) is than higher.Table 1 is listed the transistor characteristic of typical 0.35um DRAM technology, covers the step except adding for the Vt that increases word line transistors in this example, and the manufacturing step of word line transistors and logic transistor is identical.Word line transistors has higher Vt (example in the table 1 is 1.1 volts), can shorten the length (Lmin) of minimum channel like this, is 0.35um in this example, and does not have the problem of electric leakage.Logic transistor has lower Vt (this example is 0.7 volt), but its Lmin is bigger.On the other hand, the logic transistor of typical DRAM fabrication process is equivalent to the logic transistor of 0.5um explained hereafter, rather than is equivalent to the logic transistor of 0.35um explained hereafter.In other words, the performance of the logic transistor of DRAM explained hereafter is lower than the logic transistor that typical logic technology is produced.A kind of high performance logic transistor of making on same chip is to use complicated processing step to make different types of transistor with the transistorized method of low electric leakage DRAM.Table 2 shows the transistor characteristic in the example of the technology of making this complicated in-line memory.This technology contain high Vt and thick-oxide word line, be equipped with thick-oxide and the high voltage transistor of long raceway groove and the logic transistor of low Vt and thin-oxide.This technology is very complicated, and manufacturing cost is very high.

The word line transistors of the DRAM of table 1 prior art and the transistor characteristic of logic transistor.

	Tox	Vt (volt)	Lmin (micron)
				Word line transistors	100	1.1	0.35
Logic transistor	100	0.7	0.5

The word line transistors of the embedded DRAM of table 2. prior art and logic transistor transistor characteristic.

	Tox	Vt (volt)	Lmin (micron)
				Word line transistors	100	1.1	0.35

High voltage transistor	100	0.7	0.5
				Logic transistor	70	0.7	0.35

Therefore, disclose a kind of DRAM that on base material, supports (dynamic RAM) cell array in the present invention.The DRAM cell array comprises a plurality of memory cells, and each unit all has one to select transistor, and wherein each is selected transistor to have one and selects the transistor gate electrode.Also comprise a peripheral logical circuit that contains logic transistor outside the DRAM, wherein each logic transistor has a logic transistor gate electrode.Select the transistor gate electrode to have identical thickness substantially with the logical circuit gate electrode, and each each logic transistor with peripheral logical circuit of logic transistor critical voltage of selection transistor AND gate with memory cell of selecting the transistor critical voltage also has same thickness, wherein selects the transistor critical voltage identical with the logic transistor critical voltage substantially.In most preferred embodiment, each memory cell also contains channel transistor.In another most preferred embodiment, the DRAM cell array also comprises the active region of being determined and being isolated by the field oxide layer edge that is deposited on the base material, and wherein each trench type capacitor all is deposited in the active region and with the field oxide layer edge and carries out self-aligned.In another most preferred embodiment, the DRAM cell array also comprises by the determined active region in field oxide layer edge that is deposited on the base material.Each trench type capacitor all is deposited in the active region, and carries out self-aligned with the edge of field oxide layer edge and selection transistor gate electrode.In another most preferred embodiment, the DRAM cell array also comprises error code inspection (ECC) and the correcting device that is connected to memory cell, is used for checking and revising the read error of all storeies in the critical error detector correction time.

In sum, the present invention has disclosed a kind of manufacturing and has had the method for selecting transistorized embedded DRAM cell array, wherein this DRAM cell array and high performance logic circuits coexist as on the same base material, this method comprises step (a) and adopts equal form to select transistorized gate electrode and high performance logic circuits gate electrode making step, wherein selects transistor gate anodizing thing to have identical thickness substantially with logical circuit gate electrode oxide; (b) adopt the embedding step of selecting the transistor AND gate logic transistor identical substantially forming, wherein select the transistor AND gate logic transistor to have identical substantially critical voltage.In most preferred embodiment, the step that this method also comprises a capacitive character transistor channel radome of a step (c) use is exactly to use the step of a capacitive character transistor channel radome in a zone of opening with field oxide isolation.Capacitive character transistor channel radome carries out the etching raceway groove of autoregistration formula with field oxide in the active region of being determined the edge by field oxide.In another most preferred embodiment, be exactly active region to be isolated in the closed region step with electric capacity transistor channel radome with field oxide with the step of capacitive character transistor channel radome and field oxide.Here determine an edge of trench type capacitor with capacitive character transistor channel radome, and other edge of trench type capacitor still uses the field oxide self-aligned, and the etched edge that wherein remains the edge is still to be determined in active region by field oxide.In another most preferred embodiment, think that with electric capacity the step of transistor channel radome and field oxide is exactly active region to be isolated into the step of using electric capacity transistor channel radome in the closed region with the gate electrode in field oxide and the active region.In another most preferred embodiment, this method also comprises step: (d) at the etch channels capacitor and after and then filling up capacitor with compound crystal silicon layer covering active region, remove capacitor transistor raceway groove radome; And, determine the contact opening that a trench type capacitor is used with the etching polycrystalline layer (e) once more at the place of above-mentioned steps opposite polarity use capacitor transistor raceway groove radome.

According to top accompanying drawing and explanatory note, the present invention has also disclosed a kind of method of making embedded DRAM (dynamic RAM) cell array on base material.This method comprises step (a) and form logic transistor on the base material with the poly-silicon gate electrode that is covered by insulating protective layer; wherein insulating protective layer is deposited on the field oxide layer next door, wherein determines the open area: and the trench type capacitor that (b) forms memory cell by etching openings zone (this zone has the trench edges of being determined by insulating protective layer and field oxide layer).In another most preferred embodiment, the step that forms logic transistor on the base material with poly-silicon gate electrode comprises formation word line (WL) and selects transistorized step, wherein each transistor all has with the rebasing WL transistor gate electrode of WL selection gate electrode oxide skin(coating), and the thickness of this oxide skin(coating) equates with the gate electrode oxide skin(coating) of pad under the poly-silicon gate electrode of logic transistor substantially.In another most preferred embodiment, this method also comprises a step (c) error code inspection (ECC) and correcting device is connected to memory cell, and all storeies that are used to check and revise in critical error detector and correction time read mistake.In another most preferred embodiment, this method also comprises a step (d) and forms diffusion layer on every side at the raceway groove that has with logic transistor drain electrode identical conduction kind.In another most preferred embodiment, this method also comprises step (e), forms logic transistor on the base material with the poly-silicon gate electrode that is covered by insulating protective layer; (f) gate electrode with a plurality of logic transistors is connected to ground voltage, so that determine a plurality of insulated transistors that are used for isolating two adjacent logic transistors, wherein the insulating protective layer of insulated transistor and adjacent logic transistor is determined open area between the two; And the trench type capacitor that (g) forms memory cell by etching openings zone (this zone has the trench edges of being determined by the insulating protective layer of insulated transistor and adjacent logic transistor).

Embedded technology of the present invention uses the high-performance transistor to support logical circuit and memory circuitry, and this circuit performance is quite high, and manufacturing course is simple.But, the leakage current that is caused by word line transistors will be higher than the leakage current of the word line transistors of prior art.Because slim gate electrode can't bear high voltage operation, so we can't use the word line supercharging mode to increase store charge.The tolerance that therefore must provide the design of innovation to improve leakage current and store charge loss, United States Patent (USP) U.S.5 has disclosed a kind of DRAM array noise signal that can improve for 748, No. 547 and has compared and can not increase the device Method for Area.After using this method, storage arrangement just can be operated under the word line voltage that does not use supercharging.It is lower and can not allow the method for the self-Data Update that external user discovers that this patent has also disclosed a kind of power consumption, use this self-data-updating method can increase the internal data renewal frequency, we just can hold higher storer electric leakage electric current like this, and need not change to the existing memory specification.Another important method is to use bug patch code (ECC) protection, to improve the tolerance for undesirable memory characteristics.

Figure 20 (a) shows in the large-scale DRAM storer storage unit distribution condition of required typical data update time.With regard to the storage arrangement of prior art, between millions of memory cells, the Data Update time T min of the worst numerical digit has determined the Data Update time of whole storage arrangement in storage arrangement.The Data Update time (Tmin) of the worst numerical digit is contained the in turn time also shorter than average data update time (Tav) usually, and this is because the worst numerical digit is always caused by the defect sturcture in the memory cell.

Figure 20 (b) shows the simplification calcspar of the storage arrangement that has the ECC holding circuit.Write operating period at storer, the data of input will be handled to calculate the ECC odd and even data by ECC parity tree (2005).The input data will deposit normal data storage device array-(2001) in, and the ECC odd and even data then deposits odd and even data array (2003) in.During read operation, can read the data and the ECC odd and even data of storage from memory array (2001,2003), and deliver to ECC parity tree (2005).Having under the situation of data damage, ECC correction logic (2007) can be found out problem and correct mistakes, and is correct so that make the data of input.The correction mechanism of ECC is for the people in the industry, and right and wrong Changshu knows, but because it needs bigger area, so do not use on DRAM cheaply.The present invention uses the ECC protection that it is treated as the method for improving memory cell leakage current tolerance, when storage arrangement is equipped with the ECC circuit, just can revise most unit mistake.As a result, the Data Update time of storage arrangement is just no longer depended on the worst numerical digit in the storer, the substitute is, and this device can operate to produce always and surpass till the machine-processed amount of error that can revise of ECC.Therefore the Data Update time (Tecc) is greater than the Tmin shown in Figure 20 (a).

According to above-mentioned new method for designing, successfully produced and in the DRAM memory cell, used the transistorized actual storage apparatus of high performance logic.

Though the present invention does explanation with existing another most preferred embodiment, can recognize can not with disclose here as being a kind of restriction, after reading above, the people in the industry just knows can many changes and correction.Therefore, the claim of the application's case can be construed to the institute that is encompassed under original spirit of the present invention and the field changes and revises.

Claims (5)

1. a manufacturing has the method for selecting transistorized embedded DRAM cell array, and wherein this DRAM cell array and high performance logic circuits coexist as on the same base material, and this method comprises:

Adopt a gate electrode formation technology to form a DRAM simultaneously and select transistorized gate electrode, and be that a high performance logic circuits forms a logical circuit gate electrode, wherein select transistor gate anodizing thing to have identical thickness substantially with logical circuit gate electrode oxide, and

Employing wherein selects the transistor AND gate logic transistor to have identical substantially critical voltage forming the roughly the same embedded technology of selection transistor AND gate logic transistor.

2. manufacturing as claimed in claim 1 has the method for selecting transistorized embedded DRAM cell array, it is characterized in that, also comprises:

Adopt a capacitive character transistor channel radome, be a plurality of trench type capacitors of described memory cell array etching.

3. manufacturing as claimed in claim 2 has the method for selecting transistorized embedded DRAM cell array, it is characterized in that, the step of described employing capacitive character transistor channel radome is exactly to adopt the step of capacitive character transistor channel radome in the active region that comes out with field oxide isolation, and wherein said capacitive character transistor channel radome makes in the active region of being determined etched edge by field oxide with this raceway groove of self-aligned mode etching with field oxide.

4. manufacturing as claimed in claim 2 has the method for selecting transistorized embedded DRAM cell array, it is characterized in that, described employing capacitive character transistor channel radome and the synergistic step of field oxide are exactly to adopt the step of capacitive character transistor channel radome in the closed region that active region is isolated into this field oxide, wherein utilize this capacitor transistor raceway groove radome to determine an edge of this trench type capacitor, and other edge of trench type capacitor still utilizes the field oxide self-aligned, and the etching of remaining edge is still determined in active region by field oxide.

5. manufacturing as claimed in claim 2 has the method for selecting transistorized embedded DRAM cell array, it is characterized in that, described employing capacitive character transistor channel radome and the synergistic step of field oxide are exactly to adopt the step of capacitive character transistor channel radome in the closed region that active region is isolated into the gate electrode in this field oxide and the active region, wherein utilize this capacitive character transistor channel radome to determine an edge of this trench type capacitor, and field oxide and gate electrode self-aligned are still used in other edge of this trench type capacitor, and the etching of remaining edge remains to be determined in active region by field oxide and gate electrode.

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