CN1279560A - Method and device for interlaced display of video signals on plasma display - Google Patents
Method and device for interlaced display of video signals on plasma display Download PDFInfo
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- CN1279560A CN1279560A CN 99116264 CN99116264A CN1279560A CN 1279560 A CN1279560 A CN 1279560A CN 99116264 CN99116264 CN 99116264 CN 99116264 A CN99116264 A CN 99116264A CN 1279560 A CN1279560 A CN 1279560A
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Abstract
A method and device for interlaced display of vedio signals on plasma display features that in odd frame (even frame) period, the data is stored in the memory of odd frame (even frame) while the data in even frame (odd frame) memory is read out, and the data in one line is output and displayed twice. In order to stagger the display positions of odd and even frames by one line, an ineffective line is inserted or a line output is delayed. Its advantages include no time dalay, no vertical or horizontal tear or saw-distortion, and high horizontal and vertical resolutions.
Description
The present invention relates to Display Technique, specifically, relate to the technology that interlaced video signal is converted to the digital signal line by line that satisfies the requirement of plasma scope sequential, more particularly, relate to a kind of method that is used on plasma scope, showing interlaced video signal.
Plasma scope (hereinafter to be referred as PDP) is owing to the needs of its display structure, and it drives and requires to be the digital rgb signal, and adopts display mode line by line.Therefore, for showing that the PDP interface circuit should have three kinds of functions: 1) video decode, digitlization with the analog video signal of interlace mode transmission; 2) interlaced/progressive conversion; 3) the PDP control timing produces.Wherein, video decode is meant compound composite video signal is separated into R, G, B component, and the compatible multiple standard of energy, and digitlization is meant that with analog signal conversion be digital signal, and decoding and digitizing function can be realized by multiple scheme, for subsequent treatment provides signal source.Wherein, for realizing interlaced/progressive conversion, traditional method has: 1) parity field directly interweave (between interpolation), its principle is that two field signals are stored in the memory on the scene, then by alternately output of control logic circuit, be woven into progressive signal, owing to kept initial data fully, therefore the definition that has kept image, but because the parity field signal exists temporal discontinuous, when image motion, can produce crenellated phenomena, especially under rapid movement image situation, can produce serious distortion.2) line-to-line correlation interpolation, its principle is in single game, utilize 2 adjacent row, the data of interpolation delegation in the middle of calculating, form progressive signal, owing to be the additional row information that produces interpolation by logical calculated, be not initial data as the average of adjacent lines, therefore obvious at the image border partial distortion; 3) interpolation between an associated row is the integration scenario of above-mentioned 2 kinds of methods, has the strong point and the deficiency of preceding two kinds of methods concurrently, and also complicated on the hardware.
The object of the present invention is to provide a kind of method that is suitable on plasma scope, showing interlaced video signal, this method can overcome the above-mentioned shortcoming of prior art, reach good display, specifically, utilize method provided by the invention interlaced video signal can be converted to digital signal line by line, and satisfy following the requirement: 1) show synchronously in real time, guarantee in the image motion process, can not produce vertical dislocation and drop-out, reach strict synchronism between the field; 2) the interpolated signal correlation is good, guarantees that picture is level and smooth under the situation that pixel doubles, and during image motion, can the generation level not tear phenomenon, guarantees that definition does not reduce; 3) output timing should satisfy the interface requirement of PDP.
Another object of the present invention provides a kind of device that shows interlaced video signal on plasma scope based on the inventive method, makes the above-mentioned advantage of display packing of the present invention be able to economy, to realize reliably by hardware.
The object of the present invention is achieved like this, constructs a kind of method of interlaced video signal that shows and may further comprise the steps in plasma scope:
Import during the strange field signal, each line data is stored in the strange field memory, take out simultaneously and be stored in each line data in the even field memory, each row of data repeats output and shows 2 times;
Import during the even field signal, each line data is stored in the even field memory, take out simultaneously and be stored in each line data in the even field memory, each row of data repeats output and shows 2 times.
According to method provided by the invention, it is characterized in that, comprise that also inserting an inactive line or the line output of delaying time makes between the parity field display position step of delegation that staggers.
According to method provided by the invention, it is characterized in that the write cycle of described video data is more than or equal to the readout interval of field video data.
Another object of the present invention is to realize like this, construct the display unit of interlaced video signal in a kind of plasma scope, comprise the video data that is used to store output buffer BUF, be used to import the digital Video Decoder of full television video frequency signal, output R, G, B digital signal and row field synchronization, blanking and parity field identification signal, and the strange field memory RAM1 and the even field memory RAM2 that are respectively applied for strange of storage, an idol video data, it is characterized in that also comprising:
Write address/control-signals generator WAC, the address/control signal when being used to produce write data;
Read address/control-signals generator RAC; Address/control signal when being used to produce read data;
The first two-way selector MUX1 is used for providing address signal according to said write address/control-signals generator WAC and the described signal of reading address/control-signals generator RAC to described strange field memory RAM1;
The second two-way selector MUX2 is used for providing address signal according to said write address/control-signals generator WAC and the described signal of reading address/control-signals generator RAC to described even field memory RAM2;
Data input switch K1, K3 are connected between described decoder output and described strange field memory RAM1, the even field memory RAM2 FPDP;
Data output switch K2, K4 are connected between described strange field memory RAM1, even field memory RAM2 FPDP and the output buffer BUF;
Parity field control-signals generator EOC, be used to be controlled at during the strange field signal of input, data are deposited write in the strange field memory, simultaneously read each line data that is stored in the even field memory twice and deliver among the output buffer BUF, during the even field signal of input, data are write in the even field memory, take out simultaneously and be stored in each line data in the even field memory, each row of data repeats output and shows 2 times.
According to device provided by the invention, it is characterized in that described parity field control-signals generator EOC makes between the parity field display position delegation of staggering inserting an inactive line or the line output of delaying time.
According to device provided by the invention, it is characterized in that the write cycle of described video data is more than or equal to the readout interval of field video data.
Implement interlaced video signal display packing and device in the plasma provided by the invention, have following characteristics: the output field frequency is identical with the input field frequency, does not have time-delay, can not produce the vertical level that reaches and tear and crenellated phenomena when image motion; Output is progressive signal, and line number doubles, and can satisfy the PDP display requirement; The horizontal resolution aspect, because the complete corresponding input signal of horizontal pixel is so horizontal resolution can keep vertically resolution aspect fully, because two duplicate rows dislocation interweave, therefore the combination in time of two field signals can reduce because the influence that the vertical resolution that duplicate rows spatially causes descends.In addition, realize that accordingly circuit is also fairly simple, and be fit to be processed into special chip.
Below in conjunction with drawings and Examples, further specify characteristics of the present invention, in the accompanying drawing:
Fig. 1 is the interlaced video frame structural representation as input signal;
Fig. 2 is a duplicate rows field interlacing frames structural representation;
Fig. 3 is a theory diagram that embodiment is a duplicate rows field interleave circuit realizing the inventive method.
Fig. 4 is the sequential schematic illustration of parity field handoff procedure when circuit working shown in Figure 3 is described.
Fig. 5 is the wrong row of a parity field sequential key diagram when implementing the circuit working shown in Figure 3 of the inventive method.
Fig. 1 and Fig. 2 show the principle of duplicate rows field deinterleaving method.Fig. 1 shows the interlaced video frame structure as input signal, this interlaced video frame structure is formed by strange and even, every only shows the effective line number of 1/2nd frames, the picture intelligence of two fields differs hemistich in time, so that can form a frame picture in interleaved relation with each other between the field on the common picture tube, so both large-area flicker can be eliminated, video bandwidth can be reduced again.
Fig. 2 shows this clearly demarcated duplicate rows field interlacing frames structure that proposes, and the field signal that at first will import is stored in the memory, and every row repeats to export 2 times during demonstration.Same method also repeats the every capable signal in another field signal to export 2 times, and key is two display positions delegation of must staggering.
Fig. 3 shows the circuit block diagram of interlaced video signal display unit in the plasma scope of the present invention, among the figure, DECODER is digital Video Decoder, import full television video frequency signal, output R, G, B digital signal and row field synchronization, blanking and parity field identification signal are for follow-up duplicate rows field interleave circuit provides data and clock signal; RAM1 and RAM2 are strange, even field memory, are used for temporary input signal data.It among Fig. 3 the control section of duplicate rows field interleave circuit, wherein: WAC writes address/control-signals generator, RAC reads address/control-signals generator, MUX1, the 2nd, the two-way selector, K1, K3 are the data input switches, K2, K4 are data output switches, and EOC is the parity field control-signals generator, and BUF is an output buffer.
Entire circuit designs around 2 field memories, in order to realize duplicate rows field interleave function, 2 field memories alternately are operated in and write and read state, and EO switches by the parity field signal, and Fig. 4 and Fig. 5 show the work schedule and the wrong row of the parity field sequential of parity field commutation circuit.
When decoder is imported strange field signal, RAM1 is in write state, and RAM2 is in the state of reading, and the address of RAM1/control signal AC1 selects through MUX1, by writing address/control-signals generator WAC control.The RAM1 data link through K1 and decoder output, and WAC is controlled by decoder, produces corresponding address and control signal, and this moment, RAM1 can store the strange field signal of input; Meanwhile, the address of RAM2/control signal AC2 selects through MUX2, by reading address/control-signals generator RAC control, the RAM2 data link through K4 and output buffer BUF, and RAC produces to satisfy address and the control signal that the PDP sequential requires, this moment, RAM2 can read previously stored even field signal, outputed to PDP through BUF.
When from decoder input be even field signal the time, under the EO signal controlling, MUX1, MUX2, K1, K2, K3, K4 then convert inverse state to, thereby make RAM1 become read states, RAM2 becomes the state of writing, and makes the strange field signal of the previous storage of RAM1 output, the even field signal of RAM2 storage positive input.
Write and the read-out speed of data are different, write fashionable, WAC produces writes address and the control signal speed corresponding to the video data stream of input, when reading, because every line output 2 times, under output field cycle and input field duration synchronous situation, 1/2nd of the line of input cycle that is necessary for of then exporting line period.Therefore in order to export identical number of picture elements.Output data rate should be about 2 times of input rate, and address that is produced by RAC and control signal speed also should be about 2 times of WAC.
Do not require output speed fully corresponding to 2 times of relations of input speed here, be because PDP only requires in input one field time, finish one read and add necessary vertical blanking period and get final product, can save output line frequency signal Synchronization like this in the phase lock circuitry of importing line frequency 2 overtones bands.
The wrong row control of parity field is the key that the duplicate rows field interweaves, because the reference point of PDP input valid data is blanking signals, institute thinks and guarantees idol and the strange field signal delegation of staggering.Go every going into an invalid line number certificate at first of an idol valid data.This is to be finished by the address time-delay delegation of reading that RAC produces, and in addition, because output 2 row are identical datas, so the row address that RAC produces is to change once in 2 row.
In plasma scope provided by the invention in the display unit of interlaced video signal, field memory RAM1, RAM2 can select for use read or write speed at 20ns with interior SRAM, the interior circuit of frame of broken lines can be made by ordinary numbers circuit integrated manufacturing technology among Fig. 3, as the MOS manufacturing process, use on a small scale and can on FPGA, finish.
Claims (6)
1, the display packing of interlacing frequency signal in a kind of plasma scope is characterized in that may further comprise the steps:
Import during the strange field signal, each line data is stored in the strange field memory, take out simultaneously and be stored in each line data in the even field memory, each row of data repeats output and shows 2 times;
Import during the even field signal, each line data is stored in the even field memory, take out simultaneously and be stored in each line data in the even field memory, each row of data repeats output and shows 2 times.
2, method according to claim 1 is characterized in that, comprises that also inserting an inactive line or the line output of delaying time makes the parity field display position step of delegation that staggers.
3, method according to claim 1 is characterized in that, the write cycle of described video data is more than or equal to the readout interval of field video data.
4, the display unit of interlaced video signal in a kind of plasma scope, comprise the video data that is used to store output buffer BUF, be used to import the digital Video Decoder of full television video frequency signal, output R, G, B digital signal and row field synchronization, blanking and parity field identification signal, and the strange field memory RAM1 and the even field memory RAM2 that are respectively applied for strange of storage, an idol video data, it is characterized in that also comprising:
Write address/control-signals generator WAC, the address/control signal when being used to produce write data;
Read address/control-signals generator RAC; Address/control signal when being used to produce read data;
The first two-way selector MUX1 is used for providing address signal according to said write address/control-signals generator WAC and the described signal of reading address/control-signals generator RAC to described strange field memory RAM1;
The second two-way selector MUX2 is used for providing address signal according to said write address/control-signals generator WAC and the described signal of reading address/control-signals generator RAC to described even field memory RAM2;
Data input switch K1, K3 are connected between described decoder output and described strange field memory RAM1, the even field memory RAM2 FPDP;
Data output switch K2, K4, be connected between described strange field memory RAM1, even field memory RAM2 FPDP and the output buffer BUF: parity field control-signals generator EOC, be used to be controlled at during the strange field signal of input, data are deposited write in the strange field memory, simultaneously read each line data that is stored in the even field memory twice and deliver among the output buffer BUF, during the even field signal of input, data are write in the even field memory, take out simultaneously and be stored in each line data in the even field memory, each row of data repeats output and shows 2 times.
5, device according to claim 4 is characterized in that, described parity field control-signals generator EOC makes between the parity field display position delegation of staggering inserting an inactive line or the line output of delaying time.
6, device according to claim 4 is characterized in that, the write cycle of described video data is more than or equal to the readout interval of field video data.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN 99116264 CN1279560A (en) | 1999-07-02 | 1999-07-02 | Method and device for interlaced display of video signals on plasma display |
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| CN 99116264 CN1279560A (en) | 1999-07-02 | 1999-07-02 | Method and device for interlaced display of video signals on plasma display |
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| CN 99116264 Pending CN1279560A (en) | 1999-07-02 | 1999-07-02 | Method and device for interlaced display of video signals on plasma display |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7079090B2 (en) | 2002-02-13 | 2006-07-18 | Fujitsu Hitachi Plasma Display Limited | Driving method for a plasma display panel and plasma display apparatus |
| CN100336393C (en) * | 2001-11-20 | 2007-09-05 | 汤姆森许可公司 | Low bit rate compression format conversion for improved resolution |
| CN101281722B (en) * | 2003-05-29 | 2010-12-15 | 东北先锋电子股份有限公司 | Dot matrix type display device and information equipment employing the same |
| CN101488325B (en) * | 2008-01-14 | 2012-03-28 | 联咏科技股份有限公司 | Image driving method and driving circuit for display, and display apparatus |
-
1999
- 1999-07-02 CN CN 99116264 patent/CN1279560A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100336393C (en) * | 2001-11-20 | 2007-09-05 | 汤姆森许可公司 | Low bit rate compression format conversion for improved resolution |
| US7079090B2 (en) | 2002-02-13 | 2006-07-18 | Fujitsu Hitachi Plasma Display Limited | Driving method for a plasma display panel and plasma display apparatus |
| CN101281722B (en) * | 2003-05-29 | 2010-12-15 | 东北先锋电子股份有限公司 | Dot matrix type display device and information equipment employing the same |
| CN101488325B (en) * | 2008-01-14 | 2012-03-28 | 联咏科技股份有限公司 | Image driving method and driving circuit for display, and display apparatus |
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