CN1278219C - Image processor - Google Patents
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- CN1278219C CN1278219C CN 200410048551 CN200410048551A CN1278219C CN 1278219 C CN1278219 C CN 1278219C CN 200410048551 CN200410048551 CN 200410048551 CN 200410048551 A CN200410048551 A CN 200410048551A CN 1278219 C CN1278219 C CN 1278219C
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Abstract
The present invention relates to an image processing device which is used between a computer system and at least one plane display. The image processing device comprises a picture buffer, a first display engine, a second display engine, a pulse signal generator, a first-in first-out buffer memory, a pulse signal generator with broadband frequency and a reset signal generator, wherein the first-in first-out buffer memory which is electrically connected with the first display engine, the second display engine, the pulse signal generator and the plane display controls a data write-in pointer according to a working pulse signal generated by the pulse signal generator; the pulse signal generator with broadband frequency, which is electrically connected between the pulse signal generator and the first-in first-out buffer memory, is used for receiving the working pulse signal generated by the pulse signal generator and converting the working pulse signal into a pulse signal with broadband frequency to be output to the first-in first-out buffer memory; the reset signal generator which is electrically connected with the first-in first-out buffer memory is used for receiving the digital data of a plurality of pixel points which need to be input into the first-in first-out buffer memory, and the reset signal generator is also used for comparing the digital data.
Description
Technical field
The present invention relates to a kind of image processor, relate in particular to a kind of image processor that is applied between a personal computer system and at least one flat-panel screens.
Background technology
See also Fig. 1, it is a common image Presentation Function block schematic diagram among the personal computer system commonly used, for having the image Presentation Function that to support multiple screen display, wherein consist predominantly of a picture buffer (frame buffer) 10, first display engine 11, second display engine 12 and first multiplexer 15 and second multiplexer 16.Computer system is deposited in picture buffer 10 with the image data that desire shows, and the parallel processing by first display engine 11 and second display engine 12, computer system can be respectively at the different picture of displaying contents on camera tube display 21 and the LCD 22.And the configuration by first multiplexer 15 and second multiplexer 16, computer system also can only utilize first display engine 11 (or second display engine 12) to handle, and the identical picture of demonstration on camera tube display 21 and LCD 22 simultaneously.
And since LCD 22 for electromagnetic interference (EMI) (Electromagnetic Interference, abbreviation EMI) standard is comparatively strict, but because of originally by the designed phase-locked loop pulse signal producer 19 of camera tube display 21 the frequency spectrum of generation pulse signal too concentrated, therefore if directly use pulse signal that phase-locked loop pulse signal producer 19 produced that image data is exported in the LCD 22, the electromagnetic interference (EMI) phenomenon of LCD 22 will too seriously can't be passed through test, therefore one first-in first-out buffer memeory (FIFO buffer) 14 just is set between second multiplexer 16 and LCD 22, the data that its pulse signal LCDCLK that utilizes phase-locked loop pulse signal producer 19 to be exported controls this first-in first-out buffer memeory (FIFO buffer) 14 write moving of pointer, the extending frequency pulse signal SSCLK that but utilizes an extending frequency pulse signal (spread spectrum clock) generator 20 to be exported controls the data of this first-in first-out buffer memeory (FIFO buffer) 14 and reads moving of pointer, the pulse signal LCDCLK that the script frequency spectrum is too concentrated that is used for by this extending frequency pulse signal generator 20 is broken up, in order to improve the electromagnetic interference (EMI) of LCD 22.
But, when the data of using above-mentioned pulse signal LCDCLK and extending frequency pulse signal SSCLK to control this first-in first-out buffer memeory (FIFO buffer) 14 respectively write pointer and data and read pointer mobile, because the signal frequency of extending frequency pulse signal SSCLK can change in time, therefore both frequency differences will cause first-in first-out buffer memeory (FIFO buffer) 14 to produce operational mistake, for example commonly, the address that data write pointer is the data address (being overflow (overflow)) of reading pointer in advance, causes data output undesired and picture is shown produce mistake.
Summary of the invention
Fundamental purpose of the present invention is in order to overcome the defective of prior art, and a kind of image processor is provided, and this device does can be reset because of index influence the demonstration of normal pictures, can avoid the generation of overflow phenomenon again.
For realizing purpose of the present invention, the invention provides a kind of image processor, be applied between a personal computer system and at least one flat-panel screens, this image processor comprises: a picture buffer wherein stores digital image data; One first display engine is electrically connected on this picture buffer, and it reads the stored digital image data of this picture buffer and handles the back and produce a plurality of pixel number digital data and send; One second display engine is electrically connected on this picture buffer, and it reads the stored digital image data of this picture buffer and handles the back and produce a plurality of pixel number digital data and send; One pulse signal producer is electrically connected on this first display engine and this second display engine, and it provides described display engine required working pulse signal; One first-in first-out buffer memeory, be electrically connected on this first display engine and this second display engine, this pulse signal producer and this flat-panel screens, it is controlled data according to the working pulse signal that this pulse signal producer produced and writes pointer, writes wherein in order to a plurality of pixel number digital data with this first display engine or the output of this second display engine; One extending frequency pulse signal generator, be electrically connected between this pulse signal producer and this first-in first-out buffer memeory, it receives the working pulse signal that this pulse signal producer produces and converts an extending frequency pulse signal to and exports this first-in first-out buffer memeory to, reads pointer in order to data of controlling this first-in first-out buffer memeory; An and device for producing reset signal, be electrically connected on this first-in first-out buffer memeory, its reception desire is imported a plurality of pixel number digital data of this first-in first-out buffer memeory and is compared, and meet a predetermined content and when a picture occurring and showing neutral gear when the pixel number digital data in the described pixel number digital data, just produce a reset signal to this first-in first-out buffer memeory, and then control these data and write pointer and this data and read pointer and return back to one and open the beginning address.
According to above-mentioned conception, image processor of the present invention, its applied this flat-panel screens is a LCD.
According to above-mentioned conception, image processor of the present invention, wherein this first display engine, this second display engine, this pulse signal producer, this first-in first-out buffer memeory and this device for producing reset signal can be integrated in the image processing chip, and this extending frequency pulse signal generator then is independent of outside this image processing chip.
According to above-mentioned conception, image processor of the present invention, wherein this pixel number digital packets contains: one shows the control bit block, this block has the required bit data of a plurality of demonstration controls; And an image data position block, this block has a plurality of image datas position.
According to above-mentioned conception, image processor of the present invention, wherein this demonstration control bit block includes a vertical synchronization position, a horizontal synchronization position and a data start bit.
According to above-mentioned conception, image processor of the present invention, wherein this vertical synchronization position, this horizontal synchronization position and this data start bit in this pixel number digital data is respectively 1,0,0, and all positions of image data position block were all 0 o'clock, this device for producing reset signal just produces this reset signal to this first-in first-out buffer memeory, and then controls these data and write pointer and this data and read pointer and return back to one and open the beginning address.
According to above-mentioned conception, image processor of the present invention, wherein this vertical synchronization position, this horizontal synchronization position and this data start bit in this pixel number digital data is respectively 0,0,0, and all positions of image data position block were all 0 o'clock, this device for producing reset signal just produces this reset signal to this first-in first-out buffer memeory, and then controls these data and write pointer and this data and read pointer and return back to one and open the beginning address.
According to above-mentioned conception, image processor of the present invention, wherein these data of this first-in first-out buffer memeory write pointer and this data and read the beginning address of opening of pointer and be respectively first address and N address, and this first-in first-out buffer memeory has 2N address.
Another aspect of the invention is a kind of image processor, be applied between a personal computer system and at least one flat-panel screens, this image processor comprises: a picture buffer wherein stores digital image data; One display engine is electrically connected on this picture buffer, and it reads the stored digital image data of this picture buffer and handles the back and produce a plurality of pixel number digital data and send; One pulse signal producer is electrically connected on this display engine, and it provides this display engine required working pulse signal; One first-in first-out buffer memeory, be electrically connected on this display engine, this pulse signal producer and this flat-panel screens, it is controlled data according to the working pulse signal that this pulse signal producer produced and writes pointer, writes wherein in order to a plurality of pixel number digital data with this display engine output; One extending frequency pulse signal generator, be electrically connected between this pulse signal producer and this first-in first-out buffer memeory, it receives the working pulse signal that this pulse signal producer produces and converts an extending frequency pulse signal to and exports this first-in first-out buffer memeory to, reads pointer in order to data of controlling this first-in first-out buffer memeory; An and device for producing reset signal, be electrically connected on this first-in first-out buffer memeory, its reception desire is imported a plurality of pixel number digital data of this first-in first-out buffer memeory and is compared, and meet a predetermined content and when a picture occurring and showing neutral gear when the pixel number digital data in the described pixel number digital data, just produce a reset signal to this first-in first-out buffer memeory, and then control these data and write pointer and this data and read pointer and return back to one and open the beginning address.
According to above-mentioned conception, image processor of the present invention, wherein this pixel number digital packets contains one and shows a control bit block and an image data position block, vertical synchronization position in this pixel number digital data that this device for producing reset signal receives, an one horizontal synchronization position and a data start bit are respectively 1,0,0 or 0,0,0, and all positions of image data position block were all 0 o'clock, this device for producing reset signal just produces this reset signal to this first-in first-out buffer memeory, and then controls these data and write pointer and this data and read pointer and return back to one and open the beginning address.
Description of drawings
The present invention can obtain a more deep understanding by following accompanying drawing and detailed description:
Fig. 1 is a common image Presentation Function block schematic diagram among the personal computer system commonly used.
It is the preferred embodiment function block schematic diagram of the present invention for image processor among the improvement personal computer system commonly used Fig. 2.
Fig. 3 is the scanning synoptic diagram that picture (frame) shows.
10,30: picture buffer 11,31: the first display engines
12,32: the second display engines 15,35: the first multiplexers
16,36: the second multiplexers 21: camera tube display
22: LCD 19,39: phase-locked loop pulse signal producer
14,34: first-in first-out buffer memeory 20: the extending frequency pulse signal generator
38: device for producing reset signal 40,41: show neutral gear
Embodiment
See also Fig. 2, its the present invention is for improving a preferred embodiment function block schematic diagram of image processor among the personal computer system commonly used, for having the image Presentation Function that to support multiple screen display, wherein consist predominantly of a picture buffer (frame buffer) 30, first display engine 31, second display engine 32 and first multiplexer 35 and second multiplexer 36.Computer system is deposited in picture buffer 30 with the image data that desire shows, and the parallel processing by first display engine 31 and second display engine 32, computer system can be respectively at the different picture of displaying contents on camera tube display 21 and the LCD 22.And the configuration by first multiplexer 35 and second multiplexer 36, computer system also can only utilize first display engine 31 (or second display engine 32) to handle, and the identical picture of demonstration on camera tube display 21 and LCD 22 simultaneously.And between second multiplexer 36 and LCD 22, also be provided with a first-in first-out buffer memeory (FIFO buffer) 34, the data that its pulse signal LCDCLK that utilizes phase-locked loop pulse signal producer 39 to be exported controls this first-in first-out buffer memeory (FIFO buffer) 34 write moving of pointer, the extending frequency pulse signal SSCLK that utilizes an extending frequency pulse signal (spread spectrum clock) generator 20 to be exported again controls the data of this first-in first-out buffer memeory (FIFO buffer) 34 and reads moving of pointer, the pulse signal LCDCLK that the script frequency spectrum is too concentrated that is used for by this extending frequency pulse signal generator 20 is broken up, in order to improve the electromagnetic interference (EMI) of LCD 22.
And for improving common deficiency, the present invention sets up a device for producing reset signal 38 between second multiplexer 36 and this first-in first-out buffer memeory 34, it receives this second multiplexer 36 and desires to export a plurality of pixel number digital data of this first-in first-out buffer memeory 34 to and compare, and meet a predetermined content and when a picture occurring and showing neutral gear when the pixel number digital data in the described pixel number digital data, just produce a reset signal to this first-in first-out buffer memeory 34, and then control these data and write pointer and this data and read pointer and return back to one and open the beginning address.For instance, general pixel number digital data consists predominantly of a demonstration control bit block and an image data position block is formed, wherein this demonstration control bit block includes a vertical synchronization position (V-sync), a horizontal synchronization position (H-sync) and a data start bit (Data-Active), and image data position block then is made up of 24 positions (each 8 of R, G, B three primary colors).Therefore device for producing reset signal 38 of the present invention can be respectively 1,0,0 or 0,0,0 in response to this vertical synchronization position in this received pixel number digital data, this horizontal synchronization position and this data start bit, and all positions of image data position block were all 0 o'clock, this device for producing reset signal 38 just produces this reset signal to this first-in first-out buffer memeory 34, and then controls these data and write pointer and this data and read pointer and return back to one and open the beginning address.And these data write the 1st address and the 16th address that the beginning address can be first-in first-out buffer memeory 34 respectively of opening that pointer and this data are read pointer, and this first-in first-out buffer memeory 34 has 32 addresses.
This vertical synchronization position of above-mentioned pixel number digital data, this horizontal synchronization position and this data start bit are respectively 1,0,0 or 0,0,0; and all of image data position block are all for 0 opportunity; just can represent and show a picture (frame) and do not begin to show demonstration neutral gear (seeing demonstration neutral gear 40 shown in Figure 3) between another picture (frame) as yet; carrying out the index replacement at this will be an inning; can not have influence on the demonstration of normal pictures, or between every sweep trace, (see demonstration neutral gear 41 shown in Figure 3).Thus; the data that the present invention can detect the first-in first-out buffer memeory 34 of resetting opportune moment write pointer and data are read pointer; neither can reset because of index influences the demonstration of normal pictures, can avoid the generation of overflow phenomenon again, and then reach development fundamental purpose of the present invention.
In addition, above-mentioned flat-panel screens can be a LCD, plasma scope etc., and this first display engine 31, this second display engine 32, this phase-locked loop pulse signal producer 39, this first-in first-out buffer memeory 34 and this device for producing reset signal 38 can be integrated in the image processing chip, can be independent of this image processing chip or also are integrated in the image processing chip as for 20 of this extending frequency pulse signal generators.But the present invention must be appointed by those skilled in the art and executes that the craftsman thinks and be to modify as all, yet the scope of neither disengaging such as the desire protection of claims institute.
Claims (10)
1. an image processor is applied between a personal computer system and at least one flat-panel screens, and wherein this image processor comprises:
One picture buffer wherein stores digital image data;
One first display engine is electrically connected on this picture buffer, and it reads the stored digital image data of this picture buffer and handles the back and produce a plurality of pixel number digital data and send;
One second display engine is electrically connected on this picture buffer, and it reads the stored digital image data of this picture buffer and handles the back and produce a plurality of pixel number digital data and send;
One pulse signal producer is electrically connected on this first display engine and this second display engine, and it provides described display engine required working pulse signal;
One first-in first-out buffer memeory, be electrically connected on this first display engine and this second display engine, this pulse signal producer and this flat-panel screens, it is controlled data according to the working pulse signal that this pulse signal producer produced and writes pointer, writes wherein in order to a plurality of pixel number digital data with this first display engine or the output of this second display engine;
One extending frequency pulse signal generator, be electrically connected between this pulse signal producer and this first-in first-out buffer memeory, it receives the working pulse signal that this pulse signal producer produces and converts an extending frequency pulse signal to and exports this first-in first-out buffer memeory to, reads pointer in order to data of controlling this first-in first-out buffer memeory; And
One device for producing reset signal, be electrically connected on this first-in first-out buffer memeory, its reception desire is imported a plurality of pixel number digital data of this first-in first-out buffer memeory and is compared, and meet a predetermined content and when a picture occurring and showing neutral gear when the pixel number digital data in the described pixel number digital data, just produce a reset signal to this first-in first-out buffer memeory, and then control these data and write pointer and this data and read pointer and return back to one and open the beginning address.
2. image processor as claimed in claim 1 is characterized in that, its applied this flat-panel screens is a LCD.
3. image processor as claimed in claim 1, it is characterized in that, this first display engine, this second display engine, this pulse signal producer, this first-in first-out buffer memeory and this device for producing reset signal can be integrated in the image processing chip, and this extending frequency pulse signal generator then is independent of outside this image processing chip.
4. image processor as claimed in claim 1 is characterized in that, this pixel number digital packets contains:
One shows the control bit block, and this block has the required bit data of a plurality of demonstration controls; And
One image data position block, this block has a plurality of image datas position.
5. image processor as claimed in claim 4 is characterized in that, this demonstration control bit block includes a vertical synchronization position, a horizontal synchronization position and a data start bit.
6. image processor as claimed in claim 5, it is characterized in that, this vertical synchronization position in this pixel number digital data, this horizontal synchronization position and this data start bit are respectively 1,0,0, and all positions of image data position block were all 0 o'clock, this device for producing reset signal just produces this reset signal to this first-in first-out buffer memeory, and then controls these data and write pointer and this data and read pointer and return back to one and open the beginning address.
7. image processor as claimed in claim 5, it is characterized in that, this vertical synchronization position in this pixel number digital data, this horizontal synchronization position and this data start bit are respectively 0,0,0, and all positions of image data position block were all 0 o'clock, this device for producing reset signal just produces this reset signal to this first-in first-out buffer memeory, and then controls these data and write pointer and this data and read pointer and return back to one and open the beginning address.
8. image processor as claimed in claim 1, it is characterized in that, these data of this first-in first-out buffer memeory write pointer and this data and read the beginning address of opening of pointer and be respectively first address and N address, and this first-in first-out buffer memeory has 2N address.
9. an image processor is applied between a personal computer system and at least one flat-panel screens, and wherein this image processor comprises:
One picture buffer wherein stores digital image data;
One display engine is electrically connected on this picture buffer, and it reads the stored digital image data of this picture buffer and handles the back and produce a plurality of pixel number digital data and send;
One pulse signal producer is electrically connected on this display engine, and it provides this display engine required working pulse signal;
One first-in first-out buffer memeory, be electrically connected on this display engine, this pulse signal producer and this flat-panel screens, it is controlled data according to the working pulse signal that this pulse signal producer produced and writes pointer, writes wherein in order to a plurality of pixel number digital data with this display engine output;
One extending frequency pulse signal generator, be electrically connected between this pulse signal producer and this first-in first-out buffer memeory, it receives the working pulse signal that this pulse signal producer produces and converts an extending frequency pulse signal to and exports this first-in first-out buffer memeory to, reads pointer in order to data of controlling this first-in first-out buffer memeory; And
One device for producing reset signal, be electrically connected on this first-in first-out buffer memeory, its reception desire is imported a plurality of pixel number digital data of this first-in first-out buffer memeory and is compared, and meet a predetermined content and when a picture occurring and showing neutral gear when the pixel number digital data in the described pixel number digital data, just produce a reset signal to this first-in first-out buffer memeory, and then control these data and write pointer and this data and read pointer and return back to one and open the beginning address.
10. image processor as claimed in claim 9, it is characterized in that, this pixel number digital packets contains one and shows a control bit block and an image data position block, vertical synchronization position in this pixel number digital data that this device for producing reset signal receives, an one horizontal synchronization position and a data start bit are respectively 1,0,0 or 0,0,0, and all positions of image data position block were all 0 o'clock, this device for producing reset signal just produces this reset signal to this first-in first-out buffer memeory, and then controls these data and write pointer and this data and read pointer and return back to one and open the beginning address.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200410048551 CN1278219C (en) | 2004-06-08 | 2004-06-08 | Image processor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200410048551 CN1278219C (en) | 2004-06-08 | 2004-06-08 | Image processor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1584819A CN1584819A (en) | 2005-02-23 |
| CN1278219C true CN1278219C (en) | 2006-10-04 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200410048551 Expired - Lifetime CN1278219C (en) | 2004-06-08 | 2004-06-08 | Image processor |
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| Country | Link |
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| CN (1) | CN1278219C (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101426118B (en) * | 2007-10-29 | 2011-10-12 | 普诚科技股份有限公司 | Video processing device and video playing system |
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- 2004-06-08 CN CN 200410048551 patent/CN1278219C/en not_active Expired - Lifetime
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| CN1584819A (en) | 2005-02-23 |
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Granted publication date: 20061004 |