CN1277296C - Field effect transistor structure possessing strain silicon germanium layer beaping crystal and its manufacturing method - Google Patents
Field effect transistor structure possessing strain silicon germanium layer beaping crystal and its manufacturing method Download PDFInfo
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- CN1277296C CN1277296C CN 03107972 CN03107972A CN1277296C CN 1277296 C CN1277296 C CN 1277296C CN 03107972 CN03107972 CN 03107972 CN 03107972 A CN03107972 A CN 03107972A CN 1277296 C CN1277296 C CN 1277296C
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Abstract
The present invention discloses a method for fabricating a field effect transistor with strained Si-Ge layer heaping crystal. The present invention comprises the following steps: a Si substrate is provided; a Si buffer layer and a strained Si<1-x>Ge<x> passage layer grow on the Si substrate in the form of heaping crystal, wherein the strained Si<1-x>Ge<x> passage layer is under a biaxial compressing strain condition; a gate insulation layer is formed on the strained Si<1-x>Ge<x> passage layer; a grid electrode is formed on the gate insulation layer, and both sides of the grid electrode are formed with a source electrode/ drain electrode.
Description
Technical field
The present invention relates to a kind of field-effect transistor, be meant a kind of field-effect transistor structure and manufacture method thereof especially with strain silicon germanium layer extension (epitaxy).
Background technology
Along with the downsizing of grid assembly size, make mos field effect transistor (MOSFET) assembly can be under low operating voltage, having tend to act electric current and performance at a high speed of height is suitable difficulty.Therefore, many people are in the method for making great efforts to seek to improve the performance of mos field effect transistor assembly.
The band structure modification of utilizing strain to cause increases the mobility of carrier, to increase the electric current of tending to act of field-effect transistor, can improve the performance of field effect transistor element, and this kind method has been applied in the various assemblies.The silicon channel of these assemblies is in the situation of biaxial stretch-formed strain.
Increase mobility (the K.Ismail et al. of electronics in the situation that existing research is pointed out to utilize the silicon passage to be in biaxial stretch-formed strain, " Electron transport properties in Si/SiGe heterostructures:Measurements and device applications ", Appl.Phys.Lett.63, pp.660,1993.), and utilize the SiGe passage is in increases the hole in the situation of biaxial compressive strain mobility (D.K.Nayaket al., " Enhancement-mode quantum-well GeSi PMOS ", IEEE Elect.Dev.Lett.12, pp.154,1991.).Yet, be difficult to finish in conjunction with the NMOSFETs of silicon passage and the CMOS manufacturing technology of PMOSFETs with SiGe passage of biaxial compressive strain with biaxial stretch-formed strain.Many strained layer manufacture methods (K.Ismail et al. such as utilizing thick resilient coating or complex multilayer is arranged in transistorized manufacturing, IBM, Jul.1996, Complementary metal-oxide semiconductortransistor logic using strained Si/SiGe heterostructure layers, U.S.PatentNo.5534713.), these a little methods are not readily integrated in traditional CMOS operation.
Therefore, have the tend to act mos field effect transistor assembly of electric current and performance at a high speed of height, suddenly treat to seek the road of improvement at the problems referred to above in order to make.
Summary of the invention
In view of this, the purpose of this invention is to provide a kind of field-effect transistor structure and manufacture method thereof with strain silicon germanium layer extension, it utilizes to form has strained silicon Germanium channel layer (Y.-C.Yeo et al., " Enhanced performance in sub-100nm CMOSFETs using strained epitaxialsilicon-germanium ", IEEE International Electron Device Meeting TechnicalDigest, pp.753-756, San Francisco, CA, Dec.2000.), with the increase electric current of tending to act.
For achieving the above object, the present invention proposes a kind of manufacture method, comprise the following steps: to provide a silicon base with field-effect transistor of strain silicon germanium layer extension (epitaxy); Epitaxial growth one silicon buffer layer and a strain Si on this silicon base
1-xGe
xChannel layer, wherein this strain Si
1-xGe
xChannel layer is under the biaxial compressive strain situation; At this strain Si
1-xGe
xForm a gate insulator on the channel layer; On this gate insulator, form a gate electrode; And in this gate electrode both sides formation one source pole and drain electrode.
The present invention has also proposed a kind of manufacture method with field-effect transistor of strain silicon germanium layer extension in addition, comprises the following steps: to provide a silicon base; Epitaxial growth three composite beds that do not mix on this silicon base, this three composite bed is by a silicon buffer layer, a strain Si
1-xGe
xA channel layer and a silicon covering layer are formed, wherein this strain Si
1-xGe
xChannel layer is under the biaxial compressive strain situation; On this silicon covering layer, form a gate insulator; On this gate insulator, form a gate electrode; And in this gate electrode both sides formation one source pole and drain electrode.
The present invention also provides a kind of manufacture method with CMOS of strain silicon germanium layer extension, comprises the following steps: to provide a silicon base, and this substrate isolates active area by insulation and has a p-well area and a n-well area; Epitaxial growth three composite beds that do not mix on this silicon base, this three composite bed is by a silicon buffer layer, a strain Si
1-xGe
xA channel layer and a silicon covering layer are formed, wherein this strain Si
1-xGe
xChannel layer is under the biaxial compressive strain situation; On this silicon covering layer, form a gate insulator; On this gate insulator, form a gate electrode; Implement n type and p type ion doping to define a PMOS assembly and a NMOS assembly for this p-well area and n-well area; And in this gate electrode both sides formation one source pole and drain electrode.
The present invention proposes a kind of field-effect transistor structure with strain silicon germanium layer extension in addition, is applicable to a silicon base, comprising: a silicon buffer layer, and epitaxial growth is on the active area of this silicon base; One strain Si
1-xGe
xChannel layer, epitaxial growth on this resilient coating, this strain Si wherein
1-xGe
xChannel layer is under the biaxial compressive strain situation; One gate insulator is formed at this strain Si
1-xGe
xOn the channel layer; One gate electrode is formed on this gate insulator; And one source pole and drain electrode, be formed at this gate electrode both sides.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent, preferred embodiment cited below particularly, and conjunction with figs. are described in detail below.
Description of drawings
Fig. 1 to Fig. 7 represents to have according to an embodiment of the invention manufacturing process's profile of the field-effect transistor of strain silicon germanium layer extension;
Fig. 8 represents a kind of process profile of metal silicide layer of the field-effect transistor with strain silicon germanium layer extension;
Fig. 9 represents that another kind has the process profile of metal silicide layer of the field-effect transistor of strain silicon germanium layer extension;
Figure 10 represents that another kind has the process profile of metal silicide layer of the field-effect transistor of strain silicon germanium layer extension.
Wherein, description of reference numerals is as follows:
10～silicon base; 12～fleet plough groove isolation structure;
14,50～silicon buffer layer; 16,52～strain Si
1-xGe
xChannel layer;
18,54～silicon covering layer; 20～extended source/drain region;
22～gate insulator (or silicon oxide layer); 24～V-type groove;
26～dielectric layer; 28～gate electrode; 30～clearance wall;
32～metal silicide layer; S/D～source/drain electrode; 34～silicon layer.
Embodiment
The invention provides a kind of field-effect transistor structure and manufacture method thereof with strain silicon germanium layer extension.And in the present invention that atomic size is big than silicon element (for example germanium) imports in the silicon layer, has the channel layer of strain with making.
As shown in Figure 1, provide a silicon base 10, silicon base 10 is with fleet plough groove isolation structure (shallowtrench isolation, STI) 12 definition active areas.The present invention can be applicable to PMOS assembly, NMOS assembly and cmos component, in Fig. 1 is to illustrate with cmos component rice, so demonstrate p-trap (p-well) zone and n-trap (n-well) zone among the figure.Then as shown in Figure 2, epitaxial growth (epitaxy) three composite beds that do not mix comprise on silicon base 10: a silicon buffer layer 14, a strain Si
1-xGe
xChannel layer 16, an and silicon covering layer 18.Three composite beds of growing up for example utilize the selective epitaxial method to be formed at the active area of silicon base 10.The thickness of silicon buffer layer 14 is as much as possible little, is preferably less than 10nm.Strain Si
1-xGe
xThe mole rate x of Ge in the channel layer 16 is between 0.1 to 0.5, and during as if x=0.25, the critical thickness of strain SiGe layer is 10nm.Thickness Design for the strain SiGe layer of component design is not to be large enough to hold most reversed charge, but too thick and surpass critical thickness and make that the SiGe thin layer is metastable (metastable), and metastable thin layer can relax when high-temperature process.Epitaxial growth three composite beds that do not mix can utilize the high vacuum chemical vapour deposition process (ultra-high-vacuum chemicalvapor deposition UHVCD) forms.Strain Si wherein
1-xGe
xChannel layer 16 is under the biaxial compressive strain situation.Above-mentioned epitaxial growth does not mix the step of three composite beds also can only first epitaxial growth silicon buffer layer 14 and strain Si
1-xGe
xChannel layer 16 is asked for an interview following explanation.
As shown in Figure 6, the thickness of the silicon covering layer 18 of being grown up be depend on its target final thickness and the thickness of the grid oxic horizon that forms of the thermal oxidation of wanting, with these silicon covering layer 18 oxidations, make the top layer of silicon covering layer 18 transfer silicon oxide layer 22 to afterwards, remaining silicon layer then is denoted as 18a.The thickness of the silicon covering layer 18 of being grown up is decided by the thickness of its last remaining thickness and thermal oxidation rear oxidation silicon layer 22.Usually, after step of thermal oxidation, if the thickness tox of silicon oxide layer 22, then the thickness of silicon covering layer 18 can consume about 0.46tox.Suppose that wish that the silicon oxide layer 22 that step of thermal oxidation forms is 10 dusts (), the predetermined thickness of silicon layer 18a is 5 dusts, then needs the silicon layer 18 of growth 9.6 dusts before carrying out step of thermal oxidation.This silicon covering layer 18 provides a good interface quality, and can avoid silicon oxide layer 22 directly to grow up at Si
1-xGe
xChannel layer 16 surfaces, silicon covering layer 18 must cover the edge (as shown in Figure 2) of SiGe layer 16 to avoid the causing oxidation of SiGe layer when thermal oxidation is grown up.The preferable thickness of silicon layer 18a after the thermal oxidation is 2～6 atom level layers (atomic layers), promptly about 5～15 Izod right sides.This silicon covering layer 18 provides a good interface quality, and can avoid silicon oxide layer 22 directly to grow up at Si
1-xGe
xChannel layer 16 surfaces, the germanium concentration that can guarantee silicon covering layer 18a, silicon oxide layer 22 interfaces are lower than 5% and make silicon oxide layer 22 that good quality be arranged.The more important thing is that the existence of this thin silicone layer 18a can guarantee that reversed charge density is collected at Si in the N channel transistor
1-xGe
xIn the channel layer 16, and make most movable carrier (for example electronics) be positioned at Si
1-xGe
xIn the channel layer 16, so will help and benefit strain Si
1-xGe
xThe band structure modification of channel layer.Therefore, can promote transistorized performance again.Moreover because the ultra-thin silicon cover layer can cause pin hole, therefore silicon covering layer in the past is thicker, yet among the present invention, can obtain the thinnest silicon covering layer and the thickest grid oxic horizon with the formed grid oxic horizon of the method, can the actual problem that solves pin hole.
The formation of gate insulator 22 also can be selected other method, utilizes chemical vapour deposition technique in strain Si
1-xGe
xDeposition of aluminium oxide, hafnium oxide or zirconia on the channel layer 16.
As shown in Figure 3, form three composite beds that do not mix and also have another kind of method, be to use the non-selective epitaxy method, comprise a silicon buffer layer 50 in comprehensive formation of silicon base 10 as liquid phase epitaxial method; One strain Si
1-xGe
xChannel layer 52, and three composite beds of a silicon covering layer 54.Formation method, condition and the thickness of this three composite bed is identical with aforementioned person, and unique difference is to be that these a little thin layers are to form with the non-selective epitaxy method.
As shown in Figure 4, etching is removed in the part of isolated area and is stayed silicon buffer layer 50, strain Si on active area again
1-xGe
xChannel layer 52, and three lamination layer structures of silicon covering layer 54.
Then, as shown in Figure 5, after forming three composite beds that do not mix and before the growth grid oxic horizon, optionally on the V-shaped groove 24 at active area edge, form dielectric layer 26, to solve the more weak grid oxic horizon insulating properties of transistor side.Dielectric layer 26 for example uses chemical vapour deposition technique to form silicon oxide layer.
Then, please as shown in Figure 6, on gate insulator 22, form gate electrode 28.
Afterwards, please as shown in Figure 7, carry out n type and p type ion doping respectively at p-trap (p-well) zone and n-trap (n-well) zone of gate electrode 28 both sides again, and form clearance wall 30 at the sidewall of gate electrode 18, for example use chemical vapour deposition technique to form silicon nitride layer as clearance wall 30.And carry out rapid thermal annealing processing procedure (RTA) and do not causing Si
1-xGe
xActivation n type and p type ion doping under the situation of channel layer 16 strain relaxations, to form expansion source S or drain D district 20, wherein the temperature of rapid thermal annealing processing procedure (RTA) is approximately between 950 ℃ to 1050 ℃.
Form metal silicides (silicide) layer at last, and in source S and drain D and gate electrode 28 surfaces.Its formation method have following three kinds available.
First method as shown in Figure 8, is used traditional method, with the Si in source S and the drain D
1-xGe
xThe metal silication reaction is carried out to form metal silicide (silicide) layer 32 in channel layer 16 top layers.Meaning promptly deposits layer of metal, and for example titanium then utilizes high temperature, makes titanium and Si
1-xGe
xThe metal silication reaction is carried out on channel layer 16 top layers, utilizes wet etching to remove unreacted titanium at last.
Second method as shown in Figure 9, is before carrying out the metal silication reaction, removes the Si that exposes
1-xGe
xChannel layer 16 makes in the metal silicide layer 32 of formation not contain any germanium atom.
The third method as shown in figure 10, is the Si in source S and drain D
1-xGe
xSurface selectivity extension one deck silicon layer 34 of channel layer 16 occurs in the silicon layer 34 the metal silication reaction, and can not occur in Si
1-xGe
xChannel layer 16, as shown in figure 10.
The present invention proposes a kind of field-effect transistor structure with strain silicon germanium layer extension, as shown in Figure 7, is applicable to a silicon base 10, and this field-effect transistor structure has following assembly.First assembly is 14 layers of a silicon bufferings, uses the said method epitaxial growth on the active area of silicon base 10.
Second assembly is a strain Si
1-xGe
xChannel layer 16 uses the said method epitaxial growth on resilient coating 14, strain Si
1-xGe
xChannel layer 16 is under the biaxial compressive strain situation.
This field-effect transistor structure still also has following assembly: a gate insulator 22 is formed at strain Si
1-xGe
xOn the channel layer 16; One gate electrode 28 is formed on the gate insulator 22; And one source pole S and drain D, be formed at gate electrode 28 both sides.
Field-effect transistor structure with strain silicon germanium layer extension of the present invention also comprises silicon shoe cap rock 18, is formed at strain Si
1-xGe
xBetween channel layer 16 and the gate pole insulating barrier 22.
The present invention also proposes a kind of field-effect transistor structure with strain silicon germanium layer extension, as shown in Figure 8, is applicable to a silicon base 10, and this field-effect transistor structure has following assembly.First assembly is 14 layers of a silicon bufferings, uses the said method epitaxial growth on the active area of silicon base 10.
Second assembly is a strain Si
1-xGe
xChannel layer 16 uses the said method epitaxial growth on resilient coating 14, strain Si
1-xGe
xChannel layer 16 is under the biaxial compressive strain situation.
This field-effect transistor structure still has following assembly: a gate insulator 22 is formed at strain Si
1-xGe
xOn the channel layer 16; One gate electrode 28 is formed on the gate insulator 22; One source pole S and drain D are formed at gate electrode 28 both sides; And one metal suicide source and the drain electrode 32, be formed on the silicon buffer layer 14 of source S and drain D.
The present invention proposes a kind of field-effect transistor structure with strain silicon germanium layer extension again, as shown in Figure 9, is applicable to a silicon base 10, and this field-effect transistor structure has following assembly.First assembly is 14 layers of a silicon bufferings, uses the said method epitaxial growth on the active area of silicon base 10.
Second assembly is a strain Si
1-xGe
xChannel layer 16 uses the said method epitaxial growth on resilient coating 14, strain Si
1-xGe
xChannel layer 16 is under the biaxial compressive strain situation.
This field-effect transistor structure also has following assembly: a gate insulator 22 is formed at strain Si
1-xGe
xOn the channel layer 16; One gate electrode 28 is formed on the gate insulator 22; One source pole S and drain D are formed at gate electrode 28 both sides, and a metal suicide source and drain electrode 32, are formed in source S and the drain electrode.
The present invention also proposes a kind of field-effect transistor structure with strain silicon germanium layer extension, as shown in figure 10, be applicable to a silicon base 10, this field-effect transistor structure has following assembly: first assembly is 14 layers of a silicon bufferings, uses the said method epitaxial growth on the active area of silicon base 10.
Second assembly is a strain Si
1-xGe
xChannel layer 16 uses the said method epitaxial growth on resilient coating 14, strain Si
1-xGe
xChannel layer 16 is under the biaxial compressive strain situation.
This field-effect transistor structure also has following assembly: a gate insulator 22 is formed at strain Si
1-xGe
xOn the channel layer 16; One gate electrode 28 is formed on the gate insulator 22; One source pole S and drain D are formed at gate electrode 28 both sides; And a metal suicide source and a drain electrode 32, be formed at the strain Si of source S and drain D
1-xGe
xOn the channel layer 16.
Though the present invention discloses as above with preferred embodiment, but be not in order to restriction the present invention, any those skilled in the art, without departing from the spirit and scope of the present invention, the equivalent structure transformation of having done all is included in the claim of the present invention.
Claims (47)
1. the manufacture method with field-effect transistor of strain silicon germanium layer extension is characterized in that, comprises the following steps:
One silicon base is provided;
Epitaxial growth one silicon buffer layer and a strain Si on this silicon base
1-xGe
xChannel layer, wherein this strain Si
1-xGe
xChannel layer is under the biaxial compressive strain situation;
At this strain Si
1-xGe
xForm a gate insulator on the channel layer;
On this gate insulator, form a gate electrode; And
Form one source pole and drain electrode in these gate electrode both sides.
2. the manufacture method with field-effect transistor of strain silicon germanium layer extension as claimed in claim 1 is characterized in that, this strain Si
1-xGe
xChannel layer, wherein x is between 0.1 to 0.5.
3. the manufacture method with field-effect transistor of strain silicon germanium layer extension as claimed in claim 1 is characterized in that, this strain Si
1-xGe
xThe critical thickness of channel layer is 10nm.
4. the manufacture method with field-effect transistor of strain silicon germanium layer extension as claimed in claim 1 is characterized in that the thickness of this silicon buffer layer is less than 10nm.
5. the manufacture method with field-effect transistor of strain silicon germanium layer extension as claimed in claim 1 is characterized in that, this gate insulator is a silicon oxide layer.
6. the manufacture method with field-effect transistor of strain silicon germanium layer extension as claimed in claim 5 is characterized in that, the formation method of this gate insulator comprises:
At this strain Si
1-xGe
xForm a silicon layer on the channel layer; And
This silicon layer of oxidation makes the top layer of this silicon layer transfer this silicon oxide layer to.
7. the manufacture method with field-effect transistor of strain silicon germanium layer extension as claimed in claim 1 is characterized in that, the formation method of this gate insulator is to utilize chemical vapour deposition technique, at this strain Si
1-xGe
xDeposition one deck is selected from the set that aluminium oxide, hafnium oxide and zirconia form on the channel layer.
8. the manufacture method with field-effect transistor of strain silicon germanium layer extension as claimed in claim 1 is characterized in that, is included in before this silicon buffer layer of epitaxial growth, forms a fleet plough groove isolation structure in this silicon base.
9. the manufacture method with field-effect transistor of strain silicon germanium layer extension as claimed in claim 1 is characterized in that, also is included in to form after this source electrode and the drain electrode this strain Si in this source electrode and drain electrode
1-xGe
xThe metal silication reaction is carried out on the top layer of channel layer, to form a metal silicide.
10. the manufacture method with field-effect transistor of strain silicon germanium layer extension as claimed in claim 1 is characterized in that, also comprises forming after this source electrode and the drain electrode, removes this strain Si in this source electrode and the drain electrode
1-xGe
xChannel layer carries out the metal silication reaction, again to form a metal silicide.
11. the manufacture method with field-effect transistor of strain silicon germanium layer extension as claimed in claim 1 is characterized in that, also is included in to form after this source electrode and the drain electrode this strain Si of selective epitaxial one silicon layer in this source electrode and drain electrode
1-xGe
xThe metal silication reaction is carried out, again to form a metal silicide in the channel layer surface.
12. the manufacture method with field-effect transistor of strain silicon germanium layer extension as claimed in claim 1 is characterized in that, this silicon buffer layer of epitaxial growth and this strain Si
1-xGe
xChannel layer is to use the selective epitaxial method.
13. the manufacture method with field-effect transistor of strain silicon germanium layer extension as claimed in claim 1 is characterized in that, this silicon buffer layer of this epitaxial growth and this strain Si
1-xGe
xChannel layer comprises the following steps:
Use non-selective epitaxy method grow up this silicon buffer layer and this strain Si
1-xGe
xChannel layer; And
This silicon buffer layer and this strain Si of part removed in etching
1-xGe
xChannel layer and stay part on active area.
14. the manufacture method with field-effect transistor of strain silicon germanium layer extension is characterized in that, comprises the following steps:
One silicon base is provided;
Epitaxial growth three composite beds that do not mix on this silicon base, this three composite bed is by a silicon buffer layer, a strain Si
1-xGe
xA channel layer and a silicon covering layer are formed, wherein this strain Si
1-xGe
xChannel layer is under the biaxial compressive strain situation;
On this silicon covering layer, form a gate insulator;
On this gate insulator, form a gate electrode; And
Form one source pole and drain electrode in these gate electrode both sides.
15. the manufacture method with field-effect transistor of strain silicon germanium layer extension as claimed in claim 14 is characterized in that, this strain Si
1-xGe
xChannel layer, wherein x is between 0.1 to 0.5.
16. the manufacture method with field-effect transistor of strain silicon germanium layer extension as claimed in claim 14 is characterized in that, this strain Si
1-xGe
xThe critical thickness of channel layer is 10nm.
17. the manufacture method with field-effect transistor of strain silicon germanium layer extension as claimed in claim 14 is characterized in that the thickness of this silicon buffer layer is less than 10nm.
18. the manufacture method with field-effect transistor of strain silicon germanium layer extension as claimed in claim 14 is characterized in that, this gate insulator is a silicon oxide layer.
19. the manufacture method with field-effect transistor of strain silicon germanium layer extension as claimed in claim 14, it is characterized in that, the formation method of this gate insulator is to utilize chemical vapour deposition technique, and deposition one deck is selected from the set that aluminium oxide, hafnium oxide and zirconia form on this silicon covering layer.
20. the manufacture method with field-effect transistor of strain silicon germanium layer extension as claimed in claim 14 is characterized in that, is included in before this silicon buffer layer of epitaxial growth, forms a fleet plough groove isolation structure in this silicon base.
21. the manufacture method with field-effect transistor of strain silicon germanium layer extension as claimed in claim 14 is characterized in that, is included in to form after this source electrode and the drain electrode this strain Si in this source electrode and drain electrode
1-xGe
xThe metal silication reaction is carried out on the top layer of channel layer, to form a metal silicide.
22. the manufacture method with field-effect transistor of strain silicon germanium layer extension as claimed in claim 14 is characterized in that, is included in to form after this source electrode and the drain electrode, removes this strain Si in this source electrode and the drain electrode
1-xGe
xChannel layer carries out the metal silication reaction, again to form a metal silicide.
23. the manufacture method with field-effect transistor of strain silicon germanium layer extension as claimed in claim 14 is characterized in that, is included in to form after this source electrode and the drain electrode, selective epitaxial one silicon layer is this strain Si in this source electrode and drain electrode
1-xGe
xThe metal silication reaction is carried out, again to form a metal silicide in the channel layer surface.
24. the manufacture method with field-effect transistor of strain silicon germanium layer extension as claimed in claim 14 is characterized in that, this three composite bed of epitaxial growth is to use the selective epitaxial method.
25. the manufacture method with field-effect transistor of strain silicon germanium layer extension as claimed in claim 14 is characterized in that, this three composite bed of this epitaxial growth comprises the following steps:
Use non-selective epitaxy method this three composite bed of growing up; And
Etching is removed this three composite bed of part and is stayed part on active area.
26. the manufacture method with CMOS of strain silicon germanium layer extension comprises the following steps:
One silicon base is provided, and this substrate isolates active area by insulation and has a p-well area and a n-well area;
Epitaxial growth last doping three composite beds on this silicon base, this three composite bed are by a silicon buffer layer, a strain Si
1-xGe
xA channel layer and a silicon covering layer are formed, wherein this strain Si
1-xGe
xChannel layer is under the biaxial compressive strain situation;
On this silicon covering layer, form a gate insulator;
On this gate insulator, form a gate electrode;
Implement n type and p type ion doping to define a PMOS assembly and a NMOS assembly for this p-well area and n-well area; And
Form one source pole and drain electrode in these gate electrode both sides.
27. the manufacture method with CMOS of strain silicon germanium layer extension as claimed in claim 26 is characterized in that, this strain Si
1-xGe
xChannel layer, wherein x is between 0.1 to 0.5.
28. the manufacture method with CMOS of strain silicon germanium layer extension as claimed in claim 26 is characterized in that, this strain Si
1-xGe
xThe critical thickness of channel layer is 10nm.
29. the manufacture method with CMOS of strain silicon germanium layer extension as claimed in claim 26 is characterized in that the thickness of this silicon buffer layer is less than 10nm.
30. the manufacture method with CMOS of strain silicon germanium layer extension as claimed in claim 26 is characterized in that, this gate insulator is a silicon oxide layer.
31. the manufacture method with field-effect transistor of strain silicon germanium layer extension as claimed in claim 30 is characterized in that, the formation method of this gate insulator is this silicon covering layer of thermal oxidation, makes the top layer of this silicon covering layer transfer this silicon oxide layer to.
32. the manufacture method with CMOS of strain silicon germanium layer extension as claimed in claim 26 is characterized in that, before this silicon buffer layer of epitaxial growth, also is included in the step that forms a fleet plough groove isolation structure in this silicon base.
33. the manufacture method with CMOS of strain silicon germanium layer extension as claimed in claim 26 is characterized in that, also is included in to form after this source electrode and the drain electrode this strain Si in this source electrode and drain electrode
1-xGe
xThe metal silication reaction is carried out on the top layer of channel layer, to form a metal silicide.
34. the manufacture method with CMOS of strain silicon germanium layer extension as claimed in claim 26 is characterized in that, more is included in to form after this source electrode and the drain electrode, removes this strain Si in this source electrode and the drain electrode
1-xGe
xChannel layer carries out the metal silication reaction, again to form a metal silicide.
35. the manufacture method with CMOS of strain silicon germanium layer extension as claimed in claim 26 is characterized in that, also is included in to form after this source electrode and the drain electrode this strain Si of selective epitaxial one silicon layer in this source electrode and drain electrode
1-xGe
xThe metal silication reaction is carried out, again to form a metal silicide in the channel layer surface.
36. the manufacture method with CMOS of strain silicon germanium layer extension as claimed in claim 26 is characterized in that, this three composite bed of epitaxial growth is to use the selective epitaxial method.
37. the manufacture method with CMOS of strain silicon germanium layer extension as claimed in claim 26 is characterized in that, this three composite bed of this epitaxial growth comprises the following steps:
Use non-selective epitaxy method this three composite bed of growing up; And
Etching is removed this three composite bed of part and is stayed part on active area.
38. the field-effect transistor structure with strain silicon germanium layer extension is applicable to a silicon base, it is characterized in that, comprising:
One silicon buffer layer, epitaxial growth is on the active area of this silicon base;
One strain Si
1-xGe
xChannel layer, epitaxial growth on this resilient coating, this strain Si wherein
1-xGe
xChannel layer is under the biaxial compressive strain situation;
One gate insulator is formed at this strain Si
1-xGe
xOn the channel layer;
One gate electrode is formed on this gate insulator; And
One source pole and drain electrode are formed at this gate electrode both sides.
39. the field-effect transistor structure with strain silicon germanium layer extension as claimed in claim 38 is characterized in that, this strain Si
1-xGe
xChannel layer, wherein x is between 0.1 to 0.5.
40. the field-effect transistor structure with strain silicon germanium layer extension as claimed in claim 38 is characterized in that, this strain Si
1-xGe
xThe critical thickness of channel layer is 10nm.
41. the field-effect transistor structure with strain silicon germanium layer extension as claimed in claim 38 is characterized in that the thickness of this silicon buffer layer is less than 10nm.
42. the field-effect transistor structure with strain silicon germanium layer extension as claimed in claim 38 is characterized in that, this gate insulator is a silicon oxide layer.
43. the field-effect transistor structure with strain silicon germanium layer extension as claimed in claim 38 is characterized in that, this gate insulator is selected from the set that aluminium oxide, hafnium oxide and zirconia form.
44. the field-effect transistor structure with strain silicon germanium layer extension as claimed in claim 38 is characterized in that, also comprises a silicon covering layer, is formed at this strain Si
1-xGe
xBetween channel layer and this gate insulator.
45. the field-effect transistor structure with strain silicon germanium layer extension is applicable to a silicon base, it is characterized in that, comprising:
One silicon buffer layer, epitaxial growth is on the active area of this silicon base;
One strain Si
1-xGe
xChannel layer, epitaxial growth on this resilient coating, this strain Si wherein
1-xGe
xChannel layer is under the biaxial compressive strain situation;
One gate insulator is formed at this strain Si
1-xGe
xOn the channel layer;
One gate electrode is formed on this gate insulator;
One source pole and drain electrode are formed at this gate electrode both sides; And
One metal silicide layer is formed on this silicon buffer layer of this source electrode and drain electrode.
46. the field-effect transistor structure with strain silicon germanium layer extension is applicable to a silicon base, it is characterized in that, comprising:
One silicon buffer layer, epitaxial growth is on the active area of this silicon base;
One strain Si
1-xGe
xChannel layer, epitaxial growth on this resilient coating, this strain Si wherein
1-xGe
xChannel layer is under the biaxial compressive strain situation;
One gate insulator is formed at this strain Si
1-xGe
xOn the channel layer;
One gate electrode is formed on this gate insulator;
One source pole and drain electrode are formed at this gate electrode both sides; And
One metal silicide layer is formed in this source electrode and the drain electrode.
47. the field-effect transistor structure with strain silicon germanium layer extension is applicable to a silicon base, it is characterized in that, comprising:
One silicon buffer layer, epitaxial growth is on the active area of this silicon base;
One strain Si
1-xGe
xChannel layer, epitaxial growth on this resilient coating, this strain Si wherein
1-xGe
xChannel layer is under the biaxial compressive strain situation;
One gate insulator is formed at this strain Si
1-xGe
xOn the channel layer;
One gate electrode is formed on this gate insulator;
One source pole and drain electrode are formed at this gate electrode both sides; And
One metal silicide layer is formed at this strain Si of this source electrode and drain electrode
1-xGe
xOn the channel layer.
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|---|---|---|---|
| CN 03107972 CN1277296C (en) | 2003-03-27 | 2003-03-27 | Field effect transistor structure possessing strain silicon germanium layer beaping crystal and its manufacturing method |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 03107972 CN1277296C (en) | 2003-03-27 | 2003-03-27 | Field effect transistor structure possessing strain silicon germanium layer beaping crystal and its manufacturing method |
Publications (2)
| Publication Number | Publication Date |
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| CN1534744A CN1534744A (en) | 2004-10-06 |
| CN1277296C true CN1277296C (en) | 2006-09-27 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
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| CN (1) | CN1277296C (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7932146B2 (en) | 2008-03-20 | 2011-04-26 | United Microelectronics Corp. | Metal gate transistor and polysilicon resistor and method for fabricating the same |
| CN101552229B (en) * | 2008-03-31 | 2012-04-11 | 联华电子股份有限公司 | Semiconductor element and manufacturing method thereof |
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| JP5096681B2 (en) | 2006-02-21 | 2012-12-12 | ルネサスエレクトロニクス株式会社 | Manufacturing method of semiconductor device |
| CN103378001B (en) * | 2012-04-23 | 2016-06-29 | 中芯国际集成电路制造(上海)有限公司 | The forming method of the Graphene of patterning |
| CN102738156B (en) * | 2012-07-16 | 2016-03-30 | 西安电子科技大学 | A kind of SiGe base vertical-channel strain BiCMOS integrated device and preparation method |
| CN102800672B (en) * | 2012-07-16 | 2015-01-21 | 西安电子科技大学 | Strain SiGe HBT (Heterojunction Bipolar Transistor) vertical channel BiCMOS integrated device and preparation method thereof |
| US8624324B1 (en) * | 2012-08-10 | 2014-01-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Connecting through vias to devices |
| US8872225B2 (en) * | 2012-12-20 | 2014-10-28 | Intel Corporation | Defect transferred and lattice mismatched epitaxial film |
| CN105329844B (en) * | 2014-07-22 | 2017-07-14 | 中芯国际集成电路制造(上海)有限公司 | The forming method of MEMS |
| US9431536B1 (en) * | 2015-03-16 | 2016-08-30 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device structure with raised source/drain having cap element |
| CN104992930A (en) * | 2015-07-07 | 2015-10-21 | 西安电子科技大学 | Strain Ge CMOS integrated device preparation method and CMOS integrated device |
| CN105244320A (en) * | 2015-08-28 | 2016-01-13 | 西安电子科技大学 | SOI-based CMOS integrated device with strain Ge channel and inverted trapezoidal grid and preparation method of integrated device |
| CN105118809A (en) * | 2015-08-28 | 2015-12-02 | 西安电子科技大学 | Strain Ge groove-type gate CMOS (Complementary Metal Oxide Semiconductor) integrated device manufacturing method and CMOS integrated device thereof |
-
2003
- 2003-03-27 CN CN 03107972 patent/CN1277296C/en not_active Expired - Lifetime
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7932146B2 (en) | 2008-03-20 | 2011-04-26 | United Microelectronics Corp. | Metal gate transistor and polysilicon resistor and method for fabricating the same |
| CN101552229B (en) * | 2008-03-31 | 2012-04-11 | 联华电子股份有限公司 | Semiconductor element and manufacturing method thereof |
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| Publication number | Publication date |
|---|---|
| CN1534744A (en) | 2004-10-06 |
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