CN1276582C

CN1276582C - CMOS I/O offset control circuit

Info

Publication number: CN1276582C
Application number: CN 200310114561
Authority: CN
Inventors: 徐平
Original assignee: Xiamen UX High Speed IC Co Ltd
Current assignee: Xiamen UX High Speed IC Co Ltd
Priority date: 2003-12-26
Filing date: 2003-12-26
Publication date: 2006-09-20
Anticipated expiration: 2023-12-26
Also published as: CN1599248A

Abstract

The present invention provides a CMOS I/O offset control circuit. The present invention can be worked under the source voltage of 3V, 5V or any source voltage within 3V and 5V without structure adjustment. The present invention is composed of a current source and three amplifiers. Under the different operation and process condition, such as a quick transistor process and environment temperature change or supply voltage change, constant current can be provided. The present invention commonly provides two offset signals for promoting a CMOS transistor I/O.

Description

A kind of CMOS I/O bias control circuit

Technical field

The present invention relates to a kind of CMOS I/O bias control circuit, especially a kind of CMOS I/O bias control circuit that does not require specific input voltage (for example, 3V or 5V all can).

Background technology

CMOS I/O bias control circuit all required to work under specific voltage in the past, and people expect to have a kind of biasing circuit, and the structure that need not to change circuit just can be worked under 3V or these two kinds of supply voltages of 5V.Also be desirably under the situation of supply voltage, ambient temperature and course of work wide variation, the output of this biasing circuit still has constant rising and fall time (1-2V/ns).

Biasing circuit uses the technology formerly of fixing 5V input voltage Vcc, referring to Fig. 1 (U.S. Patent number: 4978905).Generally by a reference circuit and output reference voltage of several transistor for generating.Its major defect is to work under the 3V input voltage, works in the time of can only be at 5V or greater than 5V.In addition, its linear working range can only be from 4.5V to 6.5V, and when circuit was in noise circumstance, anti-power supply jamming rate was low, and the noise of power supply may directly be injected in the circuit, makes it to produce strong shake.Its DC performance Vs, Vcc are shown in Fig. 4, therefrom as seen just quit work during less than 4V as Vcc.

Summary of the invention

Purpose of the present invention aims to provide a kind of CMOS I/O bias control circuit that does not require specific input voltage (for example, 3V or 5V all can).

Purpose of the present invention aims to provide a kind of under the situation of supply voltage, ambient temperature and course of work wide variation, and output still has the CMOS I/O bias control circuit of constant rising and fall time.

A kind of CMOS I/O bias control circuit comprises:

Produce the current source 12 of first output, connect Input voltage terminal, and its output current substantially constant;

Produce first amplifier 14 of second output, connect described current source 12, connect described first output 24, and this second output there is a gain with respect to first output;

Produce second amplifier 16 of the first biasing output, connect described second output 30;

And produce the 3rd amplifier 18 that second biasing is exported, connect the described first biasing output 37, and described first, second biasing output when being 2.7 volts to 7.0 volts scope, input voltage is linear.

The scope of described input voltage is 3 volts to 5 volts.

Described current source comprises a reference circuit, and described reference circuit comprises:

P transistor npn npn M1, its grounded-grid, source electrode connects Input voltage terminal, and its drain electrode provides described first output;

P transistor npn npn M2, its source electrode connects input voltage, and drain electrode connects the drain electrode of described transistor M1;

N transistor npn npn M3, its grid, drain electrode connect the drain electrode of described transistor M1;

N transistor npn npn M4, its grid, drain electrode connect the source electrode of described transistor M3, its source ground;

P transistor npn npn M8, its source electrode connects described Input voltage terminal, and grid, drain electrode connect the grid of described transistor M2;

N transistor npn npn M9, its drain electrode connects the drain electrode of described transistor M8, and its grid connects the drain electrode of described crystal M2;

One resistance R 8, the source electrode of the described transistor M9 of one termination, other end ground connection;

Also comprise a feedback circuit, it inserts described reference circuit.

Described feedback circuit comprises:

N transistor npn npn MN3, its drain electrode connects described Input voltage terminal, and its grid connects the grid of the transistor M8 of described reference circuit;

Resistance R mn3, the one end is connected with the source electrode of described transistor MN3, other end ground connection;

P transistor npn npn MP1, its grid is connected with the source electrode of described transistor MN3;

Resistance R x2, its two ends all are connected with the source electrode of described transistor MP1;

Resistance R mpd, the end of the described resistance R x2 of one termination, the described input voltage of another termination;

Resistance R x, the drain electrode of the described transistor MP1 of a termination, other end ground connection;

Transistor MR8, its grid connects the drain electrode of described transistor MP1, and its drain electrode, source electrode are connected to described resistance R 8 two ends, and source ground.

Described first amplifier comprises a plurality of transistors

Described first amplifier comprises:

P transistor npn npn M10, its source electrode connects described input voltage, and grid connects the grid of the transistor M8 of reference current in the described current source;

N transistor npn npn M11, its drain electrode, grid are connected with the drain electrode of described transistor M10, and the drain electrode of described transistor M10 output is described second output;

And N transistor npn npn M12, its drain electrode is connected with the source electrode of described transistor M11, and its grid is connected its source ground with described first output;

Described second amplifier comprises:

P transistor npn npn M13, its source electrode connects described Input voltage terminal, its grounded-grid;

P transistor npn npn M14, its source electrode is connected with the drain electrode of described transistor M13;

And N transistor npn npn M15, its grid is connected with described second output, and its drain electrode is connected with grid, the drain electrode of described transistor M14 and provides described first biasing to export its source ground;

Described the 3rd amplifier comprises:

P transistor npn npn M17, its grid is connected with the described first biasing output, and drain electrode provides the described second biasing output, and its source electrode connects described Input voltage terminal;

One resistance R 17, the one end is connected with the drain electrode of described transistor M17;

N transistor npn npn M18, its grid, drain electrode are connected its source ground with the other end of described resistance R 17.

The invention provides a kind of CMOS I/O bias control circuit, can under 3V, 5V or any power source voltage in this is interval, work and need not to carry out the adjustment of structure.The present invention is made of a current source and three amplifiers.Require in the design: under different operations and process condition, variation of ambient temperature or mains voltage variations as often occurring in the quick transistor process can provide constant electric current.This biasing circuit can adapt to above change condition.This biasing circuit generally provides two offset signals, can be used for promoting CMOS transistor I/O.

Object of the present invention, characteristics and advantage are a kind of CMOS I/O bias control circuit, can work under 3V, 5V or other power supplys in the 2.7-7V voltage range, and keep the constant rise or fall time.This biasing has the ability that the variation to voltage, temperature and process compensates, and remains low noise, high anti-power supply jamming rate and low jitter.

Description of drawings

Below in conjunction with drawings and Examples the present invention is further described:

Fig. 1 is the circuit diagram of the biasing circuit of technology formerly;

Fig. 2 is a circuit diagram of the present invention;

Fig. 3 is that the present invention exports the partial circuit figure that is driven;

Fig. 4 is the relation curve of technology biasing circuit Obref and Vcc formerly;

Fig. 5 is the relation curve of circuit Obrefn of the present invention, Obrefp and Vcc.

Embodiment

With reference to circuit 10 shown in Figure 2, imbody circuit connecting relation of the present invention, circuit 10 by baseline current-source 12, first amplifier 14, second amplifier 16 and the 3rd amplifier 18 totally four parts form.First end of the source electrode of the source electrode of the source electrode of the source electrode of transistor M1, transistor M2, transistor M8, transistor MN3 and resistance R mpd all is connected to input voltage Vcc.Defeated people's voltage vcc also appears on the input 20 of first amplifier 14.The grounded-grid of transistor M1.The grid of transistor M2 is connected to grid and the drain electrode of transistor M8, is also connected to the drain electrode of transistor M9.Transistor M9 is used to form feedback network TOUT2.Feedback network TOUT2 has improved the temperature of current source and the performance of the course of work, makes that output is more stable and constant.

The drain electrode that the drain electrode of transistor M2 is connected to transistor M1 forms a current source node A1.Current source node A1 is connected to the grid of transistor M9, and the drain and gate of transistor M3 equally also appears in first amplifier 14, and the source electrode of transistor M3 is connected to the drain and gate of transistor M4.The source ground of transistor M4.The source electrode of transistor M9 is received the drain electrode of transistor MR8, and an end of resistance R 8 is also received in the drain electrode of MR8.The other end of resistance R 8 is connected to the source electrode of transistor MR8, and ground connection together.The grid of transistor MR8 is received the drain electrode of transistor MP1, also receives the end of resistance R x.The other end ground connection of resistance R X.The grid of MN3 is connected to electric capacity Mx one end, and the grid of transistor MP1 is connected to the source electrode of transistor MN3, also receives the end of resistance R mn3.The other end ground connection of resistance R mn3.The source electrode of transistor MP1 is connected to the two ends of resistance R x2, and first end and second end have also connected first end of resistance R mpd.Second end of resistance R mpd is connected to first amplifier input terminal 20.The drain electrode of transistor MN3 is connected to the input 20 of first amplifier 14, and grid connects the grid of M8.

Transistor M1-M4, M8, M9 and resistance R 8 are formed the first of reference circuit, are similar to technology formerly.The first of reference circuit when changing as the course of work, temperature and power supply, provides the low-tension current of quite stable under the condition that is restricted.Add the compensation of the feedback circuit of forming by transistor MN3, MP1 and MR8 and resistance R mn3, Rx, Rx2 and Rmpd, even under the situation of the course of work, temperature and power supply generation wide variation, can also produce stable electric current.Particularly under higher temperature, electric current is descended, feedback circuit can compensate this influence.For example, in the fast course of work, when the voltage on the transistor MR8 grid reduced, the electric current by resistance R 8 can increase, and output 22 is raise.Thereby the electric current of transistor MR8 descends, and the result makes the total current by transistor M8 keep constant.Generally speaking, be the gain of restriction feedback control loop, the size of transistor MR8 remains on minimum.

First amplifier 14 is made up of transistor M10, transistor M11 and transistor M12.The input voltage Vcc of input 20 is connected to the source electrode of transistor M10 and the input 26 of second amplifier 16, and is connected with the 3rd amplifier 18 at input 28.The source electrode that the drain electrode of transistor M10 is connected to transistor M11 is connected with grid and with the input 30 of second amplifier 16, and grid connects the grid of transistor M8.The drain electrode of transistor M11 is connected to the drain electrode of transistor M12, the source ground of transistor M12 and the grid of transistor M12 connects input 24.

Transistor M12 is subjected to the biasing of current source node A1, so just significantly reduced since the variation of input voltage Vcc to the influence of circuit 10.In addition, also increased the range of linearity of circuit 10.The electric current that transistor M10 produces is constant substantially, and transistor M12 is as constant active load, to increase the gain of amplifier 14.The gate bias of transistor M12 connects current source node A1.Therefore directly do not concern between transistor M12 and the input voltage Vcc.The result has realized having high anti-power supply jamming rate and big linear working range when input voltage Vcc wide variation.Transistor M12 has positive temperature coefficient in its work, the result is the signal that produces on first amplifier 14 negative temperature coefficient of having proofreaied and correct current node 8 (being exactly under the higher temperature, to produce lower electric current) and the node 9.The signal that produces on the node 9 appears on the input 30 of second amplifier 16.In addition, the signal of node 9 generations is self-compensating to the variation of the course of work, temperature and power supply.

Second amplifier 16 is made up of transistor M13, transistor M14, transistor M15 and a transistor capacitance device 36.The source electrode of transistor M13 is accepted the input voltage Vcc of input 26, the grounded-grid of transistor M13, and the drain electrode of transistor M13 connects the source electrode of transistor M14.The drain and gate of transistor M14 connects together and receives the drain electrode of transistor M15.The grid of transistor M14 is received the 3rd amplifier input terminal 32 and the output of an Obrefn is provided.The grid of transistor M15 is accepted the signal from input 30.The source ground of transistor M15.The source electrode of transistor capacitance device 36 and the drain electrode ground connection that connects together.The grid of transistor 36 is received output and is added Obrefn.

Transistor M13-M15 will amplify from the second level of input 30 acknowledge(ment) signals.Transistor M15 adopts the current mirror effect to produce a constant electric current.Generally speaking, when transistor M13 worked with linear model, transistor M14 and M15 were then with saturation mode work.Under different temperature, voltage and the course of work, can change across the source electrode of transistor M13 and the voltage of drain electrode, and guaranteed that transistor M14 and M15 can work under saturation mode, can export constant current.Therefore the voltage Obrefn of output 37 can play regulating action to the variation of input voltage Vcc, temperature and the course of work.Voltage Obrefn can provide and stable bias voltage for a transistor current source.

Third level amplifier 18 is made of transistor M17, transistor M18 and resistance R 17.The source electrode of transistor M17 connects input 28, to accept input voltage Vcc.The source electrode of transistor M17 is also received output 38.The drain electrode of transistor M17 is received first end of resistance R 17 and is received output 40.Second end of resistance R 17 and the drain and gate of transistor M18 join.The source ground of transistor M18.The grid of transistor M17 is accepted the signal from input 32.Output 40 signal of an Obrefp occurs and is coupled to the grid of transistor capacitance device 42.The source electrode and the drain electrode of transistor 42 meet Vcc.

A complementary voltage ObrefP results from the 3rd amplifier 18.Transistor M17, transistor M18 and resistance R 17 produce a back biased voltage Obrefp by the voltage Obrefn on the input 32.Bias voltage Obrefp also isolates mutually with input voltage Vcc, thereby has improved anti-power supply jamming rate.Bias voltage Obrefp provides the bias voltage of stabilizer pole for the NMOS current source.Under fast course of work condition, when bias voltage Obrefp shifted to ground, bias voltage Obrefn shifted to input voltage Vcc.Their cooperation the pulling on and leaving behind of connected transistor circuit of can slowing down, thus too fast conversion prevented.In addition, when other conditions changed, bias voltage Obrefp and Obrefn can corresponding adjusting transistor circuit make it speed-raising or deceleration, make the constant airspeed of change in voltage, and this will reduce noise widely.

Fig. 3 is a typical output buffer 50, and it is a kind of application of the

present invention.Transistor

58,60,64 draws predriver on forming one, and

transistor

61,66,68 is formed a drop-

down predriver.Transistor

62,70 is a driver.First inverter 54 and second inverter 56 are from input 52 acknowledge(ment) signals.The output termination transistor 58 of first inverter 54 and the canopy of transistor 60 are extremely gone up.On the source electrode of the source electrode of input voltage Vcc connection transistor 58, the source electrode of transistor 61 and transistor 62.The drain electrode of transistor 58 is connected with the drain electrode of transistor 60, is also connected to the grid of transistor 62.The source electrode of transistor 60 is connected to the drain electrode of transistor 64.The grid of transistor 64 is accepted the Obrefp signal from output 40.The source ground of transistor 64.The output of second inverter is received the grid of transistor 66 and transistor 68.The source electrode of transistor 66 is received the drain electrode of transistor 61.The drain electrode of the drain electrode of transistor 66 and transistor 68 links together and connects the grid of transistor 70.The source ground of transistor 68.The grid of transistor 61 is accepted from the Obrefn signal on the output 37 of second amplifier 16.The drain electrode of the drain electrode of transistor 62 and transistor 70 links together, and receives output 72.The source ground of transistor 70.Output 72 is by load capacitor 74 ground connection.

Formerly the relation curve of technology circuit Obref and Vcc is shown in Fig. 4, is respectively-55 ℃, 25 ℃, 155 ℃ temperature, and what transverse axis (VOL IS) was represented is input voltage, and what the longitudinal axis (VOLT LIN) was represented is output voltage.The relation curve of Obrefn of the present invention, Orefp and Vcc is shown in Fig. 5, be respectively-35 ℃, 100 ℃, 25 ℃ three kinds of temperature, wherein transverse axis (VOL IS) expression is input voltage, what the longitudinal axis (VOLTLIN) was represented is output voltage, as seen when Vcc almost was lower than 4 volts, formerly the biasing circuit of technology had not just been worked.

The above, only for preferred embodiment of the present invention, so can not limit scope of the invention process with this, i.e. the equivalence of doing according to the present patent application claim and description changes and modification, all should still belong in the scope that patent of the present invention contains.

Claims

1. CMOS I/O bias control circuit is characterized in that: comprising:

Produce the current source (12) of first output, connect Input voltage terminal, and its output current substantially constant;

Produce first amplifier (14) of second output, connect first output (24) of described current source (12), and this second output there is a gain with respect to first output;

Produce second amplifier (16) of the first biasing output, connect described second output (30);

And produce the 3rd amplifier (18) that second biasing is exported, connect the described first biasing output (37), and described first, second biasing output when being 2.7 volts to 7.0 volts scope, input voltage is linear;

N transistor npn npn M9, its drain electrode connects the drain electrode of described transistor M8, and its grid connects the drain electrode of described transistor M2;

Resistance R 8, the source electrode of the described transistor M9 of one termination, other end ground connection;

Described current source also comprises a feedback circuit, and it inserts described reference circuit:

Described feedback circuit comprises:

N transistor npn npn MN3, its drain electrode connects described Input voltage terminal, and grid connects the grid of described reference circuit transistor M8;

N transistor npn npn MR8, its grid connects the drain electrode of described transistor MP1, and its drain electrode, source electrode are connected to described resistance R 8 two ends, and source ground;

Described first amplifier comprises:

P transistor npn npn M10, its source electrode connects described input voltage, and its grid connects the grid of the transistor M8 of reference circuit in the described current source;

Described second amplifier comprises:

Described the 3rd amplifier comprises:

2. CMOSI/O bias control circuit according to claim 1 is characterized in that: the scope of described input voltage is 3 volts to 5 volts.