CN1274104C - Circuit driving circuit with precision relay rate control - Google Patents
Circuit driving circuit with precision relay rate control Download PDFInfo
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- CN1274104C CN1274104C CN 200310120672 CN200310120672A CN1274104C CN 1274104 C CN1274104 C CN 1274104C CN 200310120672 CN200310120672 CN 200310120672 CN 200310120672 A CN200310120672 A CN 200310120672A CN 1274104 C CN1274104 C CN 1274104C
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- operational amplifier
- line drive
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Abstract
The present invention relates to a line-driving circuit under precision relay rate control, which comprises a delay rate control circuit, a first driving circuit and a second driving circuit, wherein the delay rate control circuit is used for controlling the delay rate, and the delay rate control circuit comprises a first operational amplifier and a second operational amplifier; the first driving circuit is used for driving output signals, and the first driving circuit comprises a first current source, a second current source, a first converter and a second converter; the second driving circuit is used for setting the slope of turning state, and the second driving circuit comprises a capacitor, a third current source, a fourth current source, a third converter and a fourth converter.
Description
Technical field
The present invention relates to a kind of line drive circuit, particularly relate to a kind of line drive circuit that can accurately control output delay of output signal rate or waveform.
Background technology
Along with the increase of computer network and data communication demand, the transmission technology of data is existing great progress under the help of communication system, signal processing and very lagre scale integrated circuit (VLSIC) (VLSI) technology.The appearance of very lagre scale integrated circuit (VLSIC) allows more digital processing system and analog front-end assembly can be integrated in the one chip, makes price more competitive.Because analog front-end assembly is integrated in the digital circuit, thus also must adopt lower supply-voltage source, to adapt to very large scale integration technology dwindling on entity size.Along with the reduction of supply-voltage source, the problem that service speed, signal swing and the linearity (linearity) etc. that satisfy analog circuit simultaneously have conflict property becomes quite difficulty.
General communication system is to carry out the transmission of data by a transceiver (transceiver), comprise a line drive circuit (line driver) in the transceiver, be used for output signal is sent in the load that comprises capacitive character and ohmic different impedances, line drive circuit also will be kept the transmission of high linearity simultaneously.Therefore, line drive circuit need possess the driving force that adapts to various impedance load, and reduces rank ripple distortion as best one can.Moreover line drive circuit must guarantee that track to track (rail-to-rail) common mode range of output signal and output voltage swing are all between an acceptable dynamic range.For the output signal that adapts to line drive circuit for track to track output voltage swing and High Output Current demand to electrostatic current (quiescent current) ratio; line drive circuit can be used complementary AB class output stage usually; common AB class output stage is used two complementary and (head-to-tail) transistors of connecting end to end, guides out a level and move between the grid voltage of output transistor.Another method that is expected to improve the line drive circuit characteristic is to adjust electrostatic current, make speed and power can reach best balance, and don't need redesign circuit partly, for example utilize time sequence information to come detection signal to hand over more and corresponding compensated for electrostatic stream by the output signal conversion.
From the above, it is online that transceiver outputs to transmission by line drive circuit with signal, so transceiver is for output delay of output signal rate (slew rate), rise time, fall time of line drive circuit all certain restriction being arranged.Because the loading range that line drive circuit allows is very big, if generally do not do retardation rate control, often under the situation of unknown load, add operation, power supply, variation of temperature, output signal almost is unlikely satisfactory specification.On the other hand, though the method for retardation rate control all can be used in most line drive circuit, but it is too complicated that the shortcoming of most line drive circuit maximum is exactly a circuit, though or have and improve but retardation rate is still uncontrollable quite accurate, and some method electric current that need mate, so variation of output signals also can be bigger.
Summary of the invention
Therefore main purpose of the present invention is to provide a kind of circuit structure simple and can accurately control the line drive circuit of output signal, to address the above problem.
A kind of line drive circuit of accurate retardation rate control is provided in the preferred embodiment of the present invention, and it comprises a retardation rate control circuit, is used for the control lag rate; One first drive circuit is used for drive output signal; And one second drive circuit, be used for setting the transition slope.
This retardation rate control circuit comprises one first operational amplifier, and it comprises a positive input terminal, a negative input end, and an output; And one second operational amplifier, it comprises the positive input terminal that a positive input terminal connects this first operational amplifier, and a negative input end connects the negative input end of this first operational amplifier, and an output.
This first drive circuit comprises one first current source, it comprises one first end and connects a voltage source, one second end connects the positive input terminal of this first operational amplifier, and a control end connects output or this voltage source of this first operational amplifier via one first switch; One second current source, it comprises the positive input terminal that one first end connects this second operational amplifier, and one second end connects an earth terminal, and a control end connects output or this earth terminal of this second operational amplifier via one second switch.
This second drive circuit comprises an electric capacity, and it comprises the negative input end that one first end connects this first operational amplifier, and one second end connects this earth terminal; One the 3rd current source, it comprises one first end and connects this voltage source, and one second end connects first end of this electric capacity, and a control end connects one first bias voltage signal source or this voltage source via one the 3rd switch; And one the 4th current source, it comprises first end that one first end connects this electric capacity, and one second end connects this earth terminal, and a control end connects one second bias voltage signal source or this earth terminal via one the 4th switch.
Description of drawings
Fig. 1 is the calcspar of line drive circuit of the present invention;
Fig. 2 is the circuit diagram of line drive circuit of the present invention;
Fig. 3 is the schematic diagram of the emulated data of line drive circuit of the present invention; With
Fig. 4 is the schematic diagram of the generation circuit in bias voltage signal source among Fig. 1.
The schematic symbol explanation
10 line drive circuit, 12 first drive circuits
14 retardation rate control circuits, 16 second drive circuits
24 the one PMOS transistors, 26 first nmos pass transistors
36 first operational amplifiers, 38 second operational amplifiers
40 first electric capacity, 42 first resistance
44 second resistance, 46 second electric capacity
48 electric capacity 50 the 2nd PMOS transistor
52 second nmos pass transistors
S1 first switch S 2 second switches
S3 the 3rd switch S 4 the 4th switch
S5 the 5th switch S 6 the 6th switch
The S7 minion is closed the S8 octavo and is closed
Embodiment
Please refer to Fig. 1, Fig. 1 is the calcspar of line drive circuit 10 of the present invention.Line drive circuit 10 comprises three parts, is respectively one first drive circuit 12, a retardation rate control circuit 14 and one second drive circuit 16.The output of line drive circuit 10 (OUT) connects the load (figure does not show) an of the unknown, the output signal 20 of meeting disturbing line drive circuit 10, and in addition, the instability of variation of temperature and voltage source also all can cause interference to output signal 20.For the output signal 20 that makes line drive circuit 10 meets a predetermined specification, and be not subjected to the influence of various interference, at first according to should predetermined specification designing second drive circuit 16, second drive circuit 16 connects one first bias voltage signal source (PBIAS) and one second bias voltage signal source (NBIAS), wherein first bias voltage signal is from a bias voltage PMOS transistor, second bias voltage signal is from a bias voltage nmos pass transistor, and two bias generators just are all, and this part will be described further at Fig. 4.Second drive circuit 16 produces output signal 18 according to two bias voltage signals, can adjust the transition slope of output signal 18 by the components values of setting second drive circuit 16; Moreover, the output signal 20 of first drive circuit 12 is the output signal 20 of line drive circuit 10, because first drive circuit 12 and retardation rate control circuit 14 are connected to a negative feedback loop, the output signal 20 of first drive circuit 12 can be passed back retardation rate control circuit 14, retardation rate control circuit 14 can compare the output signal 20 of first drive circuit 12 and the output signal 18 of second drive circuit 16 in real time, and output control signal 22 to first drive circuits 12, force the transition slope of output signal 20 of first drive circuit 12 identical with the transition slope of the output signal 18 of second drive circuit 16.Therefore, no matter the load that the output of line drive circuit 10 connects why, the output signal 20 of first drive circuit 12 all can be followed the output signal 18 of second drive circuit 16, makes the output signal 20 of line drive circuit 10 meet this predetermined specification.
Please refer to Fig. 2, Fig. 2 is the circuit diagram of line drive circuit 10 of the present invention.Contrast Fig. 1 and Fig. 2, wherein, first drive circuit 12 comprises one the one PMOS transistor 24, one first nmos pass transistor 26, first switch S 1, second switch S2, the 3rd switch S 3 and the 4th switch S 4; Retardation rate control circuit 14 comprises one first operational amplifier 36, one second operational amplifier 38, one first electric capacity 40, one first resistance 42, one second electric capacity 46 and one second resistance 44; Second drive circuit 16 comprises an electric capacity 48, one the 2nd PMOS transistor 50, one second nmos pass transistor 52, one the 5th switch S 5, one the 6th switch S 6, a minion closes S7 and octavo is closed S8.The source electrode of the one PMOS transistor 24 connects a voltage source (Vdd), and drain electrode connects the positive input terminal of first operational amplifier 36, and grid can connect the output that S1 is connected to first operational amplifier 36 via first switch, or connects voltage source via second switch S2.The drain electrode of first nmos pass transistor 26 connects the positive input terminal of second operational amplifier 38, and source electrode connects an earth terminal, and grid can connect earth terminal via the 3rd switch S 3, or connects the output of second operational amplifier 38 via the 4th switch S 4.First electric capacity 40 and 42 series connection of first resistance are connected between the positive input terminal and output of first operational amplifier 36, as the frequency compensation of first operational amplifier 36.Second electric capacity 46 and 44 series connection of second resistance are connected between the positive input terminal and output of second operational amplifier 38, as the frequency compensation of second operational amplifier 38.The positive input terminal of first operational amplifier 36 is connected with the positive input terminal of second operational amplifier 38, and the negative input end of first operational amplifier 36 is connected with the negative input end of second operational amplifier 38.First end of electric capacity 48 connects the negative input end of first operational amplifier 36, and second end connects earth terminal.The source electrode of the 2nd PMOS transistor 50 connects voltage source, and drain electrode connects first end of electric capacity 48, and grid can connect the first bias voltage signal source via the 5th switch S 5, or connects voltage source via the 6th switch S 6.The drain electrode of second nmos pass transistor 52 connects first end of electric capacity 48, and source electrode connects earth terminal, and grid can close S7 via minion and connect earth terminal, or connects the second bias voltage signal source via octavo pass S8.
Please refer to Fig. 3, Fig. 3 is the schematic diagram of the emulated data of line drive circuit 10 of the present invention.Requirement for different size, can adjust the transition slope of output signal by the size of the output current of electric capacity 48 and transistor 50,52 in setting second drive circuit 16, specification with USB 1.1 LS is an example, the rise time of output signal and fall time must be between 75ns-300ns, the scope of capacitive load is 150p-600p, and the output of positive and negative binary signal has different ohmic loads.According to this specification, the evaluation formula dV/dT=I/C of substitution electric capacity, wherein dV gets 0.8*Vdd, and Vdd=3.3V, dT get the geometrical mean 150ns of 75ns and 300ns, I extract operation electric current 25u, C=1.42p then, this capacitance is easy to realize on chip.Suppose that I is resultant by the reference non-essential resistance, can be controlled in 5% the error range, C can be realized by MOS transistor, error amount is in 10%, add Vdd 10% change is arranged, then under the situation that need not revise, just the transition slope can be controlled in 25% the error range, and have to 20% error by circuit simulation.
(PBIAS, NBIAS) as shown in Figure 4, Fig. 4 is the schematic diagram of the generation circuit in bias voltage signal source among Fig. 1 in first, second bias voltage signal source that above-mentioned second drive circuit 16 is received.The first bias voltage signal source (PBIAS) and the second bias voltage signal source (NBIAS) are from the upper level circuit of line drive circuit 10, mainly formed by a current mirror, wherein first bias voltage signal is taken out by the transistorized grid of a bias voltage PMOS, and second bias voltage signal is taken out by the grid of a bias voltage nmos pass transistor.First bias voltage signal and second bias voltage signal are used to provide the suitable operating voltage of second drive circuit 16.
Compared to known technology, line drive circuit of the present invention has multiple advantages, and the first, line drive circuit mainly comprises first drive circuit, retardation rate control circuit and three parts of second drive circuit, and circuit structure is simple to be realized easily; The second, have wide range of applications, line drive circuit so have very big elasticity in design, only need be revised the components values of part owing to simple in structure when being applicable to different size; The 3rd, line drive circuit can be controlled output signal accurately and change, and does not have the problem of assembly or the essential coupling of electric current; The 4th, by circuit simulation as can be known, the rise time of output signal and fall time symmetry, and crossover point (cross point) is about half position of voltage source; The 5th, even the output of line drive circuit connects very big capacitive load, or, can not cause very big influence to output signal as ohmic load yet.
The above only is preferred embodiment of the present invention, and all equalizations of doing according to claim of the present invention change and modify, and all should belong to the covering scope of patent of the present invention.
Claims (11)
1. the line drive circuit of an accurate retardation rate control, it comprises:
One retardation rate control circuit is used for the control lag rate, and it comprises:
One first operational amplifier, it comprises a positive input terminal, a negative input end, and an output; And
One second operational amplifier, it comprises the positive input terminal that a positive input terminal connects this first operational amplifier, one negative input end connects the negative input end of this first operational amplifier, wherein this first operational amplifier and this second operational amplifier are the operational amplifier of track to track input, and an output;
One first drive circuit is used for drive output signal, and it comprises:
One first current source, it comprises one first end and connects a voltage source, and one second end connects the positive input terminal of this first operational amplifier, and a control end connects output or this voltage source of this first operational amplifier via one first switch;
One second current source, it comprises the positive input terminal that one first end connects this second operational amplifier, and one second end connects an earth terminal, and a control end connects output or this earth terminal of this second operational amplifier via one second switch; And
One second drive circuit is used for setting the transition slope, and it comprises:
One electric capacity, it comprises the negative input end that one first end connects this first operational amplifier, and one second end connects this earth terminal;
One the 3rd current source, it comprises one first end and connects this voltage source, and one second end connects first end of this electric capacity, and a control end connects one first bias voltage signal source or this voltage source via one the 3rd switch; And
One the 4th current source, it comprises first end that one first end connects this electric capacity, and one second end connects this earth terminal, and a control end connects one second bias voltage signal source or this earth terminal via one the 4th switch.
2. line drive circuit as claimed in claim 1, wherein this first current source and the 3rd current source are the PMOS transistor, and its drain electrode is first end, and source electrode is second end, and grid is a control end.
3. line drive circuit as claimed in claim 1, wherein this second current source and the 4th current source are nmos pass transistor, and its drain electrode is first end, and source electrode is second end, and grid is a control end.
4. line drive circuit as claimed in claim 1, wherein this first switch comprises two switches, and the control end that is used for switching this first current source connects the output of this voltage source or this first operational amplifier.
5. line drive circuit as claimed in claim 1, wherein this second switch comprises two switches, and the control end that is used for switching this second current source connects the output of this earth terminal or this second operational amplifier.
6. line drive circuit as claimed in claim 1, wherein the 3rd switch comprises two switches, and the control end that is used for switching the 3rd current source connects this voltage source or this first bias voltage signal source.
7. line drive circuit as claimed in claim 1, wherein the 4th switch comprises two switches, and the control end that is used for switching the 4th current source connects this earth terminal or this second bias voltage signal source.
8. line drive circuit as claimed in claim 1, it also comprises one first electric capacity and one first resistance, is connected in series between the positive input terminal and output of first operational amplifier.
9. line drive circuit as claimed in claim 1, it also comprises one second electric capacity and second resistance, is connected in series between the positive input terminal and output of second operational amplifier.
One kind control line drive circuit as claimed in claim 1 method, it comprises the following step:
(a) switch first switch in this line drive circuit to the output of the control end that connects this first current source in this first operational amplifier;
Second switch to the connection of switching in this line drive circuit connects the control end of this second current source in this earth terminal;
Switch in this line drive circuit the 3rd switch to the control end that connects the 3rd current source in this first bias voltage signal source; And
Switch in this line drive circuit the 4th switch to the control end that connects the 4th current source in this earth terminal; And
(b) switch in this line drive circuit first switch to the control end that connects this first current source in this voltage source;
Switch second switch in this line drive circuit to the output of the control end that connects this second current source in this second operational amplifier;
Switch in this line drive circuit the 3rd switch to the control end that connects this second current source in this voltage source; And
Switch in this line drive circuit the 4th switch to the control end that connects the 4th current source in this second bias voltage signal source.
11. method as claimed in claim 10, wherein step (a) and (b) be to be executed in the different period.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200310120672 CN1274104C (en) | 2003-12-18 | 2003-12-18 | Circuit driving circuit with precision relay rate control |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200310120672 CN1274104C (en) | 2003-12-18 | 2003-12-18 | Circuit driving circuit with precision relay rate control |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1553619A CN1553619A (en) | 2004-12-08 |
| CN1274104C true CN1274104C (en) | 2006-09-06 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200310120672 Expired - Lifetime CN1274104C (en) | 2003-12-18 | 2003-12-18 | Circuit driving circuit with precision relay rate control |
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| CN (1) | CN1274104C (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102280908B (en) * | 2010-06-10 | 2013-09-11 | 力林科技股份有限公司 | Heterodyne slope frequency generation mode for light and heavy load switching of power supply |
| CN106603056B (en) * | 2011-12-31 | 2020-02-28 | 意法半导体研发(深圳)有限公司 | Analog signal soft switch control circuit with accurate current steering generator |
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2003
- 2003-12-18 CN CN 200310120672 patent/CN1274104C/en not_active Expired - Lifetime
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| Publication number | Publication date |
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| CN1553619A (en) | 2004-12-08 |
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Granted publication date: 20060906 |