CN1272802C - Circuit for raising sensing amplifier speed and its stability and its method - Google Patents
Circuit for raising sensing amplifier speed and its stability and its method Download PDFInfo
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- CN1272802C CN1272802C CN 01141556 CN01141556A CN1272802C CN 1272802 C CN1272802 C CN 1272802C CN 01141556 CN01141556 CN 01141556 CN 01141556 A CN01141556 A CN 01141556A CN 1272802 C CN1272802 C CN 1272802C
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Abstract
The present invention relates to a circuit and a method for raising sensing amplifier speed and stability. The circuit comprises a compensation current device and a discharge current device connected with a data node at one side of a transmission transistor, wherein a sensing node at the other side of the transmission transistor is connected with a charge current device and a leakage current device; the leakage current is reflected from the compensation current; the compensation current is used for maintaining the incomplete closure of the transmission transistor and controlling the data node not to exceed a definite voltage; thus, the present invention has the advantages that the speed of the sensing amplifier is increased, the stability of the sensing amplifier is enhanced by the leakage current, and the performance and the operation of the sensing amplifier are well controlled by the leakage current reflected from the compensating current.
Description
Technical field
The present invention relates to a kind of sensing amplifier (sense amplifier) that is used for semiconductor memory, or rather, relate to the circuit and the method for a kind of enhancement one sensing amplifier speed and stability.
Background technology
In the semiconductor storer, sensing amplifier is used to from storage unit (memory cell) reading of data, the speed of sensing amplifier and stability thereby dominated the performance of storer.Fig. 1 shows the basic framework (architecture) of a typical semiconductor memery circuit 10, it contains a cell array (cell array) 12 by many memory transistors (storage transistor) formation, for simplicity's sake, only draw storage unit partly among this figure typically.An one X demoder 14 and a Y demoder 16 are selected particular storage from the row and the column direction of cell array 12.From selection signal wire WL1, the WL2 of X demoder 14 ..., WLM is called character line (word line), and from selection signal wire YS1, the YS2 of Y demoder 16 ..., YSN is called bit line (bit line).Selecteed storage unit connects data line DL through bit line options transistor 18, and sensed from here amplifier 20 reads, thereby produces data-signal OUT at the output terminal of sensing amplifier 20.Fig. 2 illustrates the basic principle of operation of a sensing amplifier, and Fig. 3 then is its sequential chart (timing diagram).Sensing amplifier 22 contains a transmission transistor (transmission transistor) MN1 separates a back end VD and a sense node VZ, back end VD connects data line DL, so that the approach of reading cells to be provided, sense node VZ then sends data-signal OUT through an output stage X2, and the electric capacity sum total of seeing from back end VD and sense node VZ is expressed as C2 and C1.When selecteed storage unit is the transistor of a conducting, be called low state.Data line DL went up and a cell current Icell occurred this moment; Otherwise, when selecteed storage unit is a non-conduction transistor, be called high state.Cell current Icell on the data line DL is zero at this moment.When sensing amplifier 22 read low state, back end VD was discharged by cell current Icell, caused transmission transistor MN1 conducting one current sensor Isense, the voltage of sense node VZ thereby drop to a relative low-voltage.When sensing amplifier 22 read high state, cell current Icell was zero, and current sensor Isense is zero or atomic little, and sense node VZ remains on a relative high voltage.When reading low state, transmission transistor MN1 causes the time to postpone from being closed to open, and causes sensed speed lower, and, because the voltage on the back end VD is to the retroactive effect of transmission transistor MN1, the speed that makes transmission transistor MN1 be unlocked is slower.And when reading high state, may cause the improper unlatching of transmission transistor MN1, thereby produce unsettled action because of noise.In addition, back end VD may be overcharged and makes its voltage rise to a quite high voltage after read cycle repeatedly, and the speed that so will cause transmission transistor MN1 to be unlocked more reduces, and causes sensed speed slower.
For increasing the stability of sensing amplifier, one conventional art is to sense node VZ additional charge, as shown in Figure 4, this sensing amplifier 24 is added into a current device, its sequential chart is in Fig. 5, transistor MP2 is provided a bias voltage BIAS and produces a leakage current (leakage current) Ileakage and is supplied to sense node VZ, thereby obtains preferable stability.
As shown in Figure 6, another conventional art increases by a discharge current device MN3 and connects back end VD through a switch MN2 in sensing amplifier 26, its sequential chart is in Fig. 7, and sensing amplifier 26 in advance to data node VD discharge, is unlocked to quicken transmission transistor MN1 between precharge phase.
The improvement sensing amplifier of people such as Smarandoiu in No. the 5390147th, United States Patent (USP) increases by a lubricated current mirror and connects back end and reference mode, and utilizes the feedback of reference current mirror, to improve the speed of sensing amplifier.Yet, arrange so to make that lubricated electric current and reference current influence current sensor through feedback path, when nonideal situation occurs, for example the difference of manufacture process causes the change of reference current, to cause current sensor to change, thereby it is slack-off that sensed speed takes place, even the sensing result mistake takes place.Therefore, need further improve sensing amplifier.
Summary of the invention
The purpose of this invention is to provide a kind of improved sensing amplifier, to promote its sensed speed and stability, it is that back end in transmission transistor one side connects an offset current device (offsetcurrent apparatus), transmission transistor is not fully closed and back end is no more than certain voltage by offset current, thereby promotes the speed of sensing amplifier; The sense node of transmission transistor opposite side then connects a leakage current device, to promote the stability of sensing amplifier.Utilize current mirror to produce leakage current, make the operation of sensing amplifier and performance obtain good control from the offset current mirror.Back end connects a discharge current device in addition, to offset the leakage current that imports transmission transistor.
Circuit of the present invention is achieved in that a kind of circuit of promoting sensing amplifier speed and stability, this sensing amplifier contains a transmission transistor and has an input end and an output terminal, this output terminal sense node that is coupled, this input end is coupled a back end to connect a data line, the store status of sensing one storage unit, and send a data-signal through an output stage from this sense node, it is characterized in that: this circuit comprises: first current mirror, contain first and second branch, with from this first branch mirror one intermediate current in this second branch, this first branch comprises a first transistor, this second branch comprises a transistor seconds, this first and second transistor respectively has one source pole, one leakage is drawn and a grid, described two source grounds, described two grids are connected to each other, the drain electrode of described the first transistor connects its grid, insert an offset current device between this first branch and this back end, be controlled by first control signal and conducting one offset current, this offset current device comprises one the 3rd transistor and has one source pole, one drain electrode and a grid, described drain electrode connects this back end, described grid connects a bias voltage signal, and described source electrode connects the drain electrode of this transistor seconds; Second current mirror, contain the 3rd and the 4th branch, the 3rd branch comprises one the 4th transistor, the 4th branch comprises one the 5th transistor, the the 4th and the 5th transistor respectively has one source pole, a leakage is drawn and a grid, described two source electrodes connect a supply voltage, described the 4th transistor drain connects its grid, described the 5th transistor drain connects this sense node, the 4th branch this sense node that is coupled, this intermediate current of the 3rd branching adaptation and mirror one leakage current are in the 4th branch; And charging current device this sense node that is coupled, and be controlled by the anti-phase input of second control signal and conducting one charging current.
Wherein this first control signal is a supply voltage.
Wherein to have mirror ratio be 1 to 1 to 3 to 4 to this first current mirror.
Wherein to have mirror ratio be 1 to 1 to this second current mirror.
Wherein this offset current is 1 to 1 to 3 to 4 to this leakage current ratio.
Comprise that more a discharge current device inserts between first branch of this back end and this first current mirror, and be controlled by the 3rd control signal and conducting one discharge current.
Wherein the 3rd control signal is the complementation of this second control signal.
Wherein this charging current is 5 to 1 to 10 to 1 to this discharge current ratio.
More comprise this transmission transistor common gate of intermediary's transistor AND gate, and its source electrode is connected second branch of this first current mirror and the 3rd branch of this second current mirror respectively with drain electrode.
Circuit of the present invention also can be achieved in that a kind of circuit of promoting sensing amplifier speed and stability, this sensing amplifier contains a transmission transistor and has an one source pole and a drain electrode, this drain electrode is as a sense node, this source electrode as a back end to connect a data line, the store status of sensing one storage unit, and send a storage signal through an output stage from this sense node, it is characterized in that: this circuit comprises: the first transistor, have one source pole, a drain electrode and a grid, this drain electrode connects this back end, and this grid connects a bias voltage signal; First current mirror that second and third transistor is formed, this second and third transistor respectively has one source pole, a drain electrode and a grid, these two source grounds, these two grids are connected to each other, and the drain electrode of this transistor seconds connects the source electrode of its grid and this first transistor; The 4th transistor has one source pole, a drain electrode and a grid, and this source electrode connects the 3rd transistor drain, and this grid connects the grid of this transmission transistor; Second current mirror that the 5th and the 6th transistor is formed, the the 5th and the 6th transistor respectively has one source pole, a drain electrode and a grid, these two source electrodes connect a supply voltage, these two grids are connected to each other, the 5th transistor drain connects its grid and the 4th transistor drain, and the 6th transistor drain connects this sense node; And the 7th transistor, having one source pole, a drain electrode and a grid, this source electrode connects supply voltage, and this drain electrode connects this sense node, and this grid connects the anti-phase input of the complementary signal of a precharging signal.
Wherein this second and third transistorized size is than being 1 to 1 to 3 to 1.
Wherein the 5th and the 6th transistorized size is than being 1 to 1.
Wherein the current ratio of this second and the 6th transistor turns is 1 to 1 to 3 to 1.
More comprise the 8th transistor, have one source pole, a drain electrode and a grid, this drain electrode connects this back end, and this grid connects this precharging signal.
Wherein the current ratio of the 7th and the 6th transistor turns is 5 to 1 to 10 to 1.
Method of the present invention is achieved in that a kind of method of promoting sensing amplifier speed and stability, this sensing amplifier contains a transmission transistor and has an input end and an output terminal, this output terminal sense node that is coupled, this input end is coupled a back end to connect a data line, the store status of sensing one storage unit, and send a data-signal through an output stage from this sense node, it is characterized in that: this method comprises the following steps: to utilize an offset current device provisioning one offset current to this back end, and this transmission transistor is not exclusively closed and this back end is no more than certain voltage to keep; By one first this offset current of current mirror mirror, produce an intermediate current; By one second this intermediate current of current mirror mirror, to produce a leakage current this sense node that is coupled; And the charging current device of this sense node of control coupling produces a charging current to this sense node.
More comprise and impose on a bias voltage to control this offset current.
Comprise that more the complementary signal that imposes on a precharging signal is to control this charging current.
Wherein this offset current is 1 to 1 to 3 to 4 to the leakage current ratio.
Comprise that more coupling one discharge current is to this back end.
More comprise and impose on a precharging signal to control this discharge current.
Wherein this charging current is 5 to 1 to 10 to 1 to the discharge current ratio.
More comprise this transmission transistor common gate of coupling one intermediary's transistor AND gate, to open or to close the path of this offset current of mirror and discharge current.
Description of drawings
Fig. 1 is the basic framework figure of a typical semiconductor memery circuit;
Fig. 2 is the sense amplifier figure among Fig. 1;
Fig. 3 is the sequential chart of the circuit among Fig. 2;
Fig. 4 is that a traditional sensing amplifier has the improvement circuit of promoting stability;
Fig. 5 is the sequential chart of the circuit among Fig. 4;
Fig. 6 is the improvement circuit that a traditional sensing amplifier has enhancement speed;
Fig. 7 is the sequential chart of the circuit among Fig. 6;
Fig. 8 is a preferred embodiment circuit diagram of the present invention;
Fig. 9 is the sequential chart of the circuit among Fig. 8.
Embodiment
Shown in Figure 8 is sense amplifier according to preferred embodiment of the present invention, and its sequential chart is presented among Fig. 9.Sensing amplifier as conventional art, sensing amplifier 28 shown here contains a transmission transistor MN1, have one source pole as input end, connect a back end VD, to connect data line DL from storage unit, one drain electrode is as output terminal, connect a sense node VZ, and a grid is as control end, connected node VX, and the signal of the complementary signal SEB of sensing enable signal and back end VD produces control signal to node VX through rejection gate X1, to handle transmission transistor MN1.After transmission transistor MN1 opens, go up the cell current Icell of circulation by data line DL, the store status of sensing cell, and on sense node VZ, produce corresponding voltage, and send a storage signal OUT through phase inverter X2.
As in traditional technology, sensing amplifier 28 also contains a charging current device with improvement speed, as shown in Figure 8, one transistor MP1 has one source pole and connects a supply voltage VDD, one drain electrode connects sense node VZ, and a grid connects the anti-phase input of the complementary signal PREB of a precharging signal.When transistor MP1 was opened by signal PREB, a charging current Icharge was supplied to sense node VZ and back end VD, finishing the preparation of beginning sensing, and shortened the sensing time.
For further improving sensed speed, one offset current device connects back end VD, as shown in FIG., one transistor MN4 has a drain electrode and connects back end VD, and a grid connects a supply voltage VDD, thereby produces an offset current Ioffset, the size of this offset current Ioffset is about 4 microamperes to 6 microamperes, be not fully closed to keep transmission transistor MN1, and the voltage of back end VD kept be no more than a specific voltage, so increase sensed speed.Different with previous described conventional art, this offset current Ioffset is control transmission transistor MN1 independently, and it is irrelevant with memory reference cell or reference current, therefore be not subjected to the influence of other factors, and, offset current Ioffset is that for circuit designers, this characteristic can be chosen individually by transistor MN4 size and grid bias decision thereof.
Use a pair of current mirror to be supplied to sense node VZ with reference to offset current Ioffset to produce leakage current, this comprises that to current mirror a principal current mirror (master current mirror) and is from current mirror (slave current mirror).The principal current mirror is made of transistor MN3 and MN5, and the grid of the two is connected to each other, and connects the drain electrode of transistor MN3, the source ground of the two.The input end of principal current mirror also is the drain electrode of transistor MN3, connects the source electrode of transistor MN4, to receive offset current Ioffset.Because the cause of the mirror of principal current mirror, transistor MN5 conducting one electric current I m1, offset current Ioffset to mirror electric current I m1 than being that size by transistor MN3 and MN5 is than determining that in this embodiment, its value is about 1 to 1 to 3 to 4.On the other hand, be made of transistor MP3 and MP2 from current mirror, the source electrode of the two connects supply voltage VDD, and the grid of the two is connected to each other, and connects the drain electrode of transistor MP3, and the drain electrode of transistor MP2 then connects sense node VZ.Principal current mirror and from inserting a transistor MN6 between the current mirror, itself and transmission transistor MN1 common gate, its source electrode connects the output terminal of principal current mirror, i.e. the drain electrode of transistor MN5, it drains and then connects input end from current mirror, i.e. the drain electrode of transistor MP3.When transistor MN6 opens, because the electric current of transistor MN5 conducting is Im1, so also conducting electric current I of transistor MP3 m1, because cause from the mirror of current mirror, one leakage current Ileakage is supplied to sense node VZ at transistor MP2 mirror, and electric current I m1 to the leakage current Ileakage t of mirror than be size by transistor MP3 and MP2 than decision, in this embodiment, its value is about 1 to 1.Otherwise in case transistor MN6 closes, the principal current mirror reaches will lose above-mentioned effect from current mirror.Leakage current Ileakage can also promptly promote the stability of sensing amplifier 28 to the noise in the reactive circuit to the lasting charging of sense node VZ, and the big young pathbreaker of leakage current Ileakage determines the ability of sense node VZ to interference resistant.Because the principal current mirror reaches from current mirror and produces corresponding relation by electric current I m1, therefore the relation that has a ratio between leakage current Ileakage and the offset current Ioffset, its ratio is that the big or small ratio by the big or small ratio of transistor MN3 and MN5 and transistor MP3 and MP2 decides, in this embodiment, offset current Ioffset is about 1 to 1 to 3 to 4 to the ratio of leakage current Ileakage.Different with previous described conventional art, this sensing amplifier 28 utilizes leakage current Ileakage to increase stability, and this leakage current Ileakage gives birth to from offset current Ioffset mirror, therefore the size of leakage current Ileakage and the size of offset current Ioffset have certain proportionate relationship, the condition of suitable side circuit can be provided, be not subjected to other factors, for example the influence of manufacture process.
Back end VD connects a discharge current device in addition, also is transistor MN2, and its source electrode connects the input end of principal current mirror, also is the drain electrode of transistor MN3, and its grid then connects precharging signal PRE.When transistor MN2 is opened by signal PRE, its conducting one discharge current Idischarge, its size is suitable with leakage current Ileakage, to offset each other.
When the sensing low state, it also is the storage unit of conducting, on data line DL, there is a cell current Icell to flow towards selecteed storage unit from back end VD, this moment, back end VD was discharged by electric current I cell, thereby on transmission transistor MN1, cause a current sensor Isense, and then on sense node VZ, produce relative low-voltage.On the contrary, when the sensing high state, it also is non-conduction storage unit, then the electric current I cell that flows to storage unit from back end VD is zero, sense node VZ will maintain a relative high voltage this moment, even this moment storage unit or the remaining a small amount of noise electric current of data line DL, transistor MP2 will provide a leakage current Ileakage to offset its influence, so can improve the degree of stability and the interference resistant ability of sensing amplifier.
When back end VD is recharged, because the existence of offset current Ioffset, making that back end VD is unlikely is overcharged, therefore, voltage on the back end VD will be maintained at below the specific voltage, and promptly the summation of the gate-to-source pressure reduction VGS of the drain electrode of transistor MN4-source electrode pressure reduction VDS and transistor MN3 is about 1.0 volts, so, the sensed speed in next read cycle will can not slowed down.Even do not have current flowing on data line DL, offset current Ioffset still keeps transmission transistor MN1 and is not fully closed, and in next read cycle, will promote sensed speed because of the very fast opening speed of transmission transistor MN1.
In a sense period, as shown in Figure 9, between its precharge phase, the transistor MP1 of charging current device is opened by signal PREB, and conducting one charging current Icharge is to sense node VZ and back end VD charging, and the transistor MN2 of discharge current device is opened by signal PRE, conducting one discharge current Idischarge to data node VD discharge, overcharges back end VD to prevent charging current Icharge moment.After between precharge phase, back end VD also is that the voltage on the data line DL descends gradually, and after it is reduced to certain voltage, the control signal VX that rejection gate X1 produces will rise, and the voltage of sense node VZ is descended rapidly, thereby produces data-signal OUT.
Claims (23)
1, a kind of circuit of promoting sensing amplifier speed and stability, this sensing amplifier contains a transmission transistor and has an input end and an output terminal, this output terminal sense node that is coupled, this input end is coupled a back end to connect a data line, the store status of sensing one storage unit, and send a data-signal through an output stage from this sense node, it is characterized in that: this circuit comprises: first current mirror, contain first and second branch, with from this first branch mirror one intermediate current in this second branch, this first branch comprises a first transistor, this second branch comprises a transistor seconds, this first and second transistor respectively has one source pole, one leakage is drawn and a grid, described two source grounds, described two grids are connected to each other, the drain electrode of described the first transistor connects its grid, insert an offset current device between this first branch and this back end, be controlled by first control signal and conducting one offset current, this offset current device comprises one the 3rd transistor and has one source pole, one drain electrode and a grid, described drain electrode connects this back end, described grid connects a bias voltage signal, and described source electrode connects the drain electrode of this transistor seconds; Second current mirror, contain the 3rd and the 4th branch, the 3rd branch comprises one the 4th transistor, the 4th branch comprises one the 5th transistor, the the 4th and the 5th transistor respectively has one source pole, a leakage is drawn and a grid, described two source electrodes connect a supply voltage, described the 4th transistor drain connects its grid, described the 5th transistor drain connects this sense node, the 4th branch this sense node that is coupled, this intermediate current of the 3rd branching adaptation and mirror one leakage current are in the 4th branch; And charging current device this sense node that is coupled, and be controlled by the anti-phase input of second control signal and conducting one charging current.
2, the circuit of enhancement sensing amplifier speed according to claim 1 and stability, it is characterized in that: wherein this first control signal is a supply voltage.
3, the circuit of enhancement sensing amplifier speed according to claim 1 and stability, it is characterized in that: wherein to have mirror ratio be 1 to 1 to 3 to 4 to this first current mirror.
4, the circuit of enhancement sensing amplifier speed according to claim 1 and stability, it is characterized in that: wherein to have mirror ratio be 1 to 1 to this second current mirror.
5, the circuit of enhancement sensing amplifier speed according to claim 1 and stability, it is characterized in that: wherein this offset current is 1 to 1 to 3 to 4 to this leakage current ratio.
6, the circuit of enhancement sensing amplifier speed according to claim 1 and stability, it is characterized in that: comprise that more a discharge current device inserts between first branch of this back end and this first current mirror, and be controlled by the 3rd control signal and conducting one discharge current.
7, the circuit of enhancement sensing amplifier speed according to claim 6 and stability is characterized in that: wherein the 3rd control signal is the complementation of this second control signal.
8, the circuit of enhancement sensing amplifier speed according to claim 6 and stability, it is characterized in that: wherein this charging current is 5 to 1 to 10 to 1 to this discharge current ratio.
9, the circuit of enhancement sensing amplifier speed according to claim 1 and stability, it is characterized in that: more comprise this transmission transistor common gate of intermediary's transistor AND gate, and its source electrode is connected second branch of this first current mirror and the 3rd branch of this second current mirror respectively with drain electrode.
10, a kind of circuit of promoting sensing amplifier speed and stability, this sensing amplifier contains a transmission transistor and has an one source pole and a drain electrode, this drain electrode is as a sense node, this source electrode as a back end to connect a data line, the store status of sensing one storage unit, and send a storage signal through an output stage from this sense node, it is characterized in that: this circuit comprises: the first transistor, have one source pole, a drain electrode and a grid, this drain electrode connects this back end, and this grid connects a bias voltage signal; First current mirror that second and third transistor is formed, this second and third transistor respectively has one source pole, a drain electrode and a grid, these two source grounds, these two grids are connected to each other, and the drain electrode of this transistor seconds connects the source electrode of its grid and this first transistor; The 4th transistor has one source pole, a drain electrode and a grid, and this source electrode connects the 3rd transistor drain, and this grid connects the grid of this transmission transistor; Second current mirror that the 5th and the 6th transistor is formed, the the 5th and the 6th transistor respectively has one source pole, a drain electrode and a grid, these two source electrodes connect a supply voltage, these two grids are connected to each other, the 5th transistor drain connects its grid and the 4th transistor drain, and the 6th transistor drain connects this sense node; And the 7th transistor, having one source pole, a drain electrode and a grid, this source electrode connects supply voltage, and this drain electrode connects this sense node, and this grid connects the anti-phase input of the complementary signal of a precharging signal.
11, the circuit of enhancement sensing amplifier speed according to claim 10 and stability is characterized in that: wherein this second and third transistorized size is than being 1 to 1 to 3 to 1.
12, the circuit of enhancement sensing amplifier speed according to claim 10 and stability is characterized in that: wherein the 5th and the 6th transistorized size is than being 1 to 1.
13, the circuit of enhancement sensing amplifier speed according to claim 10 and stability, it is characterized in that: wherein the current ratio of this second and the 6th transistor turns is 1 to 1 to 3 to 1.
14, the circuit of enhancement sensing amplifier speed according to claim 10 and stability is characterized in that: more comprise the 8th transistor, have one source pole, a drain electrode and a grid, this drain electrode connects this back end, and this grid connects this precharging signal.
15, the circuit of enhancement sensing amplifier speed according to claim 14 and stability, it is characterized in that: wherein the current ratio of the 7th and the 6th transistor turns is 5 to 1 to 10 to 1.
16, a kind of method of promoting sensing amplifier speed and stability, this sensing amplifier contains a transmission transistor and has an input end and an output terminal, this output terminal sense node that is coupled, this input end is coupled a back end to connect a data line, the store status of sensing one storage unit, and send a data-signal through an output stage from this sense node, it is characterized in that: this method comprises the following steps: to utilize an offset current device provisioning one offset current to this back end, and this transmission transistor is not exclusively closed and this back end is no more than certain voltage to keep; By one first this offset current of current mirror mirror, produce an intermediate current; By one second this intermediate current of current mirror mirror, to produce a leakage current this sense node that is coupled; And the charging current device of this sense node of control coupling produces a charging current to this sense node.
17, the method for enhancement sensing amplifier speed according to claim 16 and stability is characterized in that: more comprise imposing on a bias voltage to control this offset current.
18, the method for enhancement sensing amplifier speed according to claim 16 and stability is characterized in that: comprise that more the complementary signal that imposes on a precharging signal is to control this charging current.
19, the method for enhancement sensing amplifier speed according to claim 16 and stability, it is characterized in that: wherein this offset current is 1 to 1 to 3 to 4 to the leakage current ratio.
20, the method for enhancement sensing amplifier speed according to claim 16 and stability is characterized in that: comprise that more coupling one discharge current is to this back end.
21, the method for enhancement sensing amplifier speed according to claim 20 and stability is characterized in that: more comprise imposing on a precharging signal to control this discharge current.
22, the method for enhancement sensing amplifier speed according to claim 20 and stability, it is characterized in that: wherein this charging current is 5 to 1 to 10 to 1 to the discharge current ratio.
23, the method for enhancement sensing amplifier speed according to claim 16 and stability is characterized in that: more comprise this transmission transistor common gate of coupling one intermediary's transistor AND gate, to open or to close the path of this offset current of mirror and discharge current.
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| CN 01141556 CN1272802C (en) | 2001-10-15 | 2001-10-15 | Circuit for raising sensing amplifier speed and its stability and its method |
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| CN 01141556 CN1272802C (en) | 2001-10-15 | 2001-10-15 | Circuit for raising sensing amplifier speed and its stability and its method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US7478294B2 (en) * | 2005-06-14 | 2009-01-13 | Etron Technology, Inc. | Time controllable sensing scheme for sense amplifier in memory IC test |
| US7851947B2 (en) * | 2007-11-05 | 2010-12-14 | Qualcomm, Incorporated | Methods and apparatuses for selectable voltage supply |
| ATE557395T1 (en) * | 2008-07-28 | 2012-05-15 | Nxp Bv | CURRENT MEASUREMENT AMPLIFIER WITH FEEDBACK LOOP |
| US8531902B2 (en) * | 2011-06-30 | 2013-09-10 | Qualcomm Incorporated | Sensing circuit |
| US9070424B2 (en) * | 2012-06-29 | 2015-06-30 | Samsung Electronics Co., Ltd. | Sense amplifier circuitry for resistive type memory |
| US10475510B2 (en) * | 2017-12-21 | 2019-11-12 | Macronix International Co., Ltd. | Leakage compensation read method for memory device |
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